JPH01160040A - Substrate element with bump and manufacture thereof - Google Patents
Substrate element with bump and manufacture thereofInfo
- Publication number
- JPH01160040A JPH01160040A JP62317568A JP31756887A JPH01160040A JP H01160040 A JPH01160040 A JP H01160040A JP 62317568 A JP62317568 A JP 62317568A JP 31756887 A JP31756887 A JP 31756887A JP H01160040 A JPH01160040 A JP H01160040A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- bump
- substrate
- bonding
- substrate element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000009792 diffusion process Methods 0.000 claims abstract description 25
- 238000002161 passivation Methods 0.000 claims abstract description 8
- 230000004913 activation Effects 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 abstract description 20
- 230000000694 effects Effects 0.000 abstract description 7
- 230000002950 deficient Effects 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- 230000035939 shock Effects 0.000 abstract description 2
- 229910045601 alloy Inorganic materials 0.000 abstract 2
- 239000000956 alloy Substances 0.000 abstract 2
- 229910002677 Pd–Sn Inorganic materials 0.000 abstract 1
- 229910018594 Si-Cu Inorganic materials 0.000 abstract 1
- 229910008465 Si—Cu Inorganic materials 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- 238000007747 plating Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- 230000001105 regulatory effect Effects 0.000 description 3
- 150000003376 silicon Chemical class 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 2
- 238000005238 degreasing Methods 0.000 description 2
- 238000010992 reflux Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 241000282472 Canis lupus familiaris Species 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- 229910020174 Pb-In Inorganic materials 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 239000004115 Sodium Silicate Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 239000013040 bath agent Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
- 229910000029 sodium carbonate Inorganic materials 0.000 description 1
- 235000019795 sodium metasilicate Nutrition 0.000 description 1
- NTHWMYGWWRZVTN-UHFFFAOYSA-N sodium silicate Chemical compound [Na+].[Na+].[O-][Si]([O-])=O NTHWMYGWWRZVTN-UHFFFAOYSA-N 0.000 description 1
- 229910052911 sodium silicate Inorganic materials 0.000 description 1
- 238000003756 stirring Methods 0.000 description 1
- 239000004094 surface-active agent Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は集積回路等に好適するバンプを有する基板素子
に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a substrate element having bumps suitable for integrated circuits and the like.
（従来の技術）
集積回路やこれに類似する回路素子は高密度に並べられ
た多数の回路部品、電極等を一枚の基板上に夫々規制し
て配置して作られている。この素子の特徴は小さい基板
で集積度の高い回路が構成されていることであるが、内
部における各回路同志は、写真製版等の手段で効果的に
接続できるけれども他の素子との接続に関しては一般的
にリードフレームと呼称される端子を介して接続される
。(Prior Art) Integrated circuits and similar circuit elements are made by arranging a large number of circuit components, electrodes, etc. arranged at high density in a controlled manner on a single substrate. A feature of this device is that highly integrated circuits are constructed on a small substrate, and although each circuit inside can be effectively connected to each other by means such as photolithography, connections with other devices are difficult. They are connected via terminals commonly called lead frames.
従って上記回路とリードフレームの端子とは第４図に示
すように基板４１に多数形成された電極４２に活性化層
４３を介してバンプ４４が接続されているのが普通であ
る。Therefore, as shown in FIG. 4, the terminals of the circuit and lead frame are usually connected to a plurality of electrodes 42 formed on a substrate 41 via activation layers 43 to bumps 44.
ところで、上記リードフレームの端子４５に対するバン
プ４４はリードフレームの端子４５との接合、あるいは
バンプと電極との接合を電気的及び機械的に完全な接合
をしなければならない。By the way, the bumps 44 to the terminals 45 of the lead frame must be electrically and mechanically completely joined to the terminals 45 of the lead frame, or the bumps and the electrodes.
しかしながら、従来においては、しばしば問題が生ずる
場合がある。例えばバンプと電極との接着が不完全のた
めに、この部分の接触不良が発生したシ、あるいはバン
プの形成が出来なかったり（電極４にメツキ等の手段で
バンプを接着形成する）する。一方出来たバンプにリー
ドフレームの端子４５を接続する場合にボンデング技術
を用いることが多いが、このボンディングによる機械的
衝撃が電極４２及び基板４１にまで及ぶ場合があシ、こ
れの発生の主たる原因はバンプの肉の量がボンディング
に対して十分であってしかも規制された形状に形成され
ていないからである。However, problems often occur in the prior art. For example, due to incomplete adhesion between the bump and the electrode, poor contact may occur in this portion, or the bump may not be formed (the bump may be adhesively formed on the electrode 4 by plating or other means). On the other hand, bonding technology is often used when connecting the terminal 45 of the lead frame to the formed bump, but the mechanical shock caused by this bonding may extend to the electrode 42 and the substrate 41, and this is the main cause of this occurrence. This is because the amount of bump flesh is sufficient for bonding, and it is not formed into a regulated shape.
（発明が解決しようとする問題点）
本発明は上記従来の欠点を除去するためにバンプと電極
との接着部（面）に工夫をしだものである。(Problems to be Solved by the Invention) In order to eliminate the above-mentioned conventional drawbacks, the present invention devises the adhesive portion (surface) between the bump and the electrode.
すなわち、電極の一部であるバンプ接合部を対応するバ
ンプ金属材に対するぬれ効果を最大限に発輝出来るよう
に拡散層を形成することによってこの部分に接合する（
メツキ手段）金属の接着を容易にする。この接着の容易
性が向上すると接着金属のバンプ形状が整って来るし、
多数あるバング全体の形状が揃って均一になるという特
徴を巧みに利用したものである。このようにすると夫々
のバンプの量（肉厚、巾）が一定に容易に規制すること
が可能となるのでボンディングに必要な肉厚（量）を能
率よく形成でき、電極や基板への影響をほとんどなくす
ことが可能となった。That is, the bump bonding part, which is a part of the electrode, is bonded to this part by forming a diffusion layer so as to maximize the wetting effect on the corresponding bump metal material (
Plating means) Facilitates adhesion of metals. As the ease of bonding improves, the bump shape of the bonded metal becomes more regular,
This skillfully utilizes the feature that the entire shape of many bangs is uniform. In this way, the amount (thickness, width) of each bump can be easily regulated to a constant value, so the thickness (amount) required for bonding can be efficiently formed, and the effect on the electrodes and substrate can be reduced. It has become possible to almost eliminate it.
（問題を解決するための手段と作用）
本発明は、上記の様に電極の一部を拡散して作った拡散
活性化層を形成することを特徴とするものである。(Means and effects for solving the problem) The present invention is characterized in that a diffusion activation layer is formed by diffusing a part of the electrode as described above.
この拡散活性化層の厚さは約５０人〜１μｍまでの間で
形成することが出来る。５０Ａ以下ではバンプのぬれが
十分ではなく５〜１０チの不良品が出る、しかし５０先
を越えると不思義と不良品がほとんど皆無となる。しか
し最良範囲は約１００Ｘ〜１０００＾とすることも解明
されている。例えばバンプ材料として比較的高い温度で
浴融する半田を用いる場合は高温のだめ拡散活性化層と
の反応が早いので１μｍと厚くすることが望ましい。The thickness of this diffusion activation layer can be formed to be between about 50 and 1 μm. Below 50A, the bumps are not sufficiently wetted, resulting in 5 to 10 defective products.However, if the contact exceeds 50A, almost no defective products occur. However, it has also been determined that the best range is approximately 100X to 1000^. For example, when using solder that melts in a bath at a relatively high temperature as the bump material, it is desirable to have a thickness of 1 μm because the reaction with the diffusion activation layer is rapid at high temperatures.
従ってバンプの材料によって拡散活性化層を調整するこ
とが必要である。Therefore, it is necessary to adjust the diffusion activation layer depending on the material of the bump.
また、拡散活性化層を形成する際に、Ｐｄを電極表面に
メツキあるいは蒸着等で被着してから加熱してｐｄとＡ
ｌとを拡散するものであるが、この温度は約２００〜１
０００℃の範囲で調整すればよい。この加熱温度の調整
は電極が形成されている基板の材料によって決定すれば
よい。なお最良温度は３００°Ｃ〜６００℃で行なわれ
る。上記Ｐｄの電極表面へのメツキに関してはＰｄのパ
ッシベーション膜への不所望な付着が生ずる場合にはこ
れの抑制剤を用いて抑制する。このようにすれば正確な
模様の電極の拡散活性化層を形成することが可能である
。In addition, when forming the diffusion activation layer, Pd is deposited on the electrode surface by plating or vapor deposition, and then heated to form the Pd and A
This temperature is approximately 200 to 1
The temperature may be adjusted within the range of 000°C. Adjustment of this heating temperature may be determined depending on the material of the substrate on which the electrodes are formed. Note that the best temperature is 300°C to 600°C. Regarding the plating of Pd on the electrode surface, if undesirable adhesion of Pd to the passivation film occurs, this is suppressed using a suppressor. In this way, it is possible to form an electrode diffusion activation layer with an accurate pattern.
更にｐｄに代えてＺｎで拡散し、拡散活性化層を形成し
てもよい。一方半田材料としてＰｂ−Ｉｎ。Furthermore, instead of PD, Zn may be diffused to form a diffusion activation layer. On the other hand, Pb-In is used as a solder material.
８ｍ−Ｚｎ、Ｂ１−Ｉｎ、Ｐｂ−８ｎ系を用イルとよい
。8m-Zn, B1-In, and Pb-8n systems are preferably used.
この拡散活性化層は極めて便利なものでまずその作用と
しては、バンプ金属との接合を極めて容易にすることを
主とするが、この他に、この電極部表面のみぬれ性が極
めて長幼になってバンプ金属がこの部分に集中して接着
（蒸着、付着）するのでパターン切れが向上するから、
隣接する電極（電極同志）との間隙を狭く出来るので微
細なパターン形成に好適であるという他の効果も兼ね備
えている。This diffusion activation layer is very convenient, and its main function is to make it extremely easy to bond with the bump metal, but it also makes the wettability of the electrode surface extremely long. Since the bump metal is concentrated on this area and adheres (deposited, adhered), pattern cutting is improved.
Another effect is that the gap between adjacent electrodes (electrodes) can be narrowed, making it suitable for forming fine patterns.
また、従来のようにバンプと電極とを他の金属による特
別な活性層４３を形成することが不要となるのでその分
だけ、材料及び工程が少々くてすみ安価なバンプを有す
る基板素子を提供することが可能である。In addition, since it is not necessary to form a special active layer 43 made of another metal between bumps and electrodes as in the past, the materials and processes are slightly more expensive, thereby providing a substrate element with inexpensive bumps. It is possible to do so.
（実施例）
（１）第１図は本発明のバンプを有する基板素子の要部
を断面して示すもので、表面に絶縁物２を被着しだＳ
ｉ Ｏ２製の基板ｌと、この基板ｌの絶縁物２の上には
夫々所定の間隙を持たせたＡｌを主成分とする多数の電
極４と、これ等電極間には窒化シリコンより成るパッシ
ベーション膜３が形成されている。(Example) (1) Figure 1 is a cross-sectional view of the main part of a substrate element having bumps according to the present invention.
i A substrate l made of O2 and an insulator 2 of this substrate l are provided with a number of electrodes 4 mainly made of Al with predetermined gaps between them, and a passivation layer made of silicon nitride between these electrodes. A film 3 is formed.
上記電極４はその大部分がｋｔを主成分とするＡｌ−８
ｉ−Ｃｕ合金で形成されているがその一部である後述す
るバンプとの接着面には、第２図に示すようにＰｄ−、
Ａｌの拡散活性層６が形成されている。この電極４の上
にはＰｂ−Ｓｎ系合金半田より成る厚さ約２５μｍのバ
ンプ５を形成してバンプを有する基板素子１０を構成し
て成る。The electrode 4 is mostly Al-8 whose main component is kt.
Although it is made of i-Cu alloy, the adhesion surface with bumps, which will be described later, is a part of the i-Cu alloy, as shown in Figure 2, Pd-,
A diffusion active layer 6 of Al is formed. On this electrode 4, a bump 5 made of Pb--Sn alloy solder and having a thickness of approximately 25 μm is formed to constitute a substrate element 10 having a bump.
（２）基板１の上に絶縁物２を形成し、この上の一部に
Ｚｎ及びＡｌの拡散活性化層６を有する多数の電極４を
形成し、この電極４を隔離するためのパッシベーション
膜３を設ける。上記各電極４の拡散活性化層６の表面に
接着された８ ｎ −Ｚ ｎ系半田より成る厚さ約３０
μｍのバンプ５を形成してバンプを有する基板素子１０
を構成して成る。(2) An insulator 2 is formed on a substrate 1, a large number of electrodes 4 having a diffusion activation layer 6 of Zn and Al are formed on a part of the insulator 2, and a passivation film is formed to isolate the electrodes 4. 3 will be provided. Approximately 30 mm thick made of 8n-Zn solder adhered to the surface of the diffusion activation layer 6 of each electrode 4.
A substrate element 10 having bumps formed with μm bumps 5
It consists of
上記各実施例においては拡散活性化層６の作用により、
バンプとの接合が極めてよく電極上に形成される多数の
バンプは極めて均一な量、すなわちバンプの高さをボン
デング時に好適な２５μｍ〜３０μｍの範囲に完全に納
めることが出来た。In each of the above embodiments, due to the action of the diffusion activation layer 6,
The large number of bumps formed on the electrode had excellent bonding with the bumps, and the height of the bumps could be completely kept within a suitable range of 25 μm to 30 μm during bonding.
上記ボンデングは各電極と各リードフレーム端子とで行
なわれるがこれが完全となシ、多数の各チップ（１チツ
プは６４個の８０μｍ四方の電極を有するもの）毎の接
続不良は完全になくなり、しかもボンデング時の機械的
衝撃による電極及び基板のクラックもなくなったことが
確認された。The above bonding is performed between each electrode and each lead frame terminal, but this is perfect, and connection failures for each of many chips (one chip has 64 80 μm square electrodes) are completely eliminated. It was confirmed that cracks in the electrode and substrate due to mechanical impact during bonding disappeared.
（３）通常のウエノ・プロセスにより形成された電極及
びパッシベーション膜等の形成を行った基板から成るチ
ップの多数を同一板上に形成したシリコンウェハ１１を
用意した。（第３図）
上記電極はスパッタリグ装置により形成された膜厚的１
μｍのＡｌ−２％Ｓ ｉ−２％Ｃｕからなシ、またパッ
シベーション膜としては窒化シリコン膜が用いられてい
る。□そして、このシリコンウェハ・１１に形成された
各チップには８０μｍ口型の上記電極（コンタクトパッ
ド）がそれぞれ６４個形成されている。（なお、このシ
リコンウェハ１１についてはブレードダイシングを行な
っていない。）このように形成された多数のチップを有
するシリコンウェハ１１を
メタけい酸ナトリウム １２ ｙ ／ を三シん酸
ナトリウム １３９／を炭酸ナトリウム
６９／を界面活性剤 ２９／ｌ
より成る脱脂浴剤で脱脂した後水洗いをし、次にＰｄＣ
Ｌｘ−１１１ＳＨＣ１ｌ０ＣＣ，Ｈ２Ｏ９，５４ｔの浴
液に浸漬して上記各電極表面に約２ｏｏｏＡＯＰｄ層を
形成した。(3) A silicon wafer 11 was prepared in which a large number of chips were formed on the same board, each consisting of a substrate on which electrodes, passivation films, and the like were formed by the usual Ueno process. (Figure 3) The above electrode is a film with a thickness of 1
A silicon nitride film is used as the passivation film. □ Each chip formed on this silicon wafer 11 has 64 electrodes (contact pads) each having a diameter of 80 μm. (This silicon wafer 11 was not subjected to blade dicing.) The silicon wafer 11 having a large number of chips formed in this way was treated with sodium metasilicate, 12 y / of sodium trisinate, 139 / of sodium carbonate.
69/l to surfactant 29/l
After degreasing with a degreasing bath agent consisting of
About 2000 AOPd layer was formed on the surface of each electrode by immersing it in a bath solution of Lx-111SHC110CC, H2O9, 54t.
そして更にＰｄ層は電極を約４５０℃の温度に保持した
水素雰囲気中で約２０分間加熱し、表面に接着されてい
るＰｄと電極の主要材であるＡｌとを拡散せしめて約６
ｏｏｆの拡散活性化層を形成した。The Pd layer is then heated for about 20 minutes in a hydrogen atmosphere with the electrode maintained at a temperature of about 450°C to diffuse the Pd bonded to the surface and Al, which is the main material of the electrode.
oof diffusion activation layer was formed.
このシリコンウェハ１１の電極の拡散活性化層上に、第
３図に示すような超音波半田づけ装置を用いて半田バン
プを形成した。第２図において、半田槽２１内には半田
の還流路２２が形成され、溶融半田２３が収容されてい
る。どの溶融半田２３は図示しないモータにより回転さ
れる撹拌棒２４により還流路２２内を通って液面より上
に噴出して還流する。前記シリコンウェハ・１１は裏面
に高温用の接着テープを貼付し、更に図示しないガラス
板に接着した状態で縦にして、噴出している浴融半田２
３に浸漬（デイツプ）される。そして、シリコンウェハ
１１近傍の溶融半田２３中に超音波振動子２５を挿入し
て溶融半田２３に超音波を印加する。Solder bumps were formed on the diffusion activation layer of the electrode of this silicon wafer 11 using an ultrasonic soldering apparatus as shown in FIG. In FIG. 2, a solder reflux path 22 is formed in a solder tank 21, and molten solder 23 is accommodated therein. Any of the molten solder 23 is spouted out above the liquid level through the reflux path 22 by a stirring rod 24 rotated by a motor (not shown) and refluxed. The silicon wafer 11 has a high-temperature adhesive tape affixed to its back side, and is further adhered to a glass plate (not shown), held vertically, and bath melted solder 2 is spouted out.
It is immersed in 3. Then, an ultrasonic transducer 25 is inserted into the molten solder 23 near the silicon wafer 11 to apply ultrasonic waves to the molten solder 23.
なお、半田としては４ Ｑ Ｐ ｂ −Ｓ ｎ −５Ａ
ｇ （Ｄ半田を使用し、半田槽温度を３００℃に維持
した。In addition, as solder, 4 Q P b -S n -5A
g (D solder was used and the solder bath temperature was maintained at 300°C.
また、超音波振動子２５によシ溶融半田２３に周波数２
０ＫＨｚ、出力１５Ｗの超音波を印加し、シリコンウェ
ハ１１のデイツプ時間は１０秒間どした。この半田づけ
操作中、周囲に窒素ガスを１００ｔ／分の流量で流し、
電極の一部に形成されている拡散活性化層のｋｔ−Ｐｄ
と半田を構成するＳｎの酸化を防止した。Further, the ultrasonic vibrator 25 applies a frequency of 2 to the molten solder 23.
Ultrasonic waves with a frequency of 0 KHz and an output of 15 W were applied, and the dip time of the silicon wafer 11 was set to 10 seconds. During this soldering operation, nitrogen gas was passed around at a flow rate of 100 t/min.
kt-Pd in the diffusion activation layer formed on a part of the electrode
This prevented the oxidation of Sn constituting the solder.
このようにして電極の拡散活性層の上には約２５μｍの
均一なバンプ５を形成した。（第１図参照）なお上記で
は半田溶液中に超音波を印加してバンプ形成を行ったが
、上記Ｐｄ−Ａｌの拡散処理後直ちに継続して半田浴液
中に浸漬してバンプ形成を行えば上記シリコンウェー・
をわずかに振動させるのみで超音波のそれと同等の品質
でバンプ形成が可能となり、
次に上記で形成したバンプを有するチップをシリコンウ
ェハから夫々切断し、多数のバンプを有する基板素子（
チップ）を形成した。In this way, uniform bumps 5 of about 25 μm were formed on the diffusion active layer of the electrode. (See Figure 1) In the above, bumps were formed by applying ultrasonic waves into the solder solution, but after the above Pd-Al diffusion treatment, bumps were formed by continuing to immerse in the solder bath solution. For example, the above silicon wafer
It is possible to form bumps with a quality equivalent to that of ultrasonic waves by only slightly vibrating the silicon wafer.Next, the chips with the bumps formed above are individually cut from the silicon wafer, and the substrate elements (
chips) were formed.
これを確認するだめに、上記６４個のバンプに同数の端
子を有するリードフレームを用意し、この端子と上記バ
ンプとの位置合せを行った後に、約１７０℃温度で加熱
浴着（ボンデング）を行ったところ良結果が得られた。To confirm this, we prepared a lead frame having the same number of terminals as the 64 bumps mentioned above, and after aligning the terminals with the bumps mentioned above, heated bath bonding was performed at a temperature of about 170°C. I went there and got good results.
上記した様に本発明バンプを有する基板素子はバンプと
電極との浴着を極めて容易にし、バンプの形状、高さ等
の規制が極めて良く所定形状のバンプを形成出来ると共
に電極の微細化にも有利となった。また、ワイヤレスボ
ンデングに対シてもその特徴が十分に発輝することが可
能であり、浴着の信頼性が向上できる。As described above, the substrate element having the bumps of the present invention makes it extremely easy to attach the bumps to the electrodes, and the shape, height, etc. of the bumps can be extremely well regulated, making it possible to form bumps with a predetermined shape, and also to miniaturize the electrodes. It was advantageous. In addition, its characteristics can be fully demonstrated in wireless bonding, and the reliability of bathwear can be improved.
バンプは電極に直接接着出来るのでその製造が容易とな
り、総合的に安価になるという利点がある。Since the bump can be directly bonded to the electrode, it has the advantage of being easy to manufacture and being inexpensive overall.
よって量産に好適で産業上の実用的効果が犬である。Therefore, dogs are suitable for mass production and have practical industrial effects.
は本発明バンプを有する基板素子の製造方法の一部（バ
ンプを形成する際）を説明するだめの説明図である。
４・・・・・・・・・電極 ６・・・・・・・・拡散
活性化層代理人弁理士 則 近 憲 佑
同 松山光之FIG. 2 is an explanatory diagram for explaining a part of the method for manufacturing a substrate element having bumps according to the present invention (when forming bumps). 4... Electrode 6... Patent attorney representing the diffusion activation layer Noriyuki Noriyuki Yudo Mitsuyuki Matsuyama
Claims (3)
するためのパッシベーション膜と、 上記電極に接続されたバンプを具備した基板素子におい
て、上記電極の一部であって上記バンプとの接続面は拡
散活性化層が形成されていることを特徴とするバンプを
有する基板素子。(1) In a substrate element comprising an electrode formed on a part of the substrate, a passivation film for separating the electrode, and a bump connected to the electrode, the bump is a part of the electrode and is connected to the bump. A substrate element having a bump, characterized in that a diffusion activation layer is formed on a connection surface of the substrate element.
求の範囲第１項記載のバンプを有する基板素子。(2) A substrate element having bumps according to claim 1, wherein the diffusion active layer is formed of Al-Pd.
を被着し、上記電極上に活性金属を付着せしめた後に加
熱して電極金属と活性金属とを拡散せしめ、この部分に
拡散活性化層を形成することを特徴とするバンプを有す
る基板素子の製造方法。(3) After forming an electrode on a part of the substrate, depositing a passivation film, and adhering an active metal onto the electrode, heating is performed to diffuse the electrode metal and the active metal to activate diffusion in this part. A method for manufacturing a substrate element having bumps, the method comprising forming a layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62317568A JP2695804B2 (en) | 1987-12-17 | 1987-12-17 | Method for manufacturing substrate element having bump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62317568A JP2695804B2 (en) | 1987-12-17 | 1987-12-17 | Method for manufacturing substrate element having bump |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01160040A true JPH01160040A (en) | 1989-06-22 |
| JP2695804B2 JP2695804B2 (en) | 1998-01-14 |
Family
ID=18089702
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62317568A Expired - Fee Related JP2695804B2 (en) | 1987-12-17 | 1987-12-17 | Method for manufacturing substrate element having bump |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2695804B2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4844595A (en) * | 1971-10-13 | 1973-06-26 | ||
| JPS5768052A (en) * | 1980-10-15 | 1982-04-26 | Hitachi Ltd | Semiconductor device |
| JPS5790963A (en) * | 1980-11-27 | 1982-06-05 | Seiko Epson Corp | Manufacture of semiconductor device |
-
1987
- 1987-12-17 JP JP62317568A patent/JP2695804B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4844595A (en) * | 1971-10-13 | 1973-06-26 | ||
| JPS5768052A (en) * | 1980-10-15 | 1982-04-26 | Hitachi Ltd | Semiconductor device |
| JPS5790963A (en) * | 1980-11-27 | 1982-06-05 | Seiko Epson Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2695804B2 (en) | 1998-01-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5906312A (en) | Solder bump for flip chip assembly and method of its fabrication | |
| US4763829A (en) | Soldering of electronic components | |
| JPH02246335A (en) | Bump structure for reflow bonding of ic device | |
| WO1997018584A1 (en) | Method for forming bump of semiconductor device | |
| US7045389B1 (en) | Method for fabricating a semiconductor devices provided with low melting point metal bumps | |
| JPS59155950A (en) | Low melting-point glass seal type ceramic package for semiconductor device | |
| JPH10163213A (en) | Manufacture of semiconductor device and mounting method of semiconductor device | |
| JP2002507838A (en) | Cleaning-free flux for flip chip assembly | |
| JPH0266953A (en) | Mounting structure of semiconductor element and manufacture thereof | |
| JPH05315731A (en) | Manufacture of connection pad of wiring board | |
| JPH01160040A (en) | Substrate element with bump and manufacture thereof | |
| JP2000012605A (en) | Method for producing electrode part of semiconductor chip | |
| JPH0350736A (en) | Manufacture of bump of semiconductor chip | |
| JPS63289947A (en) | Substrate with solder bump and manufacture thereof | |
| JPS62204547A (en) | Solder bump forming method | |
| JPS63221634A (en) | Fixing method for semiconductor pellet | |
| JPH0282624A (en) | Semiconductor element with solder bump and manufacture thereof | |
| JPS63147348A (en) | Formation of solder bump | |
| JPH0745664A (en) | Mounting method for semiconductor device | |
| JPS62104143A (en) | Formation of solder bump | |
| JPH01184851A (en) | Substrate element having bump | |
| JPH10289973A (en) | Surface treatment method of lead frame | |
| JPS589328A (en) | Manufacture of semiconductor device | |
| JPH01205551A (en) | Formation of solder bump electrode | |
| JPH0469427B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |