JPH01143524A - Phase locked loop oscillation circuit - Google Patents
Phase locked loop oscillation circuitInfo
- Publication number
- JPH01143524A JPH01143524A JP62301885A JP30188587A JPH01143524A JP H01143524 A JPH01143524 A JP H01143524A JP 62301885 A JP62301885 A JP 62301885A JP 30188587 A JP30188587 A JP 30188587A JP H01143524 A JPH01143524 A JP H01143524A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- frequency
- phase
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 title claims abstract description 46
- 230000000737 periodic effect Effects 0.000 claims description 3
- 230000035945 sensitivity Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は通信装置等の同期回路に使用される位相同期回
路に関するものであり、特に出力周波数が数百ＭＨ２帯
で同期はずれ時にも高安定な周波数を出力する位相同期
発振回路に関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a phase synchronization circuit used in synchronization circuits of communication devices, etc., and in particular, the present invention relates to a phase synchronization circuit that is highly stable even when the output frequency is out of synchronization in the hundreds of MH2 band. This invention relates to a phase-locked oscillator circuit that outputs a frequency.
［従来の技術］
従来、高周波高安定の位相同期発振回路は、第２図に示
すような回路構成を有していた。[Prior Art] Conventionally, a high-frequency, highly stable phase-locked oscillation circuit has had a circuit configuration as shown in FIG.
同図において、第２の位相比較回路６ａは第２のルー／
フィルター７ａに接続され、ループフィルター７ａの出
力は低周波側高安定の電圧制御圧電発振回路９ａに入力
される。第１の位相比較回路２ａは、第１の分周回路５
ａの出力と、上記電圧制御圧電発振回路９ａの出力とを
入力し、その出力は第１のループフィルター３ａへ入力
され、第１のループフィルター３ａの出力は電圧制御圧
電発振回路（高周波側）４ａへ入力される。In the figure, the second phase comparison circuit 6a is connected to the second loop/
It is connected to a filter 7a, and the output of the loop filter 7a is input to a voltage controlled piezoelectric oscillation circuit 9a which is highly stable on the low frequency side. The first phase comparator circuit 2a is connected to the first frequency divider circuit 5.
a and the output of the voltage controlled piezoelectric oscillation circuit 9a, the output is input to the first loop filter 3a, and the output of the first loop filter 3a is input to the voltage controlled piezoelectric oscillation circuit (high frequency side). 4a.
又、電圧制御圧電発振回路４ａの出力は第１の分周回路
５ａと第２の分周回路８ａへ入力される。Further, the output of the voltage controlled piezoelectric oscillator circuit 4a is input to the first frequency dividing circuit 5a and the second frequency dividing circuit 8a.
このように、第２の位相比較回路６ａの出力を第１の電
圧制御圧電発振回路９ａの制御入力に接続する第２の位
相同期ループを構成し、第２の電圧制御圧電発振回路４
ａの出力から出力周波数を得る構成となっていた。In this way, a second phase-locked loop is configured that connects the output of the second phase comparison circuit 6a to the control input of the first voltage-controlled piezoelectric oscillation circuit 9a, and the second voltage-controlled piezoelectric oscillation circuit 4
The configuration was such that the output frequency was obtained from the output of a.
［発明が解決しようとする問題点］
しかしながら、上述した従来の位相同期発振回路の周波
数応答速度は、低周波側の圧電発振回路の周波数により
第１の位相比較周波数が制約をうける等のため、あまり
速くすることができなかった。[Problems to be Solved by the Invention] However, the frequency response speed of the conventional phase-locked oscillation circuit described above is limited by the frequency of the piezoelectric oscillation circuit on the low frequency side, and so on. I couldn't do it very fast.
従って、全体の位相比較ループの設計上大きな制約をう
け、自由度がないという欠点を有していた。Therefore, the design of the entire phase comparison loop is severely restricted and has the drawback of having no degree of freedom.
［問題点を解決するための手段］
本発明は上記問題点を解決し、周波数応答速度の速い、
かつ安定した出力周波数を供給することができる位相同
期発振回路を提供することを目的とする。[Means for Solving the Problems] The present invention solves the above problems and provides fast frequency response speed.
It is an object of the present invention to provide a phase-locked oscillation circuit that can supply a stable output frequency.
上記目的を達成するため本発明に係る位相同期発振回路
は、圧電共振子を含む圧電発振回路と、制御入力端子に
印加する電圧値により静電容量が変化する可変容量素子
と圧電共振子を含み、前記圧電発振回路の整数倍の周波
数で発振する電圧制御圧電発振回路と、第１、第２の分
周回路と、第１、第２の位相比較回路と、第１、第２の
ループフィルターとを有し、電圧制御圧電発振回路の出
力を第１、第２の分周回路に入力し、圧電発振回路の出
力と第１の分周回路の出力を第１の位相比較回路に入力
し、第１の位相比較回路の出力を第１のループフィルタ
ーに入力し、第１のループフィルターの出力を電圧制御
圧電発振回路の制御入力の一端に接続することにより第
１の位相同期ループを構成し、第２の分周回路の出力と
第２の分周回路の出力と同じ周波数を第２の位相比較回
路に入力し、第２の位相比較回路の出力を第２のループ
フィルターに入力し、第２のループフィルターの出力を
電圧制御圧電発振回路の制御入力の他端に接続すること
により第２の位相周期ループを構成し、電圧制御圧電発
振回路の出力から出力周波数を得るものである。In order to achieve the above object, a phase-locked oscillation circuit according to the present invention includes a piezoelectric oscillation circuit including a piezoelectric resonator, a variable capacitance element whose capacitance changes depending on a voltage value applied to a control input terminal, and a piezoelectric resonator. , a voltage-controlled piezoelectric oscillation circuit that oscillates at a frequency that is an integral multiple of the piezoelectric oscillation circuit, first and second frequency dividing circuits, first and second phase comparison circuits, and first and second loop filters. The output of the voltage controlled piezoelectric oscillation circuit is input to the first and second frequency dividing circuits, and the output of the piezoelectric oscillation circuit and the output of the first frequency dividing circuit are input to the first phase comparison circuit. , a first phase-locked loop is configured by inputting the output of the first phase comparator circuit to a first loop filter, and connecting the output of the first loop filter to one end of the control input of the voltage-controlled piezoelectric oscillator circuit. Then, the output of the second frequency dividing circuit and the same frequency as the output of the second frequency dividing circuit are inputted to the second phase comparison circuit, and the output of the second phase comparison circuit is inputted to the second loop filter. , a second phase periodic loop is constructed by connecting the output of the second loop filter to the other end of the control input of the voltage-controlled piezoelectric oscillation circuit, and the output frequency is obtained from the output of the voltage-controlled piezoelectric oscillation circuit. .
［実施例］
以下、本発明の一実施例について図面を参照して詳細に
説明する。[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明の一実施例による位相同期発振回路の構
成を示すブロック図である。FIG. 1 is a block diagram showing the configuration of a phase-locked oscillation circuit according to an embodiment of the present invention.
同図において、本実施例による位相同期発振回路は、圧
電共振子を含む高安定な圧電発揚回路１と、第１の分周
回路５と圧電発振回路１どの位相差を比較する第１の位
相比較回路２と、第１の位相比較回路２の出力を平滑化
し位相差に比例した電圧を出力する第１のループフィル
ター３と、第１のループフィルター３から制御入力の一
端に入力される電圧値により静電容量が変化する可変容
量子と圧電共振子を含み圧電発振回路１の出力周波数の
整数倍の周波数を出力する電圧制御圧電発振回路４と、
電圧制御圧電発振回路４の出力を分周する第１の分周回
路５及び第２の分周回路８と、第２の分周回路８の出力
及びこれと同じ周波数を入力する第２の位相比較回路６
と、第２の位相比較回路６の出力を平滑化し位相差に比
例した電圧を電圧制御圧電発振回路４の他方の制御入力
へ出力する第２のループフィルター７とから構成される
。In the figure, the phase-locked oscillation circuit according to the present embodiment includes a highly stable piezoelectric oscillation circuit 1 including a piezoelectric resonator, a first frequency dividing circuit 5, and a first phase-locked oscillation circuit 1 for comparing the phase difference between the first frequency dividing circuit 5 and the piezoelectric oscillation circuit 1. A comparison circuit 2, a first loop filter 3 that smoothes the output of the first phase comparison circuit 2 and outputs a voltage proportional to the phase difference, and a voltage input from the first loop filter 3 to one end of the control input. a voltage-controlled piezoelectric oscillation circuit 4 that includes a variable capacitor whose capacitance changes depending on the value and a piezoelectric resonator and outputs a frequency that is an integral multiple of the output frequency of the piezoelectric oscillation circuit 1;
A first frequency divider circuit 5 and a second frequency divider circuit 8 that frequency divide the output of the voltage controlled piezoelectric oscillator circuit 4, and a second phase that inputs the output of the second frequency divider circuit 8 and the same frequency. Comparison circuit 6
and a second loop filter 7 that smoothes the output of the second phase comparison circuit 6 and outputs a voltage proportional to the phase difference to the other control input of the voltage controlled piezoelectric oscillation circuit 4.
また、圧電発振回路１の出力周波数の整数倍の周波数を
出力する電圧制御圧電発振回路４において、その周波数
可変範囲を、前記圧電発振回路１の周波数安定度と電圧
制御圧電発振回路４自身の周波数安定度との和以上の周
波数可変範囲を有する構成とする。In addition, in the voltage controlled piezoelectric oscillation circuit 4 that outputs a frequency that is an integral multiple of the output frequency of the piezoelectric oscillation circuit 1, the frequency variable range is determined based on the frequency stability of the piezoelectric oscillation circuit 1 and the frequency of the voltage controlled piezoelectric oscillation circuit 4 itself. The configuration has a frequency variable range that is greater than the sum of the stability and stability.
次に、本実施例の動作について説明する。Next, the operation of this embodiment will be explained.
電圧制御圧電発振回路４の出力を第１の分周回路５に入
力し、ここで前記圧電発振回路１と同じ周波数まで分周
して出力し、第１の位相比較回路２に入力する。第１の
位相比較回路２の出力をループフィルター３に入力する
。第１のループフィルター３の出力は位相比較回路２の
出力を平滑化し、圧電発振回路１と電圧制御圧電発振回
路４の位相差に比例した電圧を出力し、これを電圧制御
圧電発振回路４の制御入力の一端に接続し第１の位相周
期ループが構成される。The output of the voltage-controlled piezoelectric oscillation circuit 4 is input to a first frequency dividing circuit 5, where the frequency is divided to the same frequency as the piezoelectric oscillation circuit 1, outputted, and inputted to the first phase comparison circuit 2. The output of the first phase comparator circuit 2 is input to a loop filter 3. The output of the first loop filter 3 smoothes the output of the phase comparison circuit 2 and outputs a voltage proportional to the phase difference between the piezoelectric oscillation circuit 1 and the voltage-controlled piezoelectric oscillation circuit 4. Connected to one end of the control input, a first phase periodic loop is configured.
さらに、電圧制御圧電発振回路４の出力を第２の分周回
路８にも入力し、分周回路８の出力を第２の位相比較回
路６に入力する。また第２の位相比較回路６の他方の入
力端には分周回路８の出力を同じ周波数が入力されてい
る。第２の位相比較回路６の出力を第２のループフィル
ター７に人、力する。この第２のループフィルター７の
出力は第２の位相比較回路６の出力を平滑化し、電圧制
御圧電発振回路４の制御入力の他方の一端に接続し、第
２の位相同期ループが構成されるものである。Further, the output of the voltage controlled piezoelectric oscillator circuit 4 is also input to the second frequency divider circuit 8, and the output of the frequency divider circuit 8 is input to the second phase comparator circuit 6. Further, the same frequency as the output of the frequency dividing circuit 8 is input to the other input terminal of the second phase comparator circuit 6. The output of the second phase comparison circuit 6 is applied to the second loop filter 7. The output of this second loop filter 7 smoothes the output of the second phase comparison circuit 6 and is connected to the other end of the control input of the voltage-controlled piezoelectric oscillation circuit 4, thereby forming a second phase-locked loop. It is something.
［発明の効果］
以上説明したように本発明は、第２の分周回路と第２の
位相比較回路と第２のループフィルターとで構成される
第２の位相同期ループを電圧制御圧電発振回路に直接接
続することにより・電圧制御圧電発振回路の感度のみが
周波数応答速度に関与する為、従来の回路構成より速い
周波数応答速度を得ることができる効果がある。[Effects of the Invention] As explained above, the present invention provides a voltage-controlled piezoelectric oscillation circuit that connects a second phase-locked loop composed of a second frequency divider circuit, a second phase comparator circuit, and a second loop filter. Since only the sensitivity of the voltage-controlled piezoelectric oscillator circuit is involved in the frequency response speed, it is possible to obtain a faster frequency response speed than the conventional circuit configuration.
また、第２の位相同期ループにて同期がはずれた場合に
おいても、第１の位相同期ループにより安定な出力周波
数を供給することができる。Furthermore, even if the second phase-locked loop loses synchronization, the first phase-locked loop can supply a stable output frequency.
第１図は本発明の一実施例による位相同期発振回路の構
成を示す図、第２図は従来の位相同期発振回路の一構成
例図である。
１：圧電発振回路
２．２ａ：第１の位相比較回路
３．３ａ：第１のループフィルター
４．４ａ：電圧制御圧電発振回路
５．５ａ：第１の分周回路
６．６ａ：第２の位相比較回路
７．７ａ：第２のループフィルター
８．８ａ：第２の分周回路
９ａ：電圧制御圧電発振回路FIG. 1 is a diagram showing the configuration of a phase-locked oscillation circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of the configuration of a conventional phase-locked oscillation circuit. 1: Piezoelectric oscillation circuit 2.2a: First phase comparison circuit 3.3a: First loop filter 4.4a: Voltage controlled piezoelectric oscillation circuit 5.5a: First frequency dividing circuit 6.6a: Second Phase comparison circuit 7.7a: Second loop filter 8.8a: Second frequency dividing circuit 9a: Voltage controlled piezoelectric oscillator circuit
Claims (1)
する電圧値により静電容量が変化する可変容量素子と圧
電共振子を含み、前記圧電発振回路の整数倍の周波数で
発振する電圧制御圧電発振回路と、第１、第２の分周回
路と、第１、第２の位相比較回路と、第１、第２のルー
プフィルターとを有し、電圧制御圧電発振回路の出力を
第１、第２の分周回路に入力し、圧電発振回路の出力と
第１の分周回路の出力を第１の位相比較回路に入力し、
第１の位相比較回路の出力を第１のループフィルターに
入力し、第１のループフィルターの出力を電圧制御圧電
発振回路の制御入力の一端に接続することにより第１の
位相同期ループを構成し、 第２の分周回路の出力と第２の分周回路の出力と同じ周
波数を第２の位相比較回路に入力し、第２の位相比較回
路の出力を第２のループフィルターに入力し、第２のル
ープフィルターの出力を電圧制御圧電発振回路の制御入
力の他端に接続することにより第２の位相周期ループを
構成し、電圧制御圧電発振回路の出力から出力周波数を
得る事を特徴とする位相同期発振回路。[Claims] A piezoelectric oscillation circuit including a piezoelectric resonator, a variable capacitance element whose capacitance changes depending on a voltage value applied to a control input terminal, and a piezoelectric resonator, the frequency being an integral multiple of the piezoelectric oscillation circuit. A voltage-controlled piezoelectric oscillator circuit, comprising: a voltage-controlled piezoelectric oscillator circuit that oscillates with a voltage-controlled piezoelectric oscillator circuit; inputting the output of the piezoelectric oscillator circuit and the output of the first frequency dividing circuit to a first phase comparison circuit;
A first phase-locked loop is configured by inputting the output of the first phase comparison circuit to a first loop filter, and connecting the output of the first loop filter to one end of the control input of the voltage-controlled piezoelectric oscillator circuit. , inputting the output of the second frequency dividing circuit and the same frequency as the output of the second frequency dividing circuit to the second phase comparison circuit, inputting the output of the second phase comparison circuit to the second loop filter, The second phase periodic loop is configured by connecting the output of the second loop filter to the other end of the control input of the voltage-controlled piezoelectric oscillator circuit, and the output frequency is obtained from the output of the voltage-controlled piezoelectric oscillator circuit. phase-locked oscillation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62301885A JPH01143524A (en) | 1987-11-30 | 1987-11-30 | Phase locked loop oscillation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62301885A JPH01143524A (en) | 1987-11-30 | 1987-11-30 | Phase locked loop oscillation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01143524A true JPH01143524A (en) | 1989-06-06 |
Family
ID=17902310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62301885A Pending JPH01143524A (en) | 1987-11-30 | 1987-11-30 | Phase locked loop oscillation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01143524A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0846511A (en) * | 1994-05-24 | 1996-02-16 | Matsushita Electric Ind Co Ltd | Clock generator and clock generating method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5989037A (en) * | 1982-11-12 | 1984-05-23 | Victor Co Of Japan Ltd | Phase locked loop circuit |
-
1987
- 1987-11-30 JP JP62301885A patent/JPH01143524A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5989037A (en) * | 1982-11-12 | 1984-05-23 | Victor Co Of Japan Ltd | Phase locked loop circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0846511A (en) * | 1994-05-24 | 1996-02-16 | Matsushita Electric Ind Co Ltd | Clock generator and clock generating method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS61258529A (en) | Frequency synthesizer | |
| JPS5825724A (en) | Wide band frequency synthesizer | |
| JPH01143524A (en) | Phase locked loop oscillation circuit | |
| JPH0224416B2 (en) | ||
| US4914406A (en) | Voltage controlled oscillator free from free-run oscillating frequency adjustment | |
| JPS63258116A (en) | Phase locked loop circuit | |
| JP2589531B2 (en) | Voltage controlled oscillator | |
| JPS63128816A (en) | Pll circuit | |
| JP2924296B2 (en) | Internal clock generation circuit | |
| JPH10285027A (en) | Pll oscillation circuit | |
| JPS5846586Y2 (en) | Circuit with phase locked loop | |
| JPH08154029A (en) | Resonance circuit | |
| JP2536018B2 (en) | Frequency synthesizer circuit | |
| JPS63146616A (en) | Pll frequency synthesizer circuit | |
| JPH09200046A (en) | Phase difference control pll circuit | |
| JP2004096470A (en) | Phase-locked loop circuit | |
| JPH056363B2 (en) | ||
| JPH03242017A (en) | High speed stabilized voltage controlled oscillation circuit | |
| JPH0637631A (en) | Pll oscillator | |
| JPH01144820A (en) | Oscillating circuit | |
| JPH06303032A (en) | Oscillation circuit and phase locked loop circuit | |
| JP2003110359A (en) | Voltage-controlled oscillation circuit, and receiver using the same circuit | |
| JPH07273647A (en) | Pll circuit | |
| JPH027719A (en) | Frequency synthesizer | |
| JPS61253904A (en) | Oscillation circuit |