JPH01136371A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01136371A JPH01136371A JP62295671A JP29567187A JPH01136371A JP H01136371 A JPH01136371 A JP H01136371A JP 62295671 A JP62295671 A JP 62295671A JP 29567187 A JP29567187 A JP 29567187A JP H01136371 A JPH01136371 A JP H01136371A
- Authority
- JP
- Japan
- Prior art keywords
- region
- silicon
- semiconductor device
- layer
- diffusion layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims description 34
- 238000009792 diffusion process Methods 0.000 claims abstract description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 44
- 239000010703 silicon Substances 0.000 claims abstract description 44
- 238000002955 isolation Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 5
- 239000010937 tungsten Substances 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims description 29
- 239000002184 metal Substances 0.000 claims description 29
- 238000002844 melting Methods 0.000 claims description 28
- 230000008018 melting Effects 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 239000012495 reaction gas Substances 0.000 claims description 2
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims 1
- 229910052720 vanadium Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 70
- 239000007789 gas Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
この発明は、例えばＭＯＳ ＦＥＴ等の半導体装置の
製造方法に関するもので、特に拡散層上に高融点金属層
を選択成長させて形成し、浅く且つシート抵抗の低い拡
散層を形成するための半導体装置の製造方法に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device such as a MOS FET, and particularly relates to a method of manufacturing a semiconductor device such as a MOS FET, and in particular, a method for selectively growing a high melting point metal layer on a diffusion layer. The present invention relates to a method of manufacturing a semiconductor device for forming a shallow diffusion layer with low sheet resistance.
（従来の技術）
近年、半導体素子の微細化によるＬＳＩの高集積化およ
び高性能化を図るために、浅く且つシート抵抗の低い拡
散層の形成が要求されている。(Prior Art) In recent years, in order to achieve higher integration and higher performance of LSIs due to miniaturization of semiconductor devices, it has been required to form a shallow diffusion layer with low sheet resistance.
従来、このような要求を満たせる半導体装置の製造方法
としては、拡散層上に高融点金属層を選択成長させる方
法が用いられている。すなわち、拡散層を浅く形成して
も上記高融点金属層により拡散層のシート抵抗の低減を
図れるようにしたもので、このような半導体装置は例え
ば第２図（ａ）〜（ｆ）に示すような工程で形成される
。第２図（ａ）〜（ｆ）は、この種の半導体装置として
、ＬＤＤ構３ｆｔｆ有する０ＭＯ８型＋７）ＭＯＳ
ＦＥＴを例に取って、その製造工程を順次水している。Conventionally, as a method for manufacturing a semiconductor device that can satisfy such requirements, a method has been used in which a high melting point metal layer is selectively grown on a diffusion layer. That is, even if the diffusion layer is formed shallowly, the sheet resistance of the diffusion layer can be reduced by the high melting point metal layer.Such a semiconductor device is shown in FIGS. 2(a) to 2(f), for example. It is formed through the following process. Figures 2(a) to (f) show a 0MO8 type +7) MOS having an LDD structure of 3 ftf as this type of semiconductor device.
Taking FET as an example, we will explain its manufacturing process sequentially.
まず、（ａ）図に示すように、ｎ型シリコン基板１の表
面領域中にｐ型のウェル領域２を形成した後、ＬＯＣＯ
８法により素子分離領域３を形成する。続いて、ＨＣｊ
２あるいはＡｒを用いて希釈酸化を行ない、シリコン基
板１上およびウェル領域２上にゲート絶縁膜となる薄い
酸化膜４を形成する。次に、（ｂ）図に示すように、Ｌ
ＰＣＶＤ法により多結晶シリコン層５を４０００人程度
堆積形成する。次に、上記多結晶シリコン層５をパター
ニングしてゲート電極５ａ、 ５ｂを形成し、これらの
ゲート電極５ａ、 ５ｂをそれぞれマスクとしてｎチャ
ネル型ＭＯ８ＦＥＴの形成予定領域（ｎチャネル領域）
Ｑｎに例えばリンを、ｐチャネル型ＭＯ３ＦＥＴの形成
予定領域（ｎチャネル領域）Ｑｐに例えばボロンをそれ
ぞれイオン注入・する。First, as shown in figure (a), after forming a p-type well region 2 in the surface region of an n-type silicon substrate 1, LOCO
The element isolation region 3 is formed by the 8 method. Next, HCj
A thin oxide film 4, which will become a gate insulating film, is formed on the silicon substrate 1 and the well region 2 by diluted oxidation using 2 or Ar. Next, as shown in figure (b), L
A polycrystalline silicon layer 5 is deposited by about 4,000 layers using the PCVD method. Next, the polycrystalline silicon layer 5 is patterned to form gate electrodes 5a and 5b, and using these gate electrodes 5a and 5b as masks, a region where an n-channel MO8FET is to be formed (n-channel region) is formed.
For example, phosphorus is ion-implanted into Qn, and boron, for example, is ion-implanted into the region Qp where the p-channel type MO3FET is to be formed (n-channel region).
これによって、ドレイン領域近傍における電界集中緩和
用の低濃度の拡散層６，６および１，７が形成され（Ｃ
）図に示すようになる。次に、（ｄ）図に示すように、
全面にＣＶＤ法を用いて例えば厚さ１５００人のシリコ
ン酸化１１８を堆積形成する。引続き、異方性エツチン
グを行なって上記シリコン酸化ＷＡ８を除去し、ゲート
電極５ａ、 ５ｂの側壁部のみに上記シリコン酸化膜８
ａ、 ８ａ、 ８ｂ、 ８ｂを残存させる。そして、上
記ゲート電極５ａ、シリコン酸化膜８ａ、 ８ａ、およ
び上記ゲート電極５ｂ、シリコン酸化膜８ｂ、 ８ｂを
マスクとして、ｎチャネル領域Ｑｎにはリン（Ｐ）また
はヒ素（Ａｓ）をイオン注入し、ｐチャネル領域Ｑｌ）
にはボロン（Ｂ）またはフッ化ホウ素（ＢＦ２）をそれ
ぞれイオン注入た後、熱処理を行なってソース、ドレイ
ン領域としての拡散層９ 、９．１０．１０を形成する
（（ｅ）図）。その後、希フッ化水素（希ＨＦ）処理を
施して上記多結晶シリコンから成るゲート電極５ａ、
Ｓｂ上およびソース、ドレイン領域９．９．１０、１０
上に残存されている酸化膜を除去する。そして、５５０
℃のアルゴン（Ａｒ）雰囲気中で、六フッ化タングステ
ン（ＷＦｓ ）とシリコンとを反応させることにより、
ソース、ドレイン領域９゜９ 、１０．１０上およびゲ
ート電極５ａ、 Ｓｂ上にタングステンを選択成長させ
てそれぞれタングステン層１１、１１．・・・を形成す
る。その後、図示しないが、全面に層間絶縁膜を形成し
、各ＭＯ３ＦＥＴのソース、ドレイン領域およびゲート
電極上にコンタクトホールを開孔した後、例えばアルミ
配線を行なってソース、ドレイン電極およびゲート電極
を導出し、バッジベージジン膜を形成して０ＭＯ８型の
ＭＯＳ ＦＥＴを有する半導体装置を完成する。As a result, low concentration diffusion layers 6, 6 and 1, 7 for alleviating electric field concentration near the drain region are formed (C
) as shown in the figure. Next, as shown in figure (d),
Silicon oxide 118 is deposited to a thickness of, for example, 1500 nm over the entire surface using the CVD method. Subsequently, anisotropic etching is performed to remove the silicon oxide WA8, and the silicon oxide film 8 is formed only on the side walls of the gate electrodes 5a and 5b.
Leave a, 8a, 8b, and 8b remaining. Then, using the gate electrode 5a, silicon oxide films 8a, 8a, and gate electrode 5b, silicon oxide films 8b, 8b as masks, phosphorus (P) or arsenic (As) is ion-implanted into the n-channel region Qn. p channel region Ql)
After ion implantation of boron (B) or boron fluoride (BF2), respectively, a heat treatment is performed to form diffusion layers 9, 9, 10, and 10 as source and drain regions (FIG. 3(e)). Thereafter, a gate electrode 5a made of the polycrystalline silicon is subjected to dilute hydrogen fluoride (dilute HF) treatment,
On Sb and source and drain regions 9.9.10, 10
Remove the oxide film remaining on top. And 550
By reacting tungsten hexafluoride (WFs) and silicon in an argon (Ar) atmosphere at ℃,
Tungsten is selectively grown on the source and drain regions 9.9 and 10.10 and on the gate electrodes 5a and Sb to form tungsten layers 11, 11.10, respectively. ... to form. After that, although not shown, an interlayer insulating film is formed on the entire surface, and contact holes are formed on the source, drain regions, and gate electrodes of each MO3FET, and then, for example, aluminum wiring is formed to lead out the source, drain, and gate electrodes. Then, a badge-base film is formed to complete a semiconductor device having an 0MO8 type MOS FET.
しかし、上述したような製造方法では、ソース。However, in the manufacturing method described above, the source.
ドレイン領域としての拡散層９ 、９ 、１０．１０の
シート抵抗の低減のために使用した高融点金属層１１が
製造工程（選択成長時の製造条件）のゆらぎ等により素
子分離領域３とシリコン基板１との界面に沿って成長し
、この高融点金属層１１とシリコン基板１あるいはｐウ
ェル領域２とが短絡し、製造歩留りが低下する欠点があ
る。この現象は上述した０ＭＯ８型のＭＯＳ ＦＥＴ
の製造工程に限らず、素子分離領域を有し、拡散層上に
選択成長によって高融点金属層を形成する全ての半導体
装置において問題となっており、その対策が望まれてい
る。Due to fluctuations in the manufacturing process (manufacturing conditions during selective growth), the high melting point metal layer 11 used to reduce the sheet resistance of the diffusion layers 9, 9, and 10. 1, this high melting point metal layer 11 and silicon substrate 1 or p-well region 2 are short-circuited, resulting in a reduction in manufacturing yield. This phenomenon occurs in the 0MO8 type MOS FET mentioned above.
This is a problem not only in the manufacturing process but also in all semiconductor devices that have an element isolation region and in which a high melting point metal layer is formed by selective growth on a diffusion layer, and a countermeasure is desired.
（発明が解決しようとする問題点）
上述したように、従来の半導体装置の製造方法では、高
融点金属層が素子分離領域とシリコン基板あるいはウェ
ル領域との界面に沿って成長し、この高融点金属層とシ
リコン基板あるいはウェル領域とが短絡して製造歩留り
が低下する欠点がある。(Problems to be Solved by the Invention) As described above, in the conventional semiconductor device manufacturing method, a high melting point metal layer grows along the interface between the element isolation region and the silicon substrate or well region. There is a drawback that the metal layer and the silicon substrate or well region are short-circuited, resulting in a decrease in manufacturing yield.
従って、この発明の目的は、拡散層上に高融点金属層を
選択成長させても、高融点金属層とシリコン基板あるい
はウェル領域とが短絡するのを防止でき、製造歩留りを
向上できる半導体装置の製造方法を提供することである
。Therefore, an object of the present invention is to provide a semiconductor device that can prevent short circuit between the high melting point metal layer and the silicon substrate or well region even if the high melting point metal layer is selectively grown on the diffusion layer, thereby improving the manufacturing yield. An object of the present invention is to provide a manufacturing method.
［発明の構成］
（問題点を解決するための手段と作用）すなわち、この
発明においては、上記の目的を達成するために、第１導
電型の半導体領域上に素子分離領域を形成し、この半導
体領域の表面領 域に前記素子分離領域に接した第２
導電型の拡散層を形成した後、前記素子分離領域と前記
拡散層との界面上をマスクして前記拡散層上に高融点金
属層を選択成長で形成し、前記素子分離領域と前記拡散
層との界面上におけるマスクした部分の前記拡散層上に
シリコンを選択成長させて第２導電型のシリコン層を形
成している。[Structure of the Invention] (Means and Effects for Solving the Problems) That is, in order to achieve the above object, in this invention, an element isolation region is formed on a semiconductor region of a first conductivity type; A second layer in contact with the element isolation region is provided in the surface region of the semiconductor region.
After forming a conductive type diffusion layer, a high melting point metal layer is selectively grown on the diffusion layer with a mask on the interface between the element isolation region and the diffusion layer, and the interface between the element isolation region and the diffusion layer is formed by selective growth. A second conductivity type silicon layer is formed by selectively growing silicon on the masked portion of the diffusion layer on the interface with the second conductivity type.
このような製造方法では、高融点金属が成長して問題と
なる素子分離領域と拡散層との界面上をマスクした状態
で高融点金属層を選択成長させ、その後このマスクをす
ることによって生じた高融点金属層のオフセット領域に
シリコンを選択成長させてシリコン層を形成しているの
で、素子分離領域と拡散層の界面に高融点金属層が成長
することがなく、高融点金属層とシリコン基板やウェル
領域とが短絡されるのを防止できる。In this manufacturing method, the high melting point metal layer is selectively grown while masking the interface between the device isolation region and the diffusion layer, which is a problem when the high melting point metal grows, and then this mask is applied. Since the silicon layer is formed by selectively growing silicon in the offset region of the high melting point metal layer, the high melting point metal layer does not grow at the interface between the element isolation region and the diffusion layer, and the high melting point metal layer and the silicon substrate This can prevent short-circuiting between the well region and the well region.
（実施例）
以下、この発明の一実施例について図面を参照して説明
する。第１図（ａ）、（ｂ）は、この発明の一実施例に
係わる半導体装置の製造方法について説明丈るための製
造工程の一部を示すもので、ＬＤＤ構造を有する０ＭＯ
８型のＭＯＳＦＥＴを例に取って示している。第１図（
ａ）に至るまでの工程は、前記第、２図（ａ）〜（ｅ）
における従来の製造工程と同様である。概略的に説明す
ると、ｎ型シリコン基板１に周知の方法によりｐ型のウ
ェル領域２およびＬＯＣＯ８法を用いて素子分離領域３
を形成した後、多結晶シリコンを用いたセルファライン
プロセスにより、シリコン基板１上にｐチャネル型ＭＯ
８ＦＥＴ、つエル領域２上にｎチャネル型ＭＯ８ＦＥＴ
をそれぞれ形成して第２図＜ｅ）に示したような構成を
得゛る。その後、第１図（ａ）に示すように、ソースあ
るいはドレイン領域としての拡散１ｉ９ 、９ 。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIGS. 1(a) and 1(b) show a part of the manufacturing process for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
An 8-type MOSFET is shown as an example. Figure 1 (
The steps up to step a) are shown in Figure 2 (a) to (e) above.
This is similar to the conventional manufacturing process in . Briefly, a p-type well region 2 is formed on an n-type silicon substrate 1 using a well-known method, and an element isolation region 3 is formed using a LOCO8 method.
After forming a p-channel MO on the silicon substrate 1, a self-line process using polycrystalline silicon is performed.
8FET, n-channel type MO8FET on the well region 2
are formed respectively to obtain the structure shown in FIG. 2<e). Thereafter, as shown in FIG. 1(a), diffusion 1i9,9 is formed as a source or drain region.
１０、１０上における素子分離領域３との界面上に、幅
１μｍ程度のマスク１２．１２を形成する。このマーク
材としては、例えばシリコン酸化膜を用いれシリコン（
Ｓ ｉ ）を反応させることにより、前記拡散層９ 、
９ 、１０．１０上およびゲート電極５ａ、 ５ｂ上に
タングステンｌ１１１．１１．・・・を２００人程程度
厚さに選択成長させる。その後、前記マスク１２゜１２
を除去し、素子分離領域３と高融点金属層１１との間に
オフセット領域を形成する。次に、第１図（ｂ）に示す
ように、例えば選択気相成長法を用いて、前記素子分離
領域３と高融点金属層１１とのオフセット領域にシリコ
ン層１３．１４を２００人程程度厚さに選択成長形成す
る。この際、前記各シリコン層１３．１４はそれぞれ、
その下の拡散層９゜反応ガスを圧力１００ｔｏｒｒ、温
度９００℃の条件で流し、ドーピングガスとしてｎチャ
ネル領域ＱｎにはＰＨ３ガスを、ｐチャネル領域Ｑｌ）
には８２ Ｈ６ガスをそれぞれ使用すればよい。これに
よって、ｎ型の拡散１ｉｌｅ上のシリコン層１３はｎ型
、ｐ型の拡散層９上のシリコン層１４はｐ型となる。Masks 12 and 12 having a width of about 1 μm are formed on the interface with the element isolation region 3 on the 10, 10. For example, a silicon oxide film may be used as the mark material.
By reacting S i ), the diffusion layer 9,
9, 10.10 and on the gate electrodes 5a, 5b. ... will be selectively grown to a thickness of about 200 people. After that, the mask 12°12
is removed to form an offset region between the element isolation region 3 and the high melting point metal layer 11. Next, as shown in FIG. 1(b), silicon layers 13 and 14 are deposited by about 200 layers in the offset region between the element isolation region 3 and the high melting point metal layer 11 using, for example, selective vapor deposition. Selective growth to form the thickness. At this time, each of the silicon layers 13 and 14 is
Under the diffusion layer 9°, a reaction gas is flowed under the conditions of a pressure of 100 torr and a temperature of 900°C, and PH3 gas is used as a doping gas in the n-channel region Qn, and the p-channel region Ql)
82 H6 gas may be used for each. As a result, the silicon layer 13 on the n-type diffusion layer 1ile becomes n-type, and the silicon layer 14 on the p-type diffusion layer 9 becomes p-type.
このような製造方法によれば、高融点金属層１１゜１１
・・・をソース、ドレイン領域９ 、９ 、１０．１０
上およびゲート電極５ａ、 Ｓｂ上に選択的に成長させ
て形成する際に、シリコン基板１あるいはウェル領域２
と素子分離領域３との界面上をマスクして行なうので、
製造工程に多少のゆらぎが生じても高融点金属が素子分
離領域３とシリコン基板１あるいはウェル領域２どの界
面に沿って成長することがない。従って、高融点金属層
１１．１１．・・・とシリコン基板１あるいはウェル領
域２とが短絡するという不良を防止でき、浅く且つシー
ト抵抗の低い拡散層９ 、９ 、１０．１０を形成でき
る。これによって、製造歩留りを向上できるとともに半
導体素子の微細化によるＬＳＩの高集積化および高性能
化が図れる。According to such a manufacturing method, the high melting point metal layer 11°11
... for source and drain regions 9, 9, 10.10
When selectively growing on the top and gate electrodes 5a and Sb, the silicon substrate 1 or the well region 2
This is done by masking the interface between and the element isolation region 3.
Even if some fluctuation occurs in the manufacturing process, the high melting point metal will not grow along any interface between the element isolation region 3 and the silicon substrate 1 or well region 2. Therefore, the high melting point metal layer 11.11. . . and the silicon substrate 1 or the well region 2 can be prevented, and shallow diffusion layers 9, 9, 10, 10 with low sheet resistance can be formed. This makes it possible to improve manufacturing yields and to achieve higher integration and higher performance of LSIs due to miniaturization of semiconductor elements.
なお、上記実施例では、ＬＤＤ構造を有する０ＭＯ８型
のＭＯＳ ＦＥＴの製造工程を例に取って説明したが
、この発明は上述した実施例に限られるものではなく、
素子分離領域を有し、拡散層上に高融点金属層を選択成
長させる工程を有する半導体装置であれば全てに適用で
きる。また、高融点金属としてタングステンを用いる場
合を例に取って説明したが、チタン（ＴＩ）、モリブデ
ン（Ｍｏ）、バナジウム（Ｖ）等を用いても良い。In addition, although the above embodiment has been explained by taking as an example the manufacturing process of an 0MO8 type MOS FET having an LDD structure, the present invention is not limited to the above embodiment.
The invention can be applied to any semiconductor device that has an element isolation region and includes a step of selectively growing a high melting point metal layer on a diffusion layer. Further, although the case where tungsten is used as the high melting point metal has been described as an example, titanium (TI), molybdenum (Mo), vanadium (V), etc. may also be used.
さらに、拡散層上に形成するシリコン層を拡散層と同じ
導電型にするために、ドーピングガス中に不純物を混入
したが、シリコン層（不純物を導入していない）の形成
後にイオン注入を行なっても良い。また、単にシリコン
層を形成するだけでも、後の熱処理工程において拡散層
中の不純物がシリコン層中に染み出して導入されるので
、各シリコン層はその下の拡散層と同一導電型となる。Furthermore, in order to make the silicon layer formed on the diffusion layer the same conductivity type as the diffusion layer, impurities were mixed into the doping gas, but ion implantation was performed after the formation of the silicon layer (in which no impurities were introduced). Also good. Further, even if a silicon layer is simply formed, impurities in the diffusion layer seep out and are introduced into the silicon layer in a subsequent heat treatment process, so each silicon layer has the same conductivity type as the diffusion layer below it.
［発明の効果］
以上説明したようにこの発明によれば、拡散層上に高融
点金属層を選択成長させても高融点金属層とシリコン基
板あるいはウェル領域とが短絡するのを防止でき、製造
歩留りを向上できる半導体装置の製造方法が得られる。[Effects of the Invention] As explained above, according to the present invention, even if the high melting point metal layer is selectively grown on the diffusion layer, short-circuiting between the high melting point metal layer and the silicon substrate or well region can be prevented, and manufacturing A method for manufacturing a semiconductor device that can improve yield can be obtained.
第１図はこの発明の一実施例に係わる半導体ｉｉｍの製
造方法について説明するための断面図、第２図は従来の
半導体装置の製造方法について説明するための断面図で
ある。
１・・・シリコン基板、２・・・ウェル領域、３・・・
素子分離領域、９ 、９ 、１０．１０・・・拡散ＩＩ
（ソース。
ドレイン領域） 、１１．１１．・・・ ・・・高融点
金属層、１２・・・マスク（シリコン酸化膜） 、１３
．１４・・・シリコン層。
、出願人代理人 弁理士 鈴江武彦
第１図FIG. 1 is a cross-sectional view for explaining a method of manufacturing a semiconductor IIM according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view for explaining a conventional method of manufacturing a semiconductor device. 1... Silicon substrate, 2... Well region, 3...
Element isolation region, 9, 9, 10.10...diffusion II
(Source. Drain region), 11.11. ... ... High melting point metal layer, 12 ... Mask (silicon oxide film), 13
．． 14...Silicon layer. , Applicant's agent Patent attorney Takehiko Suzue Figure 1
Claims (9)
する工程と、この半導体領域の表面領域に前記素子分離
領域に接した第２導電型の拡散層を形成する工程と、前
記素子分離領域と前記拡散層との界面上をマスクして前
記拡散層上に高融点金属を選択成長させることにより前
記拡散層のシート抵抗を低減させるための高融点金属層
を形成する工程と、前記素子分離領域と前記拡散層との
界面上のマスクした部分の前記拡散層上にシリコンを選
択成長させて第２導電型のシリコン層を形成する工程と
を具備することを特徴とする半導体装置の製造方法。(1) forming an element isolation region on a semiconductor region of a first conductivity type; forming a diffusion layer of a second conductivity type in contact with the element isolation region in a surface region of this semiconductor region; forming a high melting point metal layer for reducing the sheet resistance of the diffusion layer by selectively growing a high melting point metal on the diffusion layer while masking the interface between the separation region and the diffusion layer; selectively growing silicon on the masked portion of the diffusion layer on the interface between the element isolation region and the diffusion layer to form a silicon layer of a second conductivity type. Production method.
徴とする特許請求の範囲第１項記載の半導体装置の製造
方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor region is a silicon substrate.
ウェル領域であることを特徴とする特許請求の範囲第１
項記載の半導体装置の製造方法。(3) Claim 1, wherein the semiconductor region is a well region formed in a silicon substrate.
A method for manufacturing a semiconductor device according to section 1.
の範囲第１項記載の半導体装置の製造方法。(4) The method of manufacturing a semiconductor device according to claim 1, wherein the diffusion layer is a source or drain region of a MOSFET.
リブデン、あるいはバナジウムから成ることを特徴とす
る特許請求の範囲第１項記載の半導体装置の製造方法。(5) The method for manufacturing a semiconductor device according to claim 1, wherein the high melting point metal layer is made of tungsten, titanium, molybdenum, or vanadium.
徴とする特許請求の範囲第１項記載の半導体装置の製造
方法。(6) The method of manufacturing a semiconductor device according to claim 1, wherein the mask is made of a silicon oxide film.
前記素子分離領域との界面上にシリコンを選択成長させ
て形成したシリコン層に、後の熱処理工程において前記
拡散層中の不純物が導入されることにより形成されるも
のであることを特徴とする特許請求の範囲第１項記載の
半導体装置の製造方法。(7) The silicon layer of the second conductivity type is formed by selectively growing silicon on the interface between the diffusion layer and the element isolation region. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed by introducing a semiconductor device.
層上にシリコンを選択成長させる際に、反応ガス中に第
２導電型を形成する不純物を混入することにより形成す
るものであることを特徴とする特許請求の範囲第１項記
載の半導体装置の製造方法。(8) The silicon layer of the second conductivity type is formed by mixing an impurity forming the second conductivity type into the reaction gas when selectively growing silicon on the diffusion layer. A method for manufacturing a semiconductor device according to claim 1, characterized in that:
層上にシリコンを選択成長させた後に、第２導電型を形
成する不純物をイオン注入して形成するものであること
を特徴とする特許請求の範囲第１項記載の半導体装置の
製造方法。(9) The silicon layer of the second conductivity type is formed by selectively growing silicon on the diffusion layer and then implanting impurities forming the second conductivity type by ion implantation. A method for manufacturing a semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62295671A JPH01136371A (en) | 1987-11-24 | 1987-11-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62295671A JPH01136371A (en) | 1987-11-24 | 1987-11-24 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01136371A true JPH01136371A (en) | 1989-05-29 |
| JPH0557735B2 JPH0557735B2 (en) | 1993-08-24 |
Family
ID=17823679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62295671A Granted JPH01136371A (en) | 1987-11-24 | 1987-11-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01136371A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03188367A (en) * | 1989-09-28 | 1991-08-16 | Agency Of Ind Science & Technol | Carbon microelectrode and manufacture thereof |
-
1987
- 1987-11-24 JP JP62295671A patent/JPH01136371A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03188367A (en) * | 1989-09-28 | 1991-08-16 | Agency Of Ind Science & Technol | Carbon microelectrode and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0557735B2 (en) | 1993-08-24 |
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