JPS6333868A - Manufacture of mis field-effect transistor - Google Patents
Manufacture of mis field-effect transistorInfo
- Publication number
- JPS6333868A JPS6333868A JP17821786A JP17821786A JPS6333868A JP S6333868 A JPS6333868 A JP S6333868A JP 17821786 A JP17821786 A JP 17821786A JP 17821786 A JP17821786 A JP 17821786A JP S6333868 A JPS6333868 A JP S6333868A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- film
- thin
- oxide film
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000010409 thin film Substances 0.000 claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 15
- 150000002500 ions Chemical class 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000013078 crystal Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- 239000010408 film Substances 0.000 abstract description 15
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 6
- 239000011574 phosphorus Substances 0.000 abstract description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 239000000969 carrier Substances 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 230000002040 relaxant effect Effects 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- -1 phosphorus ions Chemical class 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ＭＩＳ型電界効果トランジスタの製造方法に
関し、特にホットキャリヤによる素子性能の劣化の少な
いＭＩＳ型電界効果トランジスタの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing an MIS field effect transistor, and more particularly to a method for manufacturing an MIS field effect transistor in which device performance is less degraded by hot carriers.
ホットキャリアによる素子性能の劣化の少ないＭＩＳ型
電界効果トランジスタとしては、例えばソース・ドレイ
ン領域のゲート電極近傍で不純物濃度が低くなったＬＤ
Ｄ構造が提案されている。As a MIS field effect transistor with less deterioration in device performance due to hot carriers, for example, an LD with a low impurity concentration near the gate electrode in the source/drain region.
D structure has been proposed.
従来、ＬＤＤ構造を得るためには、ゲート電極形成後、
ソース・ドレイン領域に低濃度のリンのイオン注入を行
い、その後イオン注入のマスクをゲート電極側壁に自己
整合的に形成し、高濃度のヒ素をイオン注入する方法が
用いられている。Conventionally, in order to obtain an LDD structure, after forming the gate electrode,
A method is used in which ions of low concentration phosphorus are implanted into the source/drain regions, then an ion implantation mask is formed in a self-aligned manner on the side wall of the gate electrode, and ions of arsenic are implanted at a high concentration.
しかしながら、上述した従来の製造方法では、ソ
ゲート電極形成後状−スおよびドレインを形成するたあ
たシ、２度のイオン注入を行う工程と、イオン注入のマ
スクをゲート電極側壁に自己整合的に形成する工程とを
必要とするため、製造方法が複雑になシかつ、ウェハ面
内およびウェア１間のパラツギが大きくなるという欠点
がある。However, in the above-mentioned conventional manufacturing method, after forming the gate electrode, there are steps for forming the source and drain, and two ion implantation steps, and the ion implantation mask is self-aligned with the sidewall of the gate electrode. Since this requires a step of forming, the manufacturing method is complicated, and there are disadvantages in that variations within the wafer surface and between the wafers 1 are increased.
本発明は、ＭＩＳ型電界効果トランジスタのＪ−ス・ド
レインの不純物拡散領域を第１の導電型のシリコン単結
晶基板の一主面に形成する堀たシ、ゲート電極となる導
電性薄膜を含む１層以上の薄膜を被着する工程と、この
薄膜を７オトレジストによるパターニング後テーパーエ
ツチングする工程と、絶縁性の薄膜を被着する工程と、
逆導電型の不純物イオンを絶縁性の薄膜およびゲート電
極部薄膜のテーパーの一部を透過し、ソース・ドレイン
形成領域のシリコン基板中に到達するエネルギーでイオ
ン注入する工程を有している。The present invention includes a trench for forming an impurity diffusion region of a J-S drain of a MIS type field effect transistor on one main surface of a silicon single crystal substrate of a first conductivity type, and a conductive thin film serving as a gate electrode. a step of depositing one or more thin films; a step of patterning this thin film with a 7-photoresist and taper etching; a step of depositing an insulating thin film;
This process involves implanting impurity ions of the opposite conductivity type with energy that passes through a part of the taper of the insulating thin film and the gate electrode thin film and reaches the silicon substrate in the source/drain forming region.
このように、本発明によれば、ゲート電極をテーパーエ
ツチングし、その上に被着した絶縁性薄膜およびゲート
電極部薄膜のテーパーの一部を透過するエネルギーで不
純物のイオン注入を行うことによシ、１度のイオン注入
工程で、ゲート電極の隣接する部分が低不純物濃度とな
ったソースおよびドレイン領域を設けることができる。As described above, according to the present invention, the gate electrode is taper-etched, and impurity ions are implanted with energy that passes through the insulating thin film deposited thereon and a part of the taper of the gate electrode thin film. Second, by a single ion implantation process, source and drain regions in which adjacent portions of the gate electrode have a low impurity concentration can be provided.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（Ｑ〜（Φは本発明の一実施例を工程順に示した
縦断面図である。Ｐ型シリコン単結晶基板１上の素子領
域上にゲート酸化膜２を形成し、ゲート電極として例え
ば多結晶シリコン薄膜３をａｏｏｏＸの膜厚で被着し、
フォトレジストによるマスクを用いてテーパーエツチン
グを行いゲート電極４ｆ！ｃ形成する。その後、絶縁膜
として例えば酸化膜５をｘｏｏｏＸ程度被着し、酸化膜
５とゲート電極４のテーパーの一部を透過するエネルギ
ーでリンのイオン注入６を行う。以下、層間絶縁膜を被
着し、通常の製造方法により、ＭＩＳ型電界効果トラン
ジスタを得ることができる。FIG. 1 (Q~(Φ) is a vertical cross-sectional view showing an embodiment of the present invention in the order of steps. A gate oxide film 2 is formed on the element region on a P-type silicon single crystal substrate 1, and is used as a gate electrode. For example, a polycrystalline silicon thin film 3 is deposited with a film thickness of aoooX,
Taper etching is performed using a photoresist mask and the gate electrode 4f! c form. Thereafter, for example, an oxide film 5 is deposited as an insulating film to an extent of xoooox, and phosphorus ions are implanted 6 with energy that passes through the oxide film 5 and a part of the taper of the gate electrode 4. Thereafter, an interlayer insulating film is deposited, and a MIS field effect transistor can be obtained by a normal manufacturing method.
この実施例において、酸化膜５は、接合深さが深くなシ
すぎない様にしてゲート電極４のテーパーの一部を不純
物イオンが透過する様に設けである。これにより、ゲー
ト電極４の近傍では不純物濃度が低くなったソース・ド
レイン領域を一度で得ることができ、このリンの低濃度
領域でホットキャリヤ効果１に緩和することができる。In this embodiment, the oxide film 5 is provided so that the junction depth is not too deep so that impurity ions can pass through a part of the taper of the gate electrode 4. As a result, a source/drain region having a low impurity concentration near the gate electrode 4 can be obtained at once, and the hot carrier effect 1 can be alleviated in this low phosphorus concentration region.
〔実施例２〕
第２図（ａ）〜（ψは本発明の第２の実施例を工程順に
示した縦断面図である。本実施例では、ゲート電極とし
て金橋シリサイド８と多結晶シリコン３との２層で構成
されている。金属シリサイド８を所定形状にエツチング
後、多結晶シリコン３？テーパーエツチングし、絶縁膜
５を被覆後、絶縁膜５と多結晶シリコン３のテーパーの
一部を透過するエネルギーで不純物濃度となったソース
・ドレイン領域を得ることができる。[Example 2] Figures 2(a) to (ψ are vertical cross-sectional views showing the second example of the present invention in the order of steps. In this example, gold bridge silicide 8 and polycrystalline silicon 3 are used as gate electrodes. After etching the metal silicide 8 into a predetermined shape, taper etching the polycrystalline silicon 3 and covering the insulating film 5. It is possible to obtain source/drain regions with an impurity concentration due to the transmitted energy.
以上説明したように、本発明は、ＭＩＳ型電界効果トラ
ンジスタにおけるソース・ドレインの形成にあたり、ゲ
ート電極となる薄膜をテーパーエツチングし、その後絶
縁性＃腹を被着し、絶縁性薄膜およびゲート電極のテー
パーの一部を透過するエネルギーで不純物イオンの注入
を行うことによシ、プロセスが単純で制御性が良く、ホ
ットキャリアによる素子性能の劣化の少ないＭＩＳ型電
界効果トランジスタを製造できる。As explained above, in forming the source/drain in a MIS field effect transistor, the present invention taper-etches a thin film that will become the gate electrode, and then deposits an insulating film to form the insulating thin film and the gate electrode. By implanting impurity ions with energy that passes through a portion of the taper, a MIS field effect transistor can be manufactured with a simple process, good controllability, and less deterioration of device performance due to hot carriers.
第１図（ａ）〜（ψは本発明の第１の実施例を工程順に
示した縦断面図、第２図（ａ）〜（Φは本発明の第２の
実施例を工程順に示した縦断面図である。
１・・・・・・Ｐ型シリコン単結晶基板、２・・・・・
・ゲート酸化膜、３・・・・・・多結晶シリコン薄膜、
４・・・・・・ゲート電極、４・・・・・・酸化膜、６
・・・・・・リンのイオン注入、７・・・・・・不純物
拡散領域、８・・・・・・金属シリサイド薄膜。
第 １ ワ
、、ｌＱリイに５５１人
第２ 図Figures 1(a) to (ψ are vertical sectional views showing the first embodiment of the present invention in the order of steps; Figures 2(a) to (Φ) are longitudinal cross-sectional views showing the second embodiment of the present invention in the order of steps. It is a vertical cross-sectional view. 1... P-type silicon single crystal substrate, 2...
・Gate oxide film, 3...polycrystalline silicon thin film,
4... Gate electrode, 4... Oxide film, 6
... Phosphorus ion implantation, 7 ... Impurity diffusion region, 8 ... Metal silicide thin film. 1st Wow, 551 people in lQ 2nd figure
Claims (1)
レインの不純拡散領域を一の導電型のシリコン単結晶基
板の一主面に形成するにあたり、ゲート電極となる薄膜
を被着する工程と、前記薄膜をテーパーエッチングによ
ってゲート電極形状に形成する工程と、逆導電型の不純
物イオンを前記ゲート電極部のテーパーの一部を透過し
ソース・ドレイン領域のシリコン基板中に到達するエネ
ルギーでイオン注入する工程とを有することを特徴とす
るＭＩＳ型電界効果トランジスタの製造方法。(1) In forming impurity diffusion regions for the source and drain of a MIS field effect transistor on one main surface of a silicon single crystal substrate of one conductivity type, a process of depositing a thin film that will become a gate electrode, and a process of depositing the thin film A step of forming a gate electrode shape by taper etching, and a step of implanting impurity ions of the opposite conductivity type with an energy that passes through a part of the taper of the gate electrode portion and reaches the silicon substrate in the source/drain region. A method for manufacturing an MIS field effect transistor, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17821786A JPS6333868A (en) | 1986-07-28 | 1986-07-28 | Manufacture of mis field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17821786A JPS6333868A (en) | 1986-07-28 | 1986-07-28 | Manufacture of mis field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6333868A true JPS6333868A (en) | 1988-02-13 |
Family
ID=16044631
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17821786A Pending JPS6333868A (en) | 1986-07-28 | 1986-07-28 | Manufacture of mis field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6333868A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04158861A (en) * | 1990-10-22 | 1992-06-01 | Mikio Fukunaga | Spine correction therapeutic apparatus |
| JP2010232635A (en) * | 2009-03-27 | 2010-10-14 | Samsung Mobile Display Co Ltd | Thin film transistor, method of fabricating the same, and organic electroluminescent display device including the same |
| US8409887B2 (en) | 2009-03-03 | 2013-04-02 | Samsung Display Co., Ltd. | Organic light emitting diode display device and method of fabricating the same |
| US8546248B2 (en) | 2009-03-05 | 2013-10-01 | Samsung Display Co., Ltd. | Method of forming polycrystalline silicon layer and atomic layer deposition apparatus used for the same |
| US8890165B2 (en) | 2009-11-13 | 2014-11-18 | Samsung Display Co., Ltd. | Method of forming polycrystalline silicon layer, thin film transistor, organic light emitting diode display device having the same, and methods of fabricating the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5816566A (en) * | 1981-07-22 | 1983-01-31 | Hitachi Ltd | Semiconductor device and manufacture thereof |
-
1986
- 1986-07-28 JP JP17821786A patent/JPS6333868A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5816566A (en) * | 1981-07-22 | 1983-01-31 | Hitachi Ltd | Semiconductor device and manufacture thereof |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04158861A (en) * | 1990-10-22 | 1992-06-01 | Mikio Fukunaga | Spine correction therapeutic apparatus |
| JPH0553502B2 (en) * | 1990-10-22 | 1993-08-10 | Mikio Fukunaga | |
| US8409887B2 (en) | 2009-03-03 | 2013-04-02 | Samsung Display Co., Ltd. | Organic light emitting diode display device and method of fabricating the same |
| US9035311B2 (en) | 2009-03-03 | 2015-05-19 | Samsung Display Co., Ltd. | Organic light emitting diode display device and method of fabricating the same |
| US8546248B2 (en) | 2009-03-05 | 2013-10-01 | Samsung Display Co., Ltd. | Method of forming polycrystalline silicon layer and atomic layer deposition apparatus used for the same |
| JP2010232635A (en) * | 2009-03-27 | 2010-10-14 | Samsung Mobile Display Co Ltd | Thin film transistor, method of fabricating the same, and organic electroluminescent display device including the same |
| US9117798B2 (en) | 2009-03-27 | 2015-08-25 | Samsung Display Co., Ltd. | Thin film transistor, method of fabricating the same and organic light emitting diode display device including the same |
| US8890165B2 (en) | 2009-11-13 | 2014-11-18 | Samsung Display Co., Ltd. | Method of forming polycrystalline silicon layer, thin film transistor, organic light emitting diode display device having the same, and methods of fabricating the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2735041B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH0923010A (en) | Semiconductor element and its preparation | |
| US7413954B2 (en) | Insulated gate semiconductor device and manufacturing method of the same | |
| US4948744A (en) | Process of fabricating a MISFET | |
| JPS6333868A (en) | Manufacture of mis field-effect transistor | |
| JPS63257231A (en) | Manufacture of semiconductor device | |
| JPS6251216A (en) | Manufacture of semiconductor device | |
| JPH0758785B2 (en) | Method for manufacturing vertical field effect transistor | |
| JPS6014471A (en) | Manufacture of semiconductor device | |
| JPH01181566A (en) | Insulated gate field effect transistor and its manufacture | |
| KR950007396B1 (en) | Making method of vertical mos transistor | |
| KR100305205B1 (en) | Method for manufacturing semiconductor device | |
| JP3144509B2 (en) | Method for manufacturing semiconductor device | |
| JPS6154661A (en) | Manufacture of semiconductor device | |
| JP3848782B2 (en) | Manufacturing method of semiconductor device | |
| US20030216005A1 (en) | Method for forming transistor of semiconductor device | |
| JPS6039868A (en) | Manufacture of semiconductor device | |
| KR0135670B1 (en) | Method of manufacturing semiconductor device | |
| KR940004266B1 (en) | Manufacturing method of cmos | |
| JPS6395664A (en) | Semiconductor device and manufacture thereof | |
| JPS62147776A (en) | Manufacture of semiconductor device | |
| JPH0555585A (en) | Manufacture of insulated-gate field-effect transistor | |
| JPH01191478A (en) | Manufacture of semiconductor device | |
| JPS60119781A (en) | Manufacture of semiconductor device | |
| JPH06275839A (en) | Manufacture of vertical semiconductor element |