JP7425839B2 - フェイルセーフic製造テスト - Google Patents
フェイルセーフic製造テスト Download PDFInfo
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- JP7425839B2 JP7425839B2 JP2022116639A JP2022116639A JP7425839B2 JP 7425839 B2 JP7425839 B2 JP 7425839B2 JP 2022116639 A JP2022116639 A JP 2022116639A JP 2022116639 A JP2022116639 A JP 2022116639A JP 7425839 B2 JP7425839 B2 JP 7425839B2
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- test
- integrated circuit
- volatile memory
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- 238000012360 testing method Methods 0.000 title claims description 269
- 238000004519 manufacturing process Methods 0.000 title claims description 36
- 238000000034 method Methods 0.000 claims description 26
- 230000004913 activation Effects 0.000 claims description 8
- 230000003213 activating effect Effects 0.000 claims description 3
- 230000006870 function Effects 0.000 description 7
- 230000004044 response Effects 0.000 description 7
- 239000002131 composite material Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000009471 action Effects 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- 206010000210 abortion Diseases 0.000 description 2
- 230000001186 cumulative effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000977 initiatory effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000010998 test method Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000013523 data management Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
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- 230000003287 optical effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/027—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in fuses
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56008—Error analysis, representation of errors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/20—Initialising; Data preset; Chip identification
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
Landscapes
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
集積回路(IC)製造テスト(PT)は、製造後にICをテストし、欠陥部品を選別するように用いられている。通常、PTは、パラメータの調整、キャリブレーション、個別のシリアル番号の挿入、およびその他のパーソナライゼーション機能にも用いられる。
102 集積回路(IC)
104 自動テスト装置(ATE)
106 テストポート
108 機能回路
109 制御回路
110 ビルトインセルフテスト(BIST)回路
112 ワンタイムプログラマブル(OTP)メモリ
200 フローチャート
202~214 ステップ
300 フローチャート
302~316 ステップ
400 ブロック図
402 OTPワード
404 反復
408 例ボックス
500 フローチャート
502~508 ステップ
600 フローチャート
602~606 ステップ
650 フローチャート
652~658 ステップ
Claims (16)
- 不揮発性メモリ、および
集積回路の製造テストが正常に完了したかどうかを示す1つ又は2つ以上の完了示唆値を前記不揮発性メモリから読み取り、前記集積回路を起動しているときに、読み取った前記完了示唆値をチェックするように構成された起動回路を含み、
前記完了示唆値が、前記製造テストが正常に完了したことを示した場合、前記起動回路は前記集積回路をさらに起動し、及び
前記完了示唆値が、前記製造テストが正常に完了されなかったことを示した場合、前記起動回路は前記集積回路を起動することを中止する、集積回路(IC)。 - 前記完了示唆値は、単一のパス/フェイルビットで構成されている請求項1に記載の集積回路。
- 前記完了示唆値は、外部自動テスト装置(ATE)によって不揮発性メモリに書き込まれている請求項1に記載の集積回路。
- 前記製造テストが正常に完了したかどうかを示す情報を外部自動テスト装置(ATE)から受け取り、前記情報に基づいて前記完了示唆値を前記不揮発性メモリに書き込むように構成された制御回路をさらに含む請求項1に記載の集積回路。
- 前記完了示唆値は、回復不可能テストパス指示、回復不可能テストフェイル指示、回復可能テストフェイル指示、および回復可能テストパス指示のうちの1つ以上を含む請求項1に記載の集積回路。
- 2つ以上の前記完了示唆値は相互に直交している請求項1に記載の集積回路。
- 前記不揮発性メモリは、ワンタイムプログラマブル(OTP)メモリである請求項1に記載の集積回路。
- 前記不揮発性メモリは、マルチタイムプログラマブル不揮発性メモリ(MTP NVM)である請求項1に記載の集積回路。
- 不揮発性メモリを含む集積回路(IC)を起動するステップを含み、
前記集積回路の製造テストが正常に完了したかどうかを示す1つ又は2つ以上の完了示唆値を前記不揮発性メモリから読み取り、読み取った前記完了示唆値をチェックするステップ、および
前記完了示唆値が、前記製造テストが正常に完了したことを示した場合、前記集積回路をさらに起動し、前記完了示唆値が、前記製造テストが正常に完了されなかったことを示した場合、前記集積回路を起動することを中止するステップを含む方法。 - 前記完了示唆値は、単一のパス/フェイルビットで構成されている請求項9に記載の方法。
- 前記完了示唆値は、外部自動テスト装置(ATE)によって不揮発性メモリに書き込まれている請求項9に記載の方法。
- 前記集積回路で前記製造テストが正常に完了したかどうかを示す情報を外部自動テスト装置(ATE)から受け取り、前記情報に基づいて前記完了示唆値を前記不揮発性メモリに書き込むステップをさらに含む請求項9に記載の方法。
- 前記完了示唆値は、回復不可能テストパス指示、回復不可能テストフェイル指示、回復可能テストフェイル指示、および回復可能テストパス指示のうちの1つ以上を含む請求項9に記載の方法。
- 2つ以上の前記完了示唆値は相互に直交している請求項9に記載の方法。
- 前記不揮発性メモリは、ワンタイムプログラマブル(OTP)メモリである請求項9に記載の方法。
- 前記不揮発性メモリは、マルチタイムプログラマブル不揮発性メモリ(MTP NVM)である請求項9に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/463,631 US11495313B1 (en) | 2021-09-01 | 2021-09-01 | Fail-safe IC production testing |
US17/463631 | 2021-09-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2023035864A JP2023035864A (ja) | 2023-03-13 |
JP7425839B2 true JP7425839B2 (ja) | 2024-01-31 |
Family
ID=83902359
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2022116639A Active JP7425839B2 (ja) | 2021-09-01 | 2022-07-21 | フェイルセーフic製造テスト |
Country Status (4)
Country | Link |
---|---|
US (1) | US11495313B1 (ja) |
JP (1) | JP7425839B2 (ja) |
CN (1) | CN115732024A (ja) |
TW (1) | TW202311953A (ja) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009027010A (ja) | 2007-07-20 | 2009-02-05 | Hitachi Ltd | 半導体装置 |
WO2012023211A1 (ja) | 2010-08-20 | 2012-02-23 | 富士通株式会社 | 半導体装置 |
US20120124441A1 (en) | 2010-11-17 | 2012-05-17 | Hoy Technologies Co | Embedded testing module and testing method thereof |
US20190033367A1 (en) | 2017-11-02 | 2019-01-31 | Intel Corporation | System, Apparatus And Method For Functional Testing Of One Or More Fabrics Of A Processor |
JP6611877B1 (ja) | 2018-07-25 | 2019-11-27 | 三菱電機株式会社 | 半導体集積回路および回転検出装置 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7249109B1 (en) * | 1997-07-15 | 2007-07-24 | Silverbrook Research Pty Ltd | Shielding manipulations of secret data |
US7984286B2 (en) * | 2008-06-25 | 2011-07-19 | Intel Corporation | Apparatus and method for secure boot environment |
US8650446B2 (en) | 2010-03-24 | 2014-02-11 | Apple Inc. | Management of a non-volatile memory based on test quality |
KR20170016108A (ko) | 2015-08-03 | 2017-02-13 | 삼성전자주식회사 | 오티피 메모리 장치의 프로그램 방법 및 이를 포함하는 반도체 집적 회로의 테스트 방법 |
-
2021
- 2021-09-01 US US17/463,631 patent/US11495313B1/en active Active
-
2022
- 2022-03-03 TW TW111107652A patent/TW202311953A/zh unknown
- 2022-04-20 CN CN202210415139.7A patent/CN115732024A/zh active Pending
- 2022-07-21 JP JP2022116639A patent/JP7425839B2/ja active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009027010A (ja) | 2007-07-20 | 2009-02-05 | Hitachi Ltd | 半導体装置 |
WO2012023211A1 (ja) | 2010-08-20 | 2012-02-23 | 富士通株式会社 | 半導体装置 |
US20120124441A1 (en) | 2010-11-17 | 2012-05-17 | Hoy Technologies Co | Embedded testing module and testing method thereof |
US20190033367A1 (en) | 2017-11-02 | 2019-01-31 | Intel Corporation | System, Apparatus And Method For Functional Testing Of One Or More Fabrics Of A Processor |
JP6611877B1 (ja) | 2018-07-25 | 2019-11-27 | 三菱電機株式会社 | 半導体集積回路および回転検出装置 |
Also Published As
Publication number | Publication date |
---|---|
TW202311953A (zh) | 2023-03-16 |
CN115732024A (zh) | 2023-03-03 |
JP2023035864A (ja) | 2023-03-13 |
US11495313B1 (en) | 2022-11-08 |
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