JP7407203B2 - スタティックランダムアクセスメモリを有する3次元メモリデバイスのキャッシュプログラム動作 - Google Patents
スタティックランダムアクセスメモリを有する3次元メモリデバイスのキャッシュプログラム動作 Download PDFInfo
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- JP7407203B2 JP7407203B2 JP2021559120A JP2021559120A JP7407203B2 JP 7407203 B2 JP7407203 B2 JP 7407203B2 JP 2021559120 A JP2021559120 A JP 2021559120A JP 2021559120 A JP2021559120 A JP 2021559120A JP 7407203 B2 JP7407203 B2 JP 7407203B2
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Description
Claims (16)
- 3次元(3D)メモリデバイスであって、
複数のページを有する3D NANDメモリアレイと、
同じチップ上のページバッファを介して前記メモリアレイに結合され、ホストと前記メモリアレイとの間のプログラムデータの複数のバッチをキャッシュするように構成されたオンダイキャッシュであって、スタティックランダムアクセスメモリ(SRAM)セルを含むオンダイキャッシュと、
前記同じチップ上の前記オンダイキャッシュに結合されたコントローラであって、
プログラムデータの(N-2)番目のバッチのステータスをチェックし、Nは2以上の整数であり、
プログラムデータの(N-1)番目のバッチを前記3D NANDメモリアレイ内のそれぞれのページにプログラムし、
プログラムデータのN番目のバッチのバックアップコピーとして、プログラムデータの前記N番目のバッチを前記オンダイキャッシュ内のそれぞれの空間にキャッシュするように構成される、コントローラと、を含む、3Dメモリデバイス。 - 前記コントローラは、同時に、プログラムデータの(N-2)番目のバッチのステータスをチェックし、プログラムデータの(N-1)番目のバッチをプログラムし、プログラムデータのN番目のバッチをキャッシュするように構成される、請求項1に記載の3Dメモリデバイス。
- プログラムデータの前記(N-2)番目のバッチが失敗したという前記ステータスに応答して、前記コントローラは、プログラムデータの前記(N-2)番目のバッチのバックアップコピーを前記オンダイキャッシュから取得し、プログラムデータの前記(N-2)番目のバッチの前記バックアップコピーを、前記3D NANDメモリアレイ内のそれぞれのページにプログラムするようにさらに構成される、請求項2に記載の3Dメモリデバイス。
- 前記コントローラは、
プログラムデータの前記N番目のバッチを前記オンダイキャッシュから読み出し、
前記読み出したプログラムデータのN番目のバッチを前記ホストに送信するように構成される、請求項1に記載の3Dメモリデバイス。 - 前記コントローラは、
プログラムデータの前記(N-2)番目のバッチが前記3D NANDメモリアレイ内のそれぞれのページにプログラムされているときに、プログラムデータの前記(N-1)番目のバッチのバックアップコピーとして、プログラムデータの前記(N-1)番目のバッチを前記ホストから前記オンダイキャッシュにキャッシュするように構成される、請求項1に記載の3Dメモリデバイス。 - 前記コントローラは、
プログラムデータの前記(N-1)番目のバッチのステータスをチェックし、
プログラムデータの前記N番目のバッチを前記3D NANDメモリアレイ内のそれぞれのページにプログラムし、
プログラムデータの(N+1)番目のバッチを前記オンダイキャッシュ内のそれぞれの空間にキャッシュするようにさらに構成される、
請求項1に記載の3Dメモリデバイス。 - プログラムデータのそれぞれのバッチを前記3D NANDメモリアレイ内のそれぞれのページにプログラムするために、前記コントローラは、
プログラムデータの前記それぞれのバッチのバッファされたコピーをそれぞれのページバッファから取得し、
プログラムデータの前記それぞれのバッチの前記バッファされたコピーを、前記3D NANDメモリアレイ内の前記それぞれのページにプログラムするようにさらに構成される、請求項1に記載の3Dメモリデバイス。 - 前記コントローラは、プログラムデータの前記それぞれのバッチが前記それぞれのページにプログラムされる前に、プログラムデータの前記それぞれのバッチを前記それぞれのページバッファにバッファするようにさらに構成される、請求項7に記載の3Dメモリデバイス。
- 前記3Dメモリデバイスは、埋め込み型マルチメディアカード(eMMC)またはユニバーサルフラッシュストレージ(UFS)のうちの少なくとも1つにパッケージ化される、請求項1に記載の3Dメモリデバイス。
- 3次元(3D)メモリデバイス上でキャッシュプログラム動作を実行するためのシステムであって、
ホストと、
複数ページのNANDメモリセルを有し、前記ホストに接続された記憶ユニットと、
前記記憶ユニットと同じチップ上にあり同じチップにてページバッファを介して前記記憶ユニットに結合され、前記ホストと前記記憶ユニットとの間のプログラムデータの複数のバッチをキャッシュするように構成され、オンダイスタティックランダムアクセスメモリ(SRAM)セルを含むキャッシュユニットと、
前記キャッシュユニットおよび前記ホストに結合された制御ユニットであって、
前記ホストから前記記憶ユニットにプログラムされたプログラムデータの(N-2)番目のバッチのステータスをチェックし、Nは2以上の整数であり、
プログラムデータの(N-1)番目のバッチを前記記憶ユニットのそれぞれのページにプログラムし、
プログラムデータのN番目のバッチのバックアップコピーとして、前記キャッシュユニット内のそれぞれの空間にプログラムデータの前記N番目のバッチをキャッシュするように構成される、制御ユニットと、を含む、システム。 - 前記制御ユニットは、同時に、プログラムデータの(N-2)番目のバッチのステータスをチェックし、プログラムデータの(N-1)番目のバッチをプログラムし、プログラムデータのN番目のバッチをキャッシュするように構成される、請求項10に記載のシステム。
- プログラムデータの前記(N-2)番目のバッチが失敗したという前記ステータスに応答して、前記制御ユニットは、プログラムデータの前記(N-2)番目のバッチのバックアップコピーを前記キャッシュユニットから取得し、プログラムデータの前記(N-2)番目のバッチの前記バックアップコピーを前記記憶ユニットのそれぞれのページにプログラムするようにさらに構成される、請求項11に記載のシステム。
- 前記制御ユニットは、
プログラムデータの前記N番目のバッチを前記キャッシュユニットから読み出し、
前記読み出したプログラムデータの前記N番目のバッチを前記ホストに送信するようにさらに構成される、請求項10に記載のシステム。 - 前記制御ユニットは、
プログラムデータの前記(N-2)番目のバッチが前記記憶ユニットのそれぞれのページにプログラムされているときに、プログラムデータの前記(N-1)番目のバッチのバックアップコピーとして、プログラムデータの前記(N-1)番目のバッチを前記ホストから前記キャッシュユニットにキャッシュするようにさらに構成される、請求項10に記載のシステム。 - 3次元(3D)メモリデバイス上でキャッシュプログラム動作を実行するための方法であって、
ホストから記憶ユニットにプログラムされたプログラムデータの第(N-2)番目のバッチのステータスをチェックすることであって、Nは2以上の整数である、ことと、
プログラムデータの(N-1)番目のバッチを3D NANDメモリアレイ内のそれぞれのページにプログラムすることと、
プログラムデータのN番目のバッチのバックアップコピーとして、プログラムデータの前記N番目のバッチをオンダイスタティックランダムアクセスメモリ(SRAM)セル内のそれぞれの空間にキャッシュすることと、を含み、
前記プログラムデータの前記(N-1)番目のバッチを前記3D NANDメモリアレイ内のそれぞれのページにプログラムすることは、前記プログラムデータの前記(N-1)番目のそれぞれのバッチのバッファされたコピーをそれぞれのページバッファから取得し、
前記プログラムデータの前記それぞれのバッチの前記バッファされたコピーを、前記3D NANDメモリアレイ内の前記それぞれのページにプログラムすることを含む、方法。 - プログラムデータの(N-2)番目のバッチのステータスをチェックすることと、プログラムデータの前記(N-1)番目のバッチをプログラムすることと、プログラムデータのN番目のバッチをキャッシュすることとが同時に実行される、請求項15に記載の方法。
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