JP7342060B2 - 複合配線基板、半導体装置及び複合配線基板の製造方法 - Google Patents
複合配線基板、半導体装置及び複合配線基板の製造方法 Download PDFInfo
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- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
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- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
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Description
第1実施形態は、複合配線基板及びその製造方法に関する。
まず、第1実施形態に係る複合配線基板の構造について説明する。図1は、第1実施形態に係る複合配線基板を示す断面図である。
次に、第1実施形態に係る複合配線基板1の製造方法について説明する。図3~図7は、第1実施形態に係る複合配線基板1の製造方法を示す断面図である。
次に、第2実施形態について説明する。第2実施形態は、半導体装置に関する。図9は、第2実施形態に係る半導体装置を示す断面図である。
2 半導体装置
20 半導体チップ
100 ビルドアップ基板
124 電極パッド
124A 輪郭
200 インターポーザ
211 電極パッド
211A 輪郭
300 接合材
310 第1部分
311、313 Cu3Sn層
312 Cu6Sn5層
314 微粒子
320 第2部分
Claims (13)
- 第1接続端子を備えた第1配線基板と、
前記第1接続端子に対向する第2接続端子を備えた第2配線基板と、
前記第1接続端子と前記第2接続端子とを接合する接合材と、
を有し、
平面視で、前記第1接続端子の第1輪郭は前記第2接続端子の第2輪郭の内側にあり、
前記接合材は、
前記第1接続端子及び前記第2接続端子の両方に接触し、Cu及びSnの金属間化合物からなる第1部分と、
平面視で、前記第1輪郭と前記第2輪郭との間の部分を含み、Bi及びSnの合金からなる第2部分と、
を有し、
前記第2部分は、BiをBiSn合金の共晶組成よりも高濃度で含有し、
前記第2部分は、前記第2接続端子から離間していることを特徴とする複合配線基板。 - 前記第1配線基板はビルドアップ基板であり、
前記第2配線基板はインターポーザであることを特徴とする請求項1に記載の複合配線基板。 - 前記第2接続端子の前記第1接続端子に対向する面の全体が、前記第1部分により覆われていることを特徴とする請求項1又は2に記載の複合配線基板。
- 前記第2部分におけるBiの割合は、30質量%以上75質量%以下であることを特徴とする請求項1乃至3のいずれか1項に記載の複合配線基板。
- 前記第1接続端子と前記第2接続端子との間の距離は6μm以下であることを特徴とする請求項1乃至4のいずれか1項に記載の複合配線基板。
- 前記第1接続端子と前記第2接続端子との間の距離は3μm以下であることを特徴とする請求項5に記載の複合配線基板。
- 前記接合材の平面視で前記第1輪郭の内側にある部分の体積は、
前記接合材の平面視で前記第1輪郭の外側にある部分の体積の50%以下であることを特徴とする請求項1乃至6のいずれか1項に記載の複合配線基板。 - 前記第2部分は、前記第1接続端子の周囲に環状に形成されていることを特徴とする請求項1乃至7のいずれか1項に記載の複合配線基板。
- 前記第2配線基板は、前記第2接続端子の側面を覆う絶縁層を有することを特徴とする請求項1乃至8のいずれか1項に記載の複合配線基板。
- 前記第2部分の融点は、240℃以下であることを特徴とする請求項1乃至9のいずれか1項に記載の複合配線基板。
- 前記接合材の平面視で前記第1輪郭の内側にある部分では、Biの割合が5質量%以下であることを特徴とする請求項1乃至10のいずれか1項に記載の複合配線基板。
- 請求項1乃至11のいずれか1項に記載の複合配線基板と、
前記第2配線基板の上に実装された半導体チップと、
を有することを特徴とする半導体装置。 - Cuを含有する第1接続端子を備えた第1配線基板を準備する工程と、
Cuを含有する第2接続端子を備えた第2配線基板を準備する工程と、
前記第2接続端子の上に、Bi及びSnを含有する第1接合材を設ける工程と、
前記第2接続端子を前記第1接続端子に対向させ、前記第1接合材が前記第1接続端子に接触するように、前記第1配線基板及び前記第2配線基板を配置し、前記第1接合材を前記第1接合材の融点未満の温度に加熱しながら前記第1配線基板と前記第2配線基板との間に圧力を印加し、前記第1接合材を圧縮変形させる工程と、
前記第1接合材を前記第1接合材の融点よりも高い温度に加熱しながら前記第1配線基板と前記第2配線基板との間に前記第1接合材を圧縮変形させる工程よりも弱い圧力を印加することにより、前記第1接合材と前記第1接続端子及び前記第2接続端子とを反応させ、前記第1接続端子と前記第2接続端子とを接合する接合材を形成する工程と、
を有し、
平面視で、前記第1接続端子の第1輪郭は前記第2接続端子の第2輪郭の内側にあり、
前記接合材は、
前記第1接続端子及び前記第2接続端子の両方に接触し、Cu及びSnの金属間化合物からなる第1部分と、
平面視で、前記第1輪郭と前記第2輪郭との間の部分を含み、Bi及びSnの合金からなる第2部分と、
を有し、
前記第2部分は、BiをBiSn合金の共晶組成よりも高濃度で含有し、
前記第2部分は、前記第2接続端子から離間していることを特徴とする複合配線基板の製造方法。
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JP2021079986A JP7342060B2 (ja) | 2021-05-10 | 2021-05-10 | 複合配線基板、半導体装置及び複合配線基板の製造方法 |
CN202210478241.1A CN115334745A (zh) | 2021-05-10 | 2022-04-29 | 复合配线基板、半导体装置及复合配线基板的制造方法 |
KR1020220053205A KR20220152937A (ko) | 2021-05-10 | 2022-04-29 | 복합 배선 기판, 반도체 장치 및 복합 배선 기판 제조방법 |
US17/661,585 US11706877B2 (en) | 2021-05-10 | 2022-05-02 | Composite wiring substrate and semiconductor device |
EP22171558.4A EP4090141A1 (en) | 2021-05-10 | 2022-05-04 | Composite wiring substrate, semiconductor device, and method of manufacturing composite wiring substrate |
TW111116953A TWI844016B (zh) | 2021-05-10 | 2022-05-05 | 複合配線基板、半導體裝置及複合配線基板的製造方法 |
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Citations (8)
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WO2010061428A1 (ja) | 2008-11-28 | 2010-06-03 | 富士通株式会社 | 電子装置の製造方法、電子部品搭載用基板及びその製造方法 |
WO2014115798A1 (ja) | 2013-01-28 | 2014-07-31 | 株式会社村田製作所 | はんだバンプの形成方法およびはんだバンプ |
JP2014146635A (ja) | 2013-01-28 | 2014-08-14 | Murata Mfg Co Ltd | はんだ接合方法およびはんだボールと電極との接合構造体 |
US20170098627A1 (en) | 2014-04-23 | 2017-04-06 | Massachusetts Institute Of Technology | Interconnect structures for fine pitch assembly of semiconductor structures |
JP2017112330A (ja) | 2015-12-18 | 2017-06-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2020205331A (ja) | 2019-06-17 | 2020-12-24 | 新光電気工業株式会社 | 配線基板の製造方法及び積層構造 |
US20210022247A1 (en) | 2019-07-17 | 2021-01-21 | Samsung Electronics Co., Ltd. | Electronic device including interposer |
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JP2014146635A (ja) | 2013-01-28 | 2014-08-14 | Murata Mfg Co Ltd | はんだ接合方法およびはんだボールと電極との接合構造体 |
US20170098627A1 (en) | 2014-04-23 | 2017-04-06 | Massachusetts Institute Of Technology | Interconnect structures for fine pitch assembly of semiconductor structures |
JP2017112330A (ja) | 2015-12-18 | 2017-06-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2020205331A (ja) | 2019-06-17 | 2020-12-24 | 新光電気工業株式会社 | 配線基板の製造方法及び積層構造 |
US20210022247A1 (en) | 2019-07-17 | 2021-01-21 | Samsung Electronics Co., Ltd. | Electronic device including interposer |
US20210098353A1 (en) | 2019-09-27 | 2021-04-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Package and Method of Manufacture |
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TW202245559A (zh) | 2022-11-16 |
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