JP7313302B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 67
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 238000000034 method Methods 0.000 title description 5
- 230000002093 peripheral effect Effects 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- 238000001816 cooling Methods 0.000 claims description 12
- 238000000465 moulding Methods 0.000 claims description 9
- 239000003566 sealing material Substances 0.000 claims description 8
- 229920005989 resin Polymers 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 6
- 239000000853 adhesive Substances 0.000 claims description 5
- 230000001070 adhesive effect Effects 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229920003002 synthetic resin Polymers 0.000 description 2
- 239000000057 synthetic resin Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
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Description
実施の形態1について、図面を用いて以下に説明する。図1は、実施の形態1に係る半導体装置100の平面図である。図2は、図1のA-A線断面図である。
次に、実施の形態2に係る半導体装置100について説明する。図12は、第1ケース部品7aと第2ケース部品7cが連結する前の状態を示す断面図である。図13は、第1ケース部品7aと第2ケース部品7cが連結した状態を示す断面図である。なお、実施の形態2において、実施の形態1で説明したものと同一の構成要素については同一符号を付して説明は省略する。
次に、実施の形態3に係る半導体装置100について説明する。図14は、実施の形態3に係る半導体装置100の断面図である。なお、実施の形態2において、実施の形態1で説明したものと同一の構成要素については同一符号を付して説明は省略する。
Claims (10)
- ベース板と、
前記ベース板の下面に固定された冷却板と、
前記ベース板の上面における周縁部を除く領域に固定された絶縁基板と、
前記絶縁基板の上面に搭載された半導体素子と、
前記ベース板の上面における周縁部に固定され、前記半導体素子を囲繞するケースと、
前記ケースと一体に形成され、かつ、一端部に形成された端子を有するリードフレームと、
前記ケース内に充填され、前記半導体素子を覆う封止材と、を備え、
前記ケースは、互いに対向するように配置された一対の第1ケース部品と、一対の前記第1ケース部品と交差し、かつ、互いに対向するように配置された一対の第2ケース部品とを備え、
一対の前記第1ケース部品と一対の前記第2ケース部品とは、互いの両端部が連結されることで前記ケースを形成し、
一対の前記第1ケース部品と一対の前記第2ケース部品との連結をなす連結面は、前記ベース板の上面に対して90°<180°の角度を満たす、半導体装置。 - 各前記第1ケース部品の両端部に、水平方向に凹む凹部が形成され、
各前記第2ケース部品の両端部に、水平方向に突出し前記凹部に嵌合する凸部が形成され、
前記凹部と前記凸部は水平方向に嵌合する、請求項1に記載の半導体装置。 - 一対の前記第1ケース部品と一対の前記第2ケース部品の底面は、前記ベース板の上面における周縁部に固定された、請求項1に記載の半導体装置。
- 前記リードフレームは、複数のDLB(Direct Lead Bonding)フレームであり、
複数の前記DLBフレームは一対の前記第1ケース部品と一対の前記第2ケース部品にそれぞれ一体に形成された、請求項1に記載の半導体装置。 - 各前記第2ケース部品は、当該第2ケース部品を前記ベース板に固定するためのネジ締め孔を有し、
前記ベース板の上面に対して90°<180°の角度を満たす前記連結面は、各前記第2ケース部品に形成された、請求項1に記載の半導体装置。 - ベース板と、
前記ベース板の下面に固定された冷却板と、
前記ベース板の上面における周縁部を除く領域に固定された絶縁基板と、
前記絶縁基板の上面に搭載された半導体素子と、
前記ベース板の上面における周縁部に固定され、前記半導体素子を囲繞するケースと、
前記ケースと一体に形成され、かつ、一端部に形成された端子を有するリードフレームと、
前記ケース内に充填され、前記半導体素子を覆う封止材と、を備え、
前記ケースは、互いに対向するように配置された一対の第1ケース部品と、一対の前記第1ケース部品と交差し、かつ、互いに対向するように配置された一対の第2ケース部品とを備え、
一対の前記第1ケース部品と一対の前記第2ケース部品とは、互いの両端部が連結されることで前記ケースを形成し、
各前記第1ケース部品の両端部に、水平方向に凹む凹部が形成され、
各前記第2ケース部品の両端部に、水平方向に突出し前記凹部に嵌合する凸部が形成され、
前記凹部と前記凸部は水平方向に嵌合し、
各前記第2ケース部品の前記凸部は、平面視にて先端側の辺の長さが基端側の辺の長さよりも長い台形形状である、半導体装置。 - 一対の前記第1ケース部品は同じ形状であり、一対の前記第2ケース部品は同じ形状である、請求項1に記載の半導体装置。
- 各前記第2ケース部品は、平面視にて各前記第2ケース部品の中心に対して非対称な形状である、請求項1に記載の半導体装置。
- 各前記第1ケース部品の前記凹部と各前記第2ケース部品の前記凸部は接着剤により固定された、請求項2に記載の半導体装置。
- 請求項1から請求項9のいずれか1項に記載の半導体装置を製造する半導体装置の製造方法であって、
(a)金型に固定するためのタイバー部を有する前記リードフレームを前記金型にセットする工程と、
(b)前記金型内に樹脂を注入し、前記第1ケース部品または前記第2ケース部品を成形するとともに、当該ケース部品に対する前記リードフレームのインサート成形を行う工程と、
(c)前記インサート成形後、前記タイバー部をカットする工程と、
を備えた、半導体装置の製造方法。
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JP2020047293A JP7313302B2 (ja) | 2020-03-18 | 2020-03-18 | 半導体装置および半導体装置の製造方法 |
US17/106,636 US11348851B2 (en) | 2020-03-18 | 2020-11-30 | Case with a plurality of pair case components for a semiconductor device |
DE102021101895.1A DE102021101895B4 (de) | 2020-03-18 | 2021-01-28 | Halbleitervorrichtung und Verfahren zu deren Herstellung |
CN202110270338.9A CN113496956B (zh) | 2020-03-18 | 2021-03-12 | 半导体装置及半导体装置的制造方法 |
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JP6451117B2 (ja) * | 2014-04-01 | 2019-01-16 | 富士電機株式会社 | 半導体装置の製造方法および半導体装置 |
JP2018031590A (ja) * | 2016-08-22 | 2018-03-01 | 三菱電機株式会社 | 半導体装置、半導体装置を含むシステム、および、半導体装置の劣化検出方法 |
JP6841199B2 (ja) * | 2017-09-29 | 2021-03-10 | 三菱電機株式会社 | 半導体装置 |
CN208538843U (zh) * | 2018-08-01 | 2019-02-22 | 铜陵市锋尚精密模具有限公司 | 一种半导体封装构造的导线架 |
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JP2005050670A (ja) | 2003-07-28 | 2005-02-24 | Toyoda Iron Works Co Ltd | ターミナル装置の製造方法 |
US20120306091A1 (en) | 2011-06-03 | 2012-12-06 | Infineon Technologies Ag | Connecting System for Electrically Connecting Electronic Devices and Method for Connecting an Electrically Conductive First Connector and Electrically Conductive Second Connector |
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