JP7280261B2 - 半導体素子および半導体装置 - Google Patents
半導体素子および半導体装置 Download PDFInfo
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- JP7280261B2 JP7280261B2 JP2020530088A JP2020530088A JP7280261B2 JP 7280261 B2 JP7280261 B2 JP 7280261B2 JP 2020530088 A JP2020530088 A JP 2020530088A JP 2020530088 A JP2020530088 A JP 2020530088A JP 7280261 B2 JP7280261 B2 JP 7280261B2
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Description
図1~図29に基づき、本開示の第1実施形態にかかる半導体素子A10と、半導体素子A10を備える半導体装置B10について説明する。
図1~図6に基づき、半導体素子A10について説明する。これらの図に示す半導体素子A10は、素子本体10、主面電極21、下地層29、裏面電極22、入力電極23、複数の試験電極24、および表面保護膜25を備える。半導体素子A10が示す例においては、素子本体10には、スイッチング回路30と、スイッチング回路30に導通する制御回路40とが構成されている。スイッチング回路30は、MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)やIGBT(Insulated Gate Bipolar Transistor)などである。半導体素子A10の説明においては、スイッチング回路30がnチャンネル型、かつ縦型構造のMOSFETである場合を対象とする。制御回路40は、スイッチング回路30を流れる電流や、スイッチング回路30の温度などを検出することにより、スイッチング回路30が正常に作動するための制御を行う。つまり、半導体素子A10は、IPD(Intelligent Power Device)の主要構成部をなしている。
図21~図29に基づき、半導体装置B10について説明する。これらの図に示す半導体装置B10は、半導体素子A10、ダイパッド51、複数の端子52、複数の第1ワイヤ61、第2ワイヤ62および封止樹脂70を備える。半導体装置B10は、モータの駆動源や、車両の電装部品などに用いられるIPDである。図21に示すように、半導体装置B10が示す例においては、当該装置の構造形式はSOP(Single Outline Package)である。なお、半導体装置B10の構造形式は、SOPに限定されない。なお、図20は、理解の便宜上、封止樹脂70を透過している。図22において透過した封止樹脂70を、想像線(二点鎖線)で示している。
図30および図31に基づき、本開示の第2実施形態にかかる半導体素子A20と、半導体素子A20を備える半導体装置B20について説明する。これらの図において、先述した半導体素子A10および半導体装置B10と同一または類似の要素には同一の符号を付して、重複する説明を省略する。ここで、図30の断面位置は、図4の断面位置と同一である。図31の断面位置は、図29の断面位置と同一である。
図30に基づき、半導体素子A20について説明する。半導体素子A20においては、主面電極21の複数の第2部212の構成が、先述した半導体素子A10の当該構成と異なる。
図31に基づき、半導体装置B20について説明する。半導体装置B20は、半導体装置B10のダイパッド51に、先述した半導体素子A10に替えて半導体素子A20を搭載したものである。
図32~図34に基づき、本開示の第3実施形態にかかる半導体素子A30と、半導体素子A30を備える半導体装置B30について説明する。これらの図において、先述した半導体素子A10および半導体装置B10と同一または類似の要素には同一の符号を付して、重複する説明を省略する。ここで、図32の断面位置は、図4の断面位置と同一である。図33の断面位置は、図29の断面位置と同一である。図34の拡大前の断面位置は、図28の断面位置と同一である。
図32に基づき、半導体素子A30について説明する。半導体素子A30においては、主面電極21の複数の第2部212の構成が、先述した半導体素子A10の当該構成と異なる。
図33および図34に基づき、半導体装置B30について説明する。半導体装置B30は、半導体装置B30のダイパッド51に、先述した半導体素子A10に替えて半導体素子A30を搭載したものである。さらに半導体装置B20においては、接合層59の構成が、先述した半導体装置B10の当該構成と異なる。
前記素子本体に導通する主面電極と、を備え、
前記主面電極は、前記主面に設けられた第1部と、前記第1部に接して設けられ、かつ前記厚さ方向に対して直交する方向において互いに離れて位置する複数の第2部と、を有し、
前記厚さ方向に沿って視て、前記複数の第2部の合計面積が、前記複数の第2部に重なる部分を含めた前記第1部の面積よりも小である、半導体素子。
前記下地層は、前記主面に接するバリア層と、前記バリア層と前記第1部との間に介在するシード層と、を有し、
前記シード層の組成は、前記第1部の組成と同一である、付記2に記載の半導体素子。
前記厚さ方向に沿って視て、前記主面電極は、前記スイッチング回路に重なっている、付記2ないし5のいずれかに記載の半導体素子。
前記入力電極は、前記主面電極から離れて位置する、付記6に記載の半導体素子。
前記第1層および前記第2層の各々の組成は、ともに金属元素を含み、
前記第2層の組成に含まれる金属元素は、前記第1層の組成に含まれる金属元素とは異なる、付記1ないし7のいずれかに記載の半導体素子。
前記第1層の組成は、銅を含み、
前記第3層の組成は、前記第1層の組成に含まれる金属元素、および前記第2層の組成に含まれる金属元素とはいずれも異なる金属元素を含む、付記8に記載の半導体素子。
前記第4層の組成は、前記第1層の組成に含まれる金属元素、前記第2層の組成に含まれる金属元素、および前記第3層の組成に含まれる金属元素とはいずれも異なる金属元素を含む、付記11ないし13のいずれかに記載の半導体素子。
前記裏面に設けられ、かつ前記素子本体に導通する裏面電極をさらに備え、
前記素子本体には、前記裏面を含み、かつ前記裏面電極に接するケイ化物層が形成され、
前記ケイ化物層の組成は、ケイ素と、ケイ素とは異なる金属元素と、を含む、付記1ないし15のいずれかに記載の半導体素子。
前記半導体素子が搭載されるダイパッドと、
前記ダイパッドと前記裏面電極との間に介在し、かつ導電性を有する接合層と、
前記ダイパッドから離れて位置する端子と、
前記複数の第2部のいずれかと前記端子とに接合されたワイヤと、を備え、
前記ワイヤの組成は、銅を含む、半導体装置。
前記ダイパッドの一部が前記封止樹脂から露出している、付記18または19に記載の半導体装置。
Claims (19)
- 厚さ方向の一方側を向く主面を有する素子本体と、
前記素子本体に導通する主面電極と、を備え、
前記主面電極は、前記主面の上に設けられた第1部と、前記第1部に接して設けられ、かつ前記厚さ方向に対して直交する方向において互いに離れた複数の第2部と、を有し、
前記厚さ方向に視て、前記複数の第2部の合計面積が、前記複数の第2部に重なる部分を含めた前記第1部の面積よりも小であり、
前記複数の第2部の各々は、前記第1部に積層された第1層と、前記第1層に積層された第2層と、を有し、
前記第1層および前記第2層の各々の組成は、ともに金属元素を含み、
前記第2層の組成に含まれる金属元素は、前記第1層の組成に含まれる金属元素とは異なる、半導体素子。 - 前記第1部の組成は、銅を含む、請求項1に記載の半導体素子。
- 前記主面と前記第1部との間に介在する下地層をさらに備え、
前記下地層は、前記主面に接するバリア層と、前記バリア層と前記第1部との間に介在するシード層と、を有し、
前記シード層の組成は、前記第1部の組成と同一である、請求項2に記載の半導体素子。 - 前記厚さ方向に視て、前記複数の第2部に重なる部分を含めた前記第1部の面積に対する、前記複数の第2部の合計面積の割合は、20%以上50%以下である、請求項2または3に記載の半導体素子。
- 前記厚さ方向に視て、前記主面の面積に対する前記主面電極の面積の割合は、50%以上90%以下である、請求項4に記載の半導体素子。
- 前記素子本体には、スイッチング回路と、前記スイッチング回路に導通する制御回路と、が構成されており、
前記厚さ方向に視て、前記主面電極は、前記スイッチング回路に重なっている、請求項2ないし5のいずれかに記載の半導体素子。 - 前記主面に設けられ、かつ前記制御回路に導通する入力電極をさらに備え、
前記入力電極は、前記主面電極から離れている、請求項6に記載の半導体素子。 - 前記第1層の組成は、ニッケルを含む、請求項1ないし7のいずれかに記載の半導体素子。
- 前記第2層の組成は、パラジウムを含む、請求項8に記載の半導体素子。
- 前記複数の第2部の各々は、前記第2層に積層された第3層を有し、
前記第1層の組成は、銅を含み、
前記第3層の組成は、前記第1層の組成に含まれる金属元素、前記第2層の組成に含まれる金属元素とはいずれも異なる金属元素を含む、請求項1ないし7のいずれかに記載の半導体素子。 - 前記第2層の組成は、ニッケルを含む、請求項10に記載の半導体素子。
- 前記第3層の組成は、パラジウムを含む、請求項11に記載の半導体素子。
- 前記複数の第2部の各々は、前記第3層に積層された第4層を有し、
前記第4層の組成は、前記第1層の組成に含まれる金属元素、前記第2層の組成に含まれる金属元素、および前記第3層の組成に含まれる金属元素とはいずれも異なる金属元素を含む、請求項10ないし12のいずれかに記載の半導体素子。 - 前記第4層の組成は、金を含む、請求項13に記載の半導体素子。
- 前記素子本体に導通する裏面電極をさらに備え、
前記素子本体は、前記厚さ方向において前記主面とは反対側を向く裏面を有し、
前記裏面電極は、前記裏面に設けられており、
前記素子本体には、前記裏面を含み、かつ前記裏面電極に接するケイ化物層が形成されており、
前記ケイ化物層の組成は、ケイ素と、ケイ素とは異なる金属元素と、を含む、請求項1ないし14のいずれかに記載の半導体素子。 - 前記ケイ化物層の組成は、ケイ素およびニッケルを含む、請求項15に記載の半導体素子。
- 請求項15または16記載の半導体素子と、
前記半導体素子が搭載されるダイパッドと、
前記ダイパッドと前記裏面電極との間に介在し、かつ導電性を有する接合層と、
前記ダイパッドから離れた端子と、
前記複数の第2部のいずれかと前記端子とに接合されたワイヤと、を備え、
前記ワイヤの組成は、銅を含む、半導体装置。 - 前記接合層は、銀の焼結体を含む、請求項17に記載の半導体装置。
- 前記半導体素子および前記ワイヤを覆う封止樹脂をさらに備え、
前記ダイパッドは、前記封止樹脂から露出している、請求項17または18に記載の半導体装置。
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US11658093B2 (en) | 2023-05-23 |
JPWO2020012958A1 (ja) | 2021-08-02 |
DE112019003550T5 (de) | 2021-03-25 |
WO2020012958A1 (ja) | 2020-01-16 |
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