JP7272426B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7272426B2 JP7272426B2 JP2021515417A JP2021515417A JP7272426B2 JP 7272426 B2 JP7272426 B2 JP 7272426B2 JP 2021515417 A JP2021515417 A JP 2021515417A JP 2021515417 A JP2021515417 A JP 2021515417A JP 7272426 B2 JP7272426 B2 JP 7272426B2
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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Description
先ず、第1の実施形態について説明する。図1は、第1の実施形態に係る半導体装置のレイアウトを示す図である。図2は、第1の実施形態に係る半導体装置に含まれる電源スイッチ回路の構成を示す回路図である。
次に、第1の実施形態の第1の変形例について説明する。第1の変形例は、NチャネルMOSトランジスタ1311N及び1321N、スイッチトランジスタ111に、フィンに代えてナノワイヤが用いられる点で第1の実施形態と相違する。図13~図15は、第1の実施形態の第1の変形例におけるスタンダードセル領域10を示す断面図である。図13は、図4及び図5中のX11-X21線に沿った断面図に相当する。図14は、図4及び図5中のY11-Y21線に沿った断面図に相当する。図15は、図4及び図5中のY16-Y26線に沿った断面図に相当する。
次に、第1の実施形態の第2の変形例について説明する。第2の変形例は、コンタクトホール522Bの配置の点で第1の実施形態と相違する。図16は、第1の実施形態の第2の変形例におけるスタンダードセル領域10の平面構成を示す模式図である。図16は、主として、電源スイッチ制御回路113のNチャネルMOSトランジスタと、スイッチトランジスタ111とのレイアウトを示す。図17は、第1の実施形態の第2の変形例におけるスタンダードセル領域10を示す断面図である。図17は、図16中のY15-Y25線に沿った断面図に相当する。
次に、第1の実施形態の第3の変形例について説明する。第3の変形例は、スイッチトランジスタ111及び112の構成の点で第1の実施形態と相違する。図18及び図19は、第1の実施形態の第3の変形例におけるスイッチトランジスタ111及び112の平面構成を示す模式図である。図18は、主として、スイッチトランジスタ111のレイアウトを示す。図19は、主として、スイッチトランジスタ112のレイアウトを示す。図18及び図19の両方に示す構造物を除き、図19に示す構造物は、図18に示す構造物の上方に位置する。
次に、第1の実施形態の第4の変形例について説明する。第4の変形例は、スイッチトランジスタ111及び112の構成の点で第1の実施形態と相違する。図20及び図21は、第1の実施形態の第4の変形例におけるスイッチトランジスタ111及び112の平面構成を示す模式図である。図20は、主として、スイッチトランジスタ111のレイアウトを示す。図21は、主として、スイッチトランジスタ112のレイアウトを示す。図20及び図21の両方に示す構造物を除き、図21に示す構造物は、図20に示す構造物の上方に位置する。
次に、第1の実施形態の第5の変形例について説明する。第5の変形例は、電源スイッチ回路110のトラック数の点で第1の実施形態と相違する。図22及び図23は、第1の実施形態の第5の変形例におけるスタンダードセル領域10の平面構成を示す模式図である。図22は、主として、電源スイッチ制御回路113のNチャネルMOSトランジスタと、スイッチトランジスタ111とのレイアウトを示す。図23は、主として、電源スイッチ制御回路113のPチャネルMOSトランジスタと、スイッチトランジスタ111とのレイアウトを示す。図22及び図23の両方に示す構造物を除き、図23に示す構造物は、図22に示す構造物の上方に位置する。
次に、第2の実施形態について説明する。第2の実施形態は、ローカル配線の配置の点で第1の実施形態と相違する。図24及び図25は、第2の実施形態におけるスタンダードセル領域10の平面構成を示す模式図である。図24は、主として、電源スイッチ制御回路113のNチャネルMOSトランジスタと、スイッチトランジスタ111とのレイアウトを示す。図25は、主として、電源スイッチ制御回路113のPチャネルMOSトランジスタと、スイッチトランジスタ111とのレイアウトを示す。図24及び図25の両方に示す構造物を除き、図25に示す構造物は、図24に示す構造物の上方に位置する。図26及び図27は、第2の実施形態におけるスタンダードセル領域10を示す断面図である。図26は、図24及び図25中のY17-Y27線に沿った断面図に相当する。図27は、図24及び図25中のY18-Y28線に沿った断面図に相当する。
次に、第3の実施形態について説明する。第3の実施形態は、セルの高さの点で第1の実施形態と相違する。図28及び図29は、第3の実施形態におけるスタンダードセル領域10の平面構成を示す模式図である。図28は、主として、電源スイッチ制御回路113のNチャネルMOSトランジスタと、スイッチトランジスタ111とのレイアウトを示す。図29は、主として、電源スイッチ制御回路113のPチャネルMOSトランジスタと、スイッチトランジスタ111とのレイアウトを示す。
次に、第3の実施形態の第1の変形例について説明する。第1の変形例は、セルの高さの点で第2の実施形態と相違する。図30及び図31は、第3の実施形態の第1の変形例におけるスタンダードセル領域10の平面構成を示す模式図である。図30は、主として、電源スイッチ制御回路113のNチャネルMOSトランジスタと、スイッチトランジスタ111とのレイアウトを示す。図31は、主として、電源スイッチ制御回路113のPチャネルMOSトランジスタと、スイッチトランジスタ111とのレイアウトを示す。
次に、第3の実施形態の第2の変形例について説明する。第2の変形例は、スイッチトランジスタ111及び112の構成の点で第1の変形例と相違する。図32及び図33は、第3の実施形態の第2の変形例におけるスタンダードセル領域10の平面構成を示す模式図である。図32は、主として、電源スイッチ制御回路113のNチャネルMOSトランジスタと、スイッチトランジスタ111とのレイアウトを示す。図33は、主として、電源スイッチ制御回路113のPチャネルMOSトランジスタと、スイッチトランジスタ111とのレイアウトを示す。
次に、第4の実施形態について説明する。第4の実施形態は、電源スイッチ回路110に含まれるバッファ及びスイッチトランジスタの数の点で第1の実施形態と相違する。図34は、第4の実施形態における電源スイッチ回路110の構成を示す回路図である。
次に、第5の実施形態について説明する。第5の実施形態は、バッファに含まれるPチャネルMOSトランジスタとNチャネルMOSトランジスタとの間の上下関係の点で第1の実施形態の第1の変形例と相違する。図39及び図40は、第5の実施形態におけるスタンダードセル領域10の平面構成を示す模式図である。図39は、主として、電源スイッチ制御回路113のPチャネルMOSトランジスタと、スイッチトランジスタ111とのレイアウトを示す。図40は、主として、電源スイッチ制御回路113のNチャネルMOSトランジスタと、スイッチトランジスタ112のレイアウトを示す。図39及び図40の両方に示す構造物を除き、図40に示す構造物は、図39に示す構造物の上方に位置する。図41は、第5の実施形態におけるスタンダードセル領域10を示す断面図である。図41は、図39及び図40中のY20-Y30線に沿った断面図に相当する。
次に、第5の実施形態の第1の変形例について説明する。第1の変形例は、電源スイッチ回路110のトラック数の点で第5の実施形態と相違する。図42及び図43は、第5の実施形態の第1の変形例におけるスタンダードセル領域10の平面構成を示す模式図である。図42は、主として、電源スイッチ制御回路113のNチャネルMOSトランジスタと、スイッチトランジスタ111とのレイアウトを示す。図43は、主として、電源スイッチ制御回路113のPチャネルMOSトランジスタと、スイッチトランジスタ111とのレイアウトを示す。図42及び図43の両方に示す構造物を除き、図43に示す構造物は、図42に示す構造物の上方に位置する。
次に、第5の実施形態の第2の変形例について説明する。第2の変形例は、電源スイッチ回路110に含まれるバッファ及びスイッチトランジスタの数の点で第5の実施形態と相違する。図44及び図45は、第5の実施形態の第2の変形例におけるスタンダードセル領域10の平面構成を示す模式図である。図44は、主として、電源スイッチ制御回路113のPチャネルMOSトランジスタと、スイッチトランジスタ111とのレイアウトを示す。図45は、主として、電源スイッチ制御回路113のNチャネルMOSトランジスタと、スイッチトランジスタ111とのレイアウトを示す。図44及び図45の両方に示す構造物を除き、図45に示す構造物は、図44に示す構造物の上方に位置する。
110:電源スイッチ回路
111、112、4111、4112:スイッチトランジスタ
113、4113:電源スイッチ制御回路
120:スタンダードセル
181、182:フィン
181C、182C、281C、282C、481C、482C:チャネル
181NA、181NB、181NC、281NB、481NA、481NB、481NC、4481NC:N型領域
182PA、182PB、281PA、281PB、281PC、282PA、282PB、481PB、482PA、482PB、4481PC:P型領域
191BA、191BB、191BC、192BA、192BB
291TA、291TB、291TC、291TD、292TA、292TB:ローカル配線
281、282、481、482、4182、4282、4481、4482:半導体領域
910、920、930、4930:電源線
940、941、4940、5941、5942、5943:制御信号線
951、952、4951、4952:信号線
1311N、1321N、4311N、4312N、4321N、4322N:NチャネルMOSトランジスタ
1311P、1321P、4311P、4312P、4321P、4322P:PチャネルMOSトランジスタ
Claims (14)
- 第1電源線と、
第2電源線と、
第1接地線と、
前記第1電源線と前記第2電源線との間に設けられたスイッチ回路と、
前記第1接地線と前記第1電源線との間に設けられたスイッチ制御回路と、
を有し、
前記スイッチ回路は、
第1導電型の第1トランジスタと、
前記第1トランジスタ上に形成され、前記第1導電型の第2トランジスタと、
を有し、
前記第1トランジスタの第1ゲート電極は、前記第2トランジスタの第2ゲート電極と接続され、
前記スイッチ制御回路は、
第2導電型の第3トランジスタと、
前記第3トランジスタ上に形成され、前記第2導電型とは異なる第3導電型の第4トランジスタと、
を有し、
前記第3トランジスタの第3ゲート電極は、前記第4トランジスタの第4ゲート電極に接続され、
前記第3トランジスタの出力及び前記第4トランジスタの出力と、前記第1ゲート電極及び前記第2ゲート電極とを電気的に接続する信号線を有することを特徴とする半導体装置。 - 前記第2電源線及び前記第1接地線が埋め込まれた基板を有し、
前記第1電源線は前記基板の上方に設けられていることを特徴とする請求項1に記載の半導体装置。 - 前記第1電源線は複数に分割されて前記第2トランジスタのソースに接続されていることを特徴とする請求項2に記載の半導体装置。
- 前記第1トランジスタのソースと前記第1電源線とを接続する第1ローカル配線と、
前記第1トランジスタのドレインと前記第2電源線とを接続する第2ローカル配線と、
前記第2トランジスタのソースと前記第1電源線とを接続する第3ローカル配線と、
前記第2トランジスタのドレインと前記第2電源線とを接続する第4ローカル配線と、
前記第3トランジスタのソースと前記第1電源線又は前記第1接地線の一方とを接続する第5ローカル配線と、
前記第3トランジスタのドレインと前記信号線とを接続する第6ローカル配線と、
前記第4トランジスタのソースと前記第1電源線又は前記第1接地線の他方とを接続する第7ローカル配線と、
前記第4トランジスタのドレインと前記信号線とを接続する第8ローカル配線と、
を有することを特徴とする請求項2又は3に記載の半導体装置。 - 前記第1ローカル配線は、前記第3ローカル配線を介して前記第1電源線に接続されていることを特徴とする請求項4に記載の半導体装置。
- 前記第1ローカル配線は、前記第1ローカル配線と前記第1電源線との間の絶縁膜中に設けられたビアを通じて前記第1電源線に接続されていることを特徴とする請求項4に記載の半導体装置。
- 平面視で前記第1トランジスタのソースと前記第2トランジスタのドレインとが重なり、
平面視で前記第1トランジスタのドレインと前記第2トランジスタのソースとが重なることを特徴とする請求項6に記載の半導体装置。 - 前記第2導電型が前記第1導電型とは異なり、
前記第3導電型が前記第1導電型と一致することを特徴とする請求項1乃至7のいずれか1項に記載の半導体装置。 - 前記第1トランジスタ、前記第2トランジスタ及び前記第4トランジスタはPチャネル型トランジスタであり、
前記第3トランジスタはNチャネル型トランジスタであることを特徴とする請求項8に記載の半導体装置。 - 前記第2導電型が前記第1導電型と一致し、
前記第3導電型が前記第1導電型とは異なることを特徴とする請求項1乃至7のいずれか1項に記載の半導体装置。 - 前記第1トランジスタ、前記第2トランジスタ及び前記第3トランジスタはPチャネル型トランジスタであり、
前記第4トランジスタはNチャネル型トランジスタであることを特徴とする請求項10に記載の半導体装置。 - 前記第2トランジスタ及び前記第4トランジスタは、チャネルにナノワイヤを有することを特徴とする請求項1乃至11のいずれか1項に記載の半導体装置。
- 前記第1トランジスタ及び前記第3トランジスタは、フィン型トランジスタであることを特徴とする請求項1乃至12のいずれか1項に記載の半導体装置。
- 前記第1トランジスタ及び前記第3トランジスタは、チャネルにナノワイヤを有することを特徴とする請求項1乃至12のいずれか1項に記載の半導体装置。
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US12046598B2 (en) | 2024-07-23 |
US20220045056A1 (en) | 2022-02-10 |
WO2020217396A1 (ja) | 2020-10-29 |
JPWO2020217396A1 (ja) | 2020-10-29 |
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