JP7241901B2 - メモリデバイス及び方法 - Google Patents
メモリデバイス及び方法 Download PDFInfo
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- JP7241901B2 JP7241901B2 JP2021549866A JP2021549866A JP7241901B2 JP 7241901 B2 JP7241901 B2 JP 7241901B2 JP 2021549866 A JP2021549866 A JP 2021549866A JP 2021549866 A JP2021549866 A JP 2021549866A JP 7241901 B2 JP7241901 B2 JP 7241901B2
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- bonding
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- memory device
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- memory array
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- 238000000034 method Methods 0.000 title claims description 67
- 239000004020 conductor Substances 0.000 claims description 16
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- 238000010586 diagram Methods 0.000 description 16
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 230000001808 coupling effect Effects 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
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- 238000002955 isolation Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
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- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
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- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
- H01L2225/06537—Electromagnetic shielding
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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- H01L2225/06503—Stacked arrangements of devices
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- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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Description
Claims (19)
- メモリデバイスであって、
メモリアレイと、
回路構造体と、
前記メモリアレイと前記回路構造体との間の接合構造体であって、前記接合構造体は、第1の接合パターン及び第2の接合パターンを備え、前記回路構造体は、前記接合構造体を介して前記メモリアレイと電気的に接続される、接合構造体と、
前記メモリアレイと前記回路構造体との間で、前記接合構造体を取り囲む遮蔽構造体であって、前記遮蔽構造体は、第3の接合パターン及び第4の接合パターンを備える、遮蔽構造体と、を備え、
前記第1の接合パターンは、前記第1の接合パターンと前記第2の接合パターンとの間の第1の界面において前記第2の接合パターンと接触し、前記第3の接合パターンは、前記第3の接合パターンと前記第4の接合パターンとの間の第2の界面において前記第4の接合パターンと接触し、
前記第3の接合パターン及び前記第4の接合パターンのそれぞれは、導電性材料を含むメモリデバイス。 - 前記第1の界面と前記第2の界面とは同一平面上にある、請求項1記載のメモリデバイス。
- 前記遮蔽構造体は、前記接合構造体から電気的に絶縁されている、請求項1に記載のメモリデバイス。
- 前記メモリアレイと前記接合構造体との間の第1の相互接続構造体であって、前記接合構造体は、前記第1の相互接続構造体を介して前記メモリアレイと電気的に接続される、第1の相互接続構造体と、
前記回路構造体と前記接合構造体との間の第2の相互接続構造体であって、前記接合構造体は、前記第2の相互接続構造体を介して前記回路構造体と電気的に接続される、第2の相互接続構造体と、をさらに備える、請求項1に記載のメモリデバイス。 - 前記第1の接合パターンは、前記第1の相互接続構造体と電気的に接続されており、
前記第2の接合パターンは、前記第2の相互接続構造体と電気的に接続されている、請求項4に記載のメモリデバイス。 - 前記第1の相互接続構造体はソース線メッシュを備え、前記接合構造体は前記ソース線メッシュと電気的に接続される、請求項4に記載のメモリデバイス。
- 前記メモリアレイと前記回路構造体との間に接続構造体をさらに備え、
前記接続構造体は、前記回路構造体と電気的に接続され、前記遮蔽構造体は、前記接続構造体をさらに取り囲む、請求項1に記載のメモリデバイス。 - コンタクトパッドと、
前記コンタクトパッドと電気的に接続されたコンタクト構造体と、をさらに備え、
前記回路構造体は、前記コンタクト構造体を介して前記コンタクトパッドと電気的に接続される、請求項1に記載のメモリデバイス。 - 前記遮蔽構造体は、前記コンタクト構造体を介して前記コンタクトパッドと電気的に接続される、請求項8に記載のメモリデバイス。
- 前記遮蔽構造体は、複数の前記第3の接合パターン及び複数の前記第4の接合パターンを備え、前記第3の接合パターン及び前記第4の接合パターンは、前記遮蔽構造体の複数のセグメントにおいて、前記接合構造体を取り囲む水平方向に配置される、請求項1に記載のメモリデバイス。
- 前記接合構造体は、複数の接合構造体を備え、
前記遮蔽構造体は、前記複数の接合構造体のそれぞれを取り囲む、請求項1に記載のメモリデバイス。 - 前記遮蔽構造体は、非フローティングになるようにバイアスされるように構成される、請求項1に記載のメモリデバイス。
- 前記遮蔽構造体は、接地にバイアスされるように構成される、請求項12に記載のメモリデバイス。
- 前記遮蔽構造体は、非ゼロ電圧にバイアスされるように構成される、請求項12に記載のメモリデバイス。
- 前記メモリアレイは、
メモリスタックと、
メモリストリングと、を備え、前記メモリストリングの各々が前記メモリスタックを貫通する、請求項1に記載のメモリデバイス。 - メモリデバイスを動作させるための方法であって、前記メモリデバイスは、メモリアレイと、回路構造体と、前記メモリアレイと前記回路構造体との間の接合構造体であって、前記回路構造体は、前記接合構造体を介して前記メモリアレイと電気的に接続される、接合構造体と、前記メモリアレイと前記回路構造体との間で、前記接合構造体を取り囲む遮蔽構造体と、を備え、前記方法は、
前記遮蔽構造体を電圧源に電気的に接続するステップと、
前記遮蔽構造体を前記電圧源によって非フローティングになるようにバイアスするステップと、を含み、
前記遮蔽構造体は、第3の接合パターン及び第4の接合パターンを備え、
前記第3の接合パターンは、前記第3の接合パターンと前記第4の接合パターンとの間の第2の界面において前記第4の接合パターンと接触し、
前記第3の接合パターン及び前記第4の接合パターンのそれぞれは、導電性材料を含む方法。 - 前記接合構造体をフローティングさせるステップをさらに含む、請求項16に記載の方法。
- 前記電圧源が、接地電圧源または電源電圧源を備える、請求項16に記載の方法。
- 前記遮蔽構造体は、水平方向に複数のセグメントを備え、前記電圧源は、複数の電圧源を備え、
電気的に接続するステップは、前記遮蔽構造体の前記複数のセグメントを前記複数の電圧源にそれぞれ電気的に接続するステップを含み、
バイアスするステップは、前記遮蔽構造体の前記複数のセグメントを、前記複数の電圧源によってそれぞれ異なる電圧にバイアスするステップを含む、請求項16に記載の方法。
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