JP7206728B2 - 半導体装置及び半導体装置の制御方法 - Google Patents
半導体装置及び半導体装置の制御方法 Download PDFInfo
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- JP7206728B2 JP7206728B2 JP2018173583A JP2018173583A JP7206728B2 JP 7206728 B2 JP7206728 B2 JP 7206728B2 JP 2018173583 A JP2018173583 A JP 2018173583A JP 2018173583 A JP2018173583 A JP 2018173583A JP 7206728 B2 JP7206728 B2 JP 7206728B2
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Description
本発明の第1の実施形態に係る半導体装置は、図1に示すように、電力回路チップ3及び制御回路チップ5を備える。電力回路チップ3は、主スイッチ回路1及び温度センサ4を備える。主スイッチ回路1は、第1半導体素子2a及び第2半導体素子2bからなる双方向スイッチである。主スイッチ回路1は、第1及び第2半導体素子2a、2bのドレイン電極(第1及び第3主電極)を共通にして互いに逆向きに接続された双方向スイッチである。第1半導体素子2aのソース電極(第2主電極)が電源(VCC)接続用の電源ノード12に接続され、第2半導体素子2bのソース電極(第4主電極)が出力(OUT)用の出力ノード13に接続される。温度センサ4は、主スイッチ回路1の通電による温度変化を検知する。
図6は、第1の実施形態に係る半導体装置の構成例を示す平面図である。図6では、半導体装置の内部を示すために、樹脂パッケージ130を透視して示している。図6に示すように、第1の実施形態に係る半導体装置は、リードフレーム(111,112,113,114,115,116)、電力回路チップ3、制御回路チップ5、及び樹脂パッケージ130を備える。電力回路チップ3は、リードフレーム(111~116)に搭載される。制御回路チップ5は、電力回路チップ3に積層される。リードフレーム(111~116)は、ダイパッド111、及びリード端子112、113、114、115、116を有する。ダイパッド111には、電力回路チップ3のドレイン電極67が電気的に接続する。リード端子112、113、114、115、116のそれぞれには、電力回路チップ3や制御回路チップ5の各電極パッドが電気的に接続する。
多段昇圧部23aでは、1段目がインバータ24と、コンデンサ25と、2つのダイオード26,27とを有し、2段目がインバータ28と、コンデンサ29と、2つのダイオード30,31とを有している。
図10は、本発明の第2の実施形態に係る半導体装置の一例を説明する回路図である。図10に示すように、駆動回路6は、駆動信号が入力される処理回路16bと、処理回路16bに共通に電気的に接続された昇圧回路17c、17dを備える。また、出力回路7は、否定論理回路(インバータ)18cに共通に電気的に接続された電荷引抜半導体素子19c、19dを備える。第2の実施形態に係る半導体装置は、処理回路16bに共通に電気的に接続された昇圧回路17c、17d、及びインバータ18cに共通に電気的に接続された電荷引抜半導体素子19c、19dを備える点が第1の実施形態と異なる。他の構成は、第1の実施形態に係る半導体装置と同様であるので、重複した説明を省略する。
図11Aは、本発明の第2の実施形態に係る半導体装置の昇圧回路の構成例1を示す回路図であり、図11Bは、図11Aに示した昇圧回路17cの出力電圧の立ち上がりを示す図である。昇圧回路17dは、図9Aに示す昇圧回路17aと同じである。図11Aに示す昇圧回路17cは、昇圧回路17dに比べ多段昇圧部23bの段数が多く3段である。このように、昇圧回路17cの多段昇圧部の段数を昇圧回路17dより多くすることで、出力電圧の立ち上がりを速くすることができる。
図13Aは、本発明の第2の実施形態に係る半導体装置の昇圧回路の構成例2を示す回路図であり、図13Bは、図13Aに示した昇圧回路の出力電圧の立ち上がりを示す図である。昇圧回路17dは、図9Aに示す昇圧回路17aと同じである。図13Aに示す昇圧回路17cは、昇圧回路17dに比べ発振回路21aの周波数が高い。このように、昇圧回路17cの発振回路21aの周波数を昇圧回路17dの発振回路21の周波数より高くすることで、図13Bに示すように図9Aに示す昇圧回路17aよりも出力電圧の立ち上がりを速くすることができる。
図14Aは、本発明の第2の実施形態に係る半導体装置の昇圧回路の構成例3を示す回路図であり、図14Bは、図14Aに示した昇圧回路の出力電圧の立ち上がりを示す図である。昇圧回路17dは、図9Aに示す昇圧回路17aと同じである。図14Aに示す昇圧回路17cは、昇圧回路17dに比べコンデンサ25aの容量が大きい。このように、昇圧回路17cのコンデンサ25aの容量を昇圧回路17dのコンデンサ25の容量より大きくすることで、図14Bに示すように図9Aに示す昇圧回路17aよりも出力電圧の立ち上がりを速くすることができる。
上記のように、本発明を実施形態及び変形例によって記載したが、この開示の一部をなす論述及び図面は本発明を限定するものであると理解すべきではない。上記の実施形態の開示の趣旨を理解すれば、当業者には様々な代替実施形態、実施例及び運用技術が本発明に含まれ得ることが明らかとなろう。又、上記の実施形態及び各変形例において説明される各構成を任意に応用した構成等、本発明はここでは記載していない様々な実施形態等を含むことは勿論である。したがって、本発明の技術的範囲は上記の例示的説明から妥当な、特許請求の範囲に係る発明特定事項によってのみ定められるものである。
2a・・・第1半導体素子
2b・・・第2半導体素子
3・・・電力回路チップ
4・・・温度センサ
5・・・制御回路チップ
6・・・駆動回路
7・・・出力回路
8・・・過熱検出回路
9・・・論理回路
10・・・低電圧検出回路
11・・・内部電源
12・・・電源ノード
13・・・出力ノード
14・・・接地ノード
15・・・入力ノード
16・・・処理回路
17a、17b、17c、17d・・・昇圧回路
18a、18b、24、28、32・・・否定論理回路(インバータ)
19a、19b・・・電荷引抜半導体素子
20・・・負荷
22・・・外部電源
50・・・ドリフト領域
51・・・共通ドレイン領域(第1及び第3主電極領域)
52・・・半導体領域
53a、53b、54a、54b・・・ウェル領域
53a・・・第1のウェル領域
53b・・・第2のウェル領域
54a・・・第3のウェル領域
54b・・・第4のウェル領域
55・・・チャネルストッパ領域
56a、56b・・・コンタクト領域
57a・・・第1のソース領域(第2主電極領域)
57b・・・第2のソース領域(第4主電極領域)
58a、58b・・・素子分離膜
59a、59b・・・トレンチ
60a、60b・・・ゲート絶縁膜
61a、61b・・・ゲート電極(制御電極)
61A、61B・・・ゲート引出電極
61C・・・フィールドプレート電極
62a、62b・・・層間絶縁膜
63a、63b、63c、63d・・・ソースコンタクト層
64a、64b、64c、64d・・・ソース電極
65a、65b・・・ソース電極パッド
66a、66b・・・ゲート電極パッド
67・・・ドレイン電極
69・・・保護膜
112、113、114、115、116・・・リード端子
121、122、123、124、125、126・・・ボンディングワイヤ
130・・・樹脂パッケージ
Claims (8)
- 主スイッチ回路を構成するように第1導電型の半導体領域からなる共通領域を有し、該共通領域の上部に第2導電型の第1及び第2のウェル領域を互いに分離して設け、前記第1のウェル領域の上部に第1導電型の第1のソース領域を設けた第1半導体素子、及び前記第2のウェル領域の上部に第1導電型の第2のソース領域を設けた第2半導体素子と、
前記第1及び第2半導体素子の制御電極のそれぞれに互いに独立した第1駆動信号及び第2駆動信号を供給する駆動回路と、
を備え、
前記駆動回路は、前記第1及び第2半導体素子の前記制御電極のそれぞれに互いに独立して電気的に接続した第1及び第2昇圧回路と、前記第1及び第2昇圧回路のそれぞれが互いに独立して電気的に接続された処理回路とを有し、
前記第1半導体素子の前記制御電極に接続された前記第1昇圧回路の出力電圧のレベルが、前記第2半導体素子の前記制御電極に接続された前記第2昇圧回路の出力電圧よりも高いことを特徴とする半導体装置。 - 前記第1及び第2半導体素子のそれぞれは、
前記第1及び第2のウェル領域の上部に設けられた第2導電型のコンタクト領域と、 を更に備え、
前記第1半導体素子の前記コンタクト領域が、電源端子に電気的に接続され、前記第2半導体素子の前記コンタクト領域が、出力端子に電気的に接続されることを特徴とする請求項1に記載の半導体装置。 - 前記半導体領域は、
第1半導体領域と、
前記第1半導体領域と接し、前記第1及び第2のウェル領域と距離を有し、前記第1半導体領域よりも不純物濃度が高い第2半導体領域と、を有することを特徴とする請求項1に記載の半導体装置。 - 前記第1半導体領域は、前記第1及び第2のウェル領域を備える第1半導体層であり、
前記第2半導体領域は、前記第1半導体層の下に形成された第2半導体層であることを特徴とする請求項3に記載の半導体装置。 - 入力のそれぞれが前記第1及び第2昇圧回路のそれぞれの入力側に電気的に接続された否定論理回路、制御電極のそれぞれが前記否定論理回路のそれぞれの出力に電気的に接続され、前記第1及び第2昇圧回路それぞれと前記出力端子とに、第1主電極領域及び他方の電極領域がそれぞれ電気的に接続された電荷引抜半導体素子を有する出力回路を更に備えることを特徴とする請求項2に記載の半導体装置。
- 前記第1半導体素子の前記制御電極に接続された前記第1昇圧回路の出力電圧の立ち上がりが、前記第2半導体素子の前記制御電極に接続された前記第2昇圧回路の出力電圧の立ち上がりよりも早いことを特徴とする請求項1~5のいずれか1項に記載の半導体装置。
- 前記第1及び第2半導体素子を同一チップ上に集積化した電力回路チップ、前記駆動回路を同一チップ上に集積化した制御回路チップ、前記電力回路チップ及び前記制御回路チップを内蔵し、前記共通領域を電気的に外部に引き出し、外部電源に接続可能な電源端子、前記第2のソース領域を電気的に外部に引き出し、外部の負荷に接続可能な出力端子を有するパッケージを備えることを特徴とする請求項1に記載の半導体装置。
- 共通領域となる第1導電型の半導体領域を有し、前記共通領域の上部に第2導電型の第1及び第2のウェル領域を互いに分離して設け、前記第1のウェル領域の上部に設けた第1導電型の第2主電極領域の上面に、電源端子に電気的に接続された第1表面電極を設けた絶縁ゲート型の第1半導体素子、及び前記第2のウェル領域の上部に設けた第4主電極領域の上面に、出力端子に電気的に接続された第2表面電極を設けた絶縁ゲート型の第2半導体素子を有する主スイッチ回路を有し、
前記第1半導体素子の制御電極に第1駆動信号を印加し、前記第1半導体素子の導通及び遮断を制御し、
前記第2半導体素子の制御電極に、前記第1駆動信号とは独立して第2駆動信号を印加し、前記第2半導体素子の導通及び遮断を制御する
ことを含み、
前記第1半導体素子が導通状態の間に、前記第2駆動信号の導通及び遮断の切替を行い、
前記第1及び第2駆動信号のそれぞれが、互いに独立した昇圧回路を介して前記第1及び第2半導体素子のそれぞれの前記制御電極に印加され、
前記第1半導体素子を導通状態にする前記第1駆動信号の電圧レベルが、前記第2半導体素子を導通状態にする前記第2駆動信号の電圧レベルより高いことを特徴とする半導体装置の制御方法。
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