JP7193474B2 - Euvリソグラフィを用いたパワーグリッドのアーキテクチャ及び最適化 - Google Patents
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
- H01L2027/11868—Macro-architecture
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Description
半導体製造プロセスが進歩し、オンダイ幾何学的寸法が減少するにつれて、半導体チップは、より少ないスペースでより多くの機能及び性能を提供する。多くの進歩がなされてきたが、潜在的な利益を制限する処理及び集積回路設計における現代の技術では、設計上の問題が依然として発生する。例えば、容量結合、エレクトロマイグレーション、リーク電流及びプロセス歩留まりは、デバイスの配置及び半導体チップのダイ全体に亘る信号のルーティングに影響を与える問題の一部である。したがって、これらの問題は、設計の完了を遅らせ、市販されるまでの時間に影響を及ぼす可能性がある。
Claims (20)
- 集積回路であって、
各々が前記集積回路内のデバイスへの電源接続を提供する、第1金属層内の第1の複数の独立した電源ポストと、
各々が標準セルの高さ未満の長さを有する、前記第1金属層とは異なる第2金属層内の第2の複数の独立した電源ポストと、
前記第1金属層及び前記第2金属層の各々と異なる第3金属層内の複数の独立した電源ストラップであって、前記複数の独立した電源ストラップの各々が、前記第1の複数の独立した電源ポストのうち1つの電源ポストを、前記第2の複数の独立した電源ポストのうち1つの電源ポストに接続する、複数の独立した電源ストラップと、を備え、
前記複数の独立した電源ストラップのうち2つ以上は、前記標準セルの境界エッジまでルーティングされていない少なくとも1つの端部を有する、
集積回路。 - 前記複数の独立した電源ストラップのうち1つ以上は、前記第2の複数の独立した電源ポストのうち2対の電源ポスト間のピッチ距離の幅の半分未満の長さでルーティングされている、
請求項1の集積回路。 - 前記第2の複数の独立した電源ポストの各々の長さは、前記複数の独立した電源ストラップのピッチに基づく最短の長さである、
請求項1の集積回路。 - 前記第2の複数の独立した電源ポスト及び前記複数の独立した電源ストラップの各々は、単方向信号ルートである、
請求項1の集積回路。 - 前記第1金属層は垂直金属1層であり、前記第2金属層は水平金属2層であり、前記第3金属層は垂直金属3層である、
請求項1の集積回路。 - 電源ポスト又は電源ストラップを含む所定の金属層の各トラックに存在するギャップは、前記ギャップにおいて前記所定の金属層の非電源信号ルートを提供する、
請求項1の集積回路。 - 同じ垂直金属3層トラックを共有する前記第2の複数の独立した電源ポストのうち少なくとも2つの電源ポストは、前記垂直金属3層トラック内のこれらの間の金属3層内に非電源信号ルートを有する、
請求項5の集積回路。 - トランジスタの金属ゲートに対して垂直にルーティングされ、ソース又はドレイン接続に使用されるトレンチシリサイドコンタクトと、前記第1の複数の複数の独立した電源ポストのうち1つの電源ポストと、のビアのみに接続される、前記金属1層の下方の金属0層内の複数の独立した電源ストラップのうち1つ以上の電源ストラップをさらに備える、
請求項5の集積回路。 - 前記デバイスへの電源接続は、電源接続及び接地基準接続のうちの1つである、
請求項1の集積回路。 - コンピューティングデバイスによって実行される方法であって、
各々が集積回路内のデバイスへの電源接続を提供する第1の複数の独立した電源ポストを、第1金属層に配置することと、
各々が前記標準セルの高さ未満の長さを有する第2の複数の独立した電源ポストを、前記第1金属層とは異なる第2金属層に配置することと、
前記第1金属層及び前記第2金属層の各々と異なる第3金属層に複数の独立した電源ストラップを配置することであって、前記複数の独立した電源ストラップの各々が、前記第1の複数の独立した電源ポストのうち1つの電源ポストを前記第2の複数の独立した電源ポストのうち1つ電源ポストに接続する、ことと、を含み、
前記複数の独立した電源ストラップのうち2つ以上は、前記標準セルの境界エッジまでルーティングされていない少なくとも1つの端部を有する、
方法。 - 前記複数の独立した電源ストラップのうち1つ以上は、前記第1の複数の独立した電源ポストのうち1つの電源ポストと、前記第2の複数の独立した電源ポストのうち1つの電源ポストとの間よりも、2対の電源ポスト間のピッチ距離の幅の半分未満の長さでルーティングされている、
請求項10の方法。 - 前記第2の複数の独立した電源ポストの各々を、前記複数の独立した電源ストラップのピッチに基づく最短の長さでルーティングすることをさらに含む、
請求項10の方法。 - 前記第2の複数の独立した電源ポスト及び前記複数の独立した電源ストラップの各々は、単方向信号ルートである、
請求項10の方法。 - 前記第1金属層は垂直金属1層であり、前記第2金属層は水平金属2層であり、前記第3金属層は垂直金属3層である、
請求項10の方法。 - 実行されると標準セルの集積回路レイアウトを生成する複数の命令を記憶するコンピュータ可読記憶媒体であって、
前記集積回路レイアウトは、
各々が標準セル内のデバイスへの電源接続を提供する、第1金属層内の第1の複数の独立した電源ポストと、
各々が前記標準セルの高さ未満の長さを有する、前記第1金属層とは異なる第2金属層内の第2の複数の独立した電源ポストと、
前記第1金属層及び前記第2金属層の各々と異なる第3金属層内の複数の独立した電源ストラップであって、前記複数の独立した電源ストラップの各々が、前記第1の複数の独立した電源ポストのうち1つの電源ポストを、前記第2の複数の独立した電源ポストのうち1つの電源ポストに接続する、複数の独立した電源ストラップと、を備え、
前記複数の独立した電源ストラップのうち2つ以上は、前記標準セルの境界エッジまでルーティングされていない少なくとも1つの端部を有する、
コンピュータ可読記憶媒体。 - 前記複数の独立した電源ストラップのうち1つ以上は、前記第1の複数の独立した電源ポストのうち1つの電源ポストと、前記第2の複数の独立した電源ポストのうち1つの電源ポストとの間よりも、2対の電源ポスト間のピッチ距離の幅の半分未満の長さでルーティングされている、
請求項15のコンピュータ可読記憶媒体。 - 前記第2の複数の独立した電源ポストの各々の長さは、前記複数の独立した電源ストラップのピッチに基づく最短の長さである、
請求項15のコンピュータ可読記憶媒体。 - 前記第2の複数の独立した電源ポスト及び前記複数の独立した電源ストラップの各々は、単方向信号ルートである、
請求項15のコンピュータ可読記憶媒体。 - 前記第1金属層は垂直金属1層であり、前記第2金属層は水平金属2層であり、前記第3金属層は垂直金属3層である、
請求項15のコンピュータ可読記憶媒体。 - 前記複数の独立した電源ストラップのうち1つ以上は、前記第1の複数の独立した電源ポストのうち1つの電源ポストと、前記第2の複数の独立した電源ポストのうち1つの電源ポストとの間よりも、2対の電源ポスト間のピッチ距離の幅の半分未満の長さでルーティングされている、
請求項19のコンピュータ可読記憶媒体。
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US15/636,278 US11347925B2 (en) | 2017-05-01 | 2017-06-28 | Power grid architecture and optimization with EUV lithography |
US15/636,278 | 2017-06-28 | ||
PCT/US2018/029760 WO2018204179A1 (en) | 2017-05-01 | 2018-04-27 | Power grid architecture and optimization with euv lithography |
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US11663389B2 (en) * | 2021-04-16 | 2023-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Circuit layout |
US11929325B2 (en) * | 2021-08-18 | 2024-03-12 | Qualcomm Incorporated | Mixed pitch track pattern |
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US20180314785A1 (en) | 2018-11-01 |
EP3619630A1 (en) | 2020-03-11 |
JP2020518916A (ja) | 2020-06-25 |
KR20200003004A (ko) | 2020-01-08 |
KR102531028B1 (ko) | 2023-05-10 |
US11347925B2 (en) | 2022-05-31 |
WO2018204179A1 (en) | 2018-11-08 |
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