JP7189846B2 - 半導体装置の製造方法および金属の積層方法 - Google Patents

半導体装置の製造方法および金属の積層方法 Download PDF

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JP7189846B2
JP7189846B2 JP2019131287A JP2019131287A JP7189846B2 JP 7189846 B2 JP7189846 B2 JP 7189846B2 JP 2019131287 A JP2019131287 A JP 2019131287A JP 2019131287 A JP2019131287 A JP 2019131287A JP 7189846 B2 JP7189846 B2 JP 7189846B2
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layer
metal layer
metal
electrode
semiconductor device
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JP2021015943A (ja
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健悟 古谷
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Priority to US16/803,524 priority patent/US11183425B2/en
Priority to CN202010127923.9A priority patent/CN112242306A/zh
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Description

実施形態は、半導体装置の製造方法および金属の積層方法に関する。
半導体装置の製造過程において、ボンディングパッド等の厚い金属層を形成する際には、無電解メッキ法が用いられる。例えば、薄層のパラジウム層上に、無電解メッキを用いて金層を形成する場合がある。しかしながら、パラジウム層を厚くすると、金層の析出速度が遅くなる。このため、所定の厚さの金層を得るためには、無電解メッキの時間が長くなり、製造効率を低下させる。
特開２０１３－４７８１号公報
実施形態は、無電解メッキを用いた金層の形成時間を短縮できる半導体装置の製造方法および金属の積層方法を提供する。
実施形態に係る半導体装置は、半導体部と、前記半導体部上に選択的に設けられ、前記半導体部に電気的に接続された電極と、前記電極上に設けられた多層の金属層と、を備える。前記半導体装置の製造方法は、前記電極上に第１金属層を選択的に形成し、前記第１金属層上にパラジウム層を形成し、前記パラジウム層上に第２金属層を形成し、前記第２金属層を金層に置き換え、前記パラジウム層に接した金層を形成する。
実施形態に係る半導体装置を示す模式断面図である。 実施形態に係る半導体装置の電極構造を示す模式断面図である。 実施形態に係る半導体装置の製造過程を示す模式断面図である。 比較例に係る半導体装置の製造過程を示す模式断面図である。 実施形態に係る半導体装置の構造を示す模式断面図である。
以下、実施の形態について図面を参照しながら説明する。図面中の同一部分には、同一番号を付してその詳しい説明は適宜省略し、異なる部分について説明する。なお、図面は模式的または概念的なものであり、各部分の厚みと幅との関係、部分間の大きさの比率などは、必ずしも現実のものと同一とは限らない。また、同じ部分を表す場合であっても、図面により互いの寸法や比率が異なって表される場合もある。
さらに、各図中に示すＸ軸、Ｙ軸およびＺ軸を用いて各部分の配置および構成を説明する。Ｘ軸、Ｙ軸、Ｚ軸は、相互に直交し、それぞれＸ方向、Ｙ方向、Ｚ方向を表す。また、Ｚ方向を上方、その反対方向を下方として説明する場合がある。
図１は、実施形態に係る半導体装置１を示す模式断面図である。図１に示す例では、半導体装置１は、実装基板１０の上にマウントされている。
図１に示すように、実装基板１０は、マウントパッド１１と、配線１３と、を含む。マウントパッド１１は、実装基板１０の表面上に設けられる。半導体装置１は、マウントパッド１１の上に接続部材１５を介してマウントされる。また、半導体装置１は、例えば、接続導体２０を介して配線１３に電気的に接続される。
半導体装置１は、半導体部３０と、電極３１と、電極３３と、絶縁層３４と、金属層３５と、金属層３７と、金属層３８と、を含む。半導体装置１は、例えば、ＩＧＢＴ（Insulated Gate Bipolar Transisitor）である。電極３１は、例えば、コレクタ電極であり、電極３３は、例えば、エミッタ電極である。半導体部３０は、例えば、シリコンである。
電極３１は、半導体部３０の裏面上に設けられる。電極３１は、接続部材１５を介してマウントパッド１１に接続される。マウントパッド１１は、例えば、銅もしくは銅合金を含む金属板である。接続部材１５は、例えば、ハンダ材である。
電極３３は、半導体部３０の表面上に設けられる。絶縁層３４は、電極３３の外縁を覆うように設けられる。絶縁層３４は、例えば、ポリイミド等の絶縁性樹脂である。電極３３は、絶縁層３４に囲まれた領域に露出した表面を有する。金属層３５は、電極３３の表面上に選択的に設けられる。金属層３７は、絶縁層３４に囲まれた領域において、金属層３５を覆うように設けられる。金属層３８は、絶縁層３４に囲まれた領域において、金属層３７を覆うように設けられる。
接続導体２０は、接続部材２３を介して金属層３８の上にボンディングされる。接続導体２０は、例えば、銅もしくは銅合金を含む板状のコネクタである。接続部材２３は、例えば、ハンダ材である。さらに、接続導体２０は、接続部材２５を介して配線１３上にボンディングされる。接続部材２５は、例えば、ハンダ材である。
半導体装置１は、上記の例に限定される訳ではない。例えば、半導体装置１は、ＭＯＳＦＥＴやダイオードであっても良い。また、半導体装置１の実装には、実装基板１０に代えて、リードフレームなどを用いても良い。
図２は、実施形態に係る半導体装置１の電極構造を示す模式断面図である。図２は、図１中の破線で囲まれた領域を表している。
半導体装置１は、例えば、電極３３の上に積層された金属層３５、金属層３７および金属層３８を含む。電極３３は、例えば、アルミニウム電極である。また、電極３３は、銅を含む金属層であっても良い。金属層３５は、例えば、ニッケル層である。金属層３７は、例えば、パラジウム層である。金属層３８は、例えば、金（Ａｕ）層である。
金属層３７は、例えば、バリア層として機能し、金属層３５に含まれるニッケルの金属層３８への拡散を防ぐ。これにより、金属層３８の変質を防ぐことができる。すなわち、金属層３７を設けない場合には、金属層３５のニッケルが金属層３８へ拡散し、金属層３８は、例えば、ニッケルを含む金層となる。例えば、金属層３８と接続部材２３との間の接続強度（図１参照）は、ニッケルを含まない金属層３８に比べて低下する場合がある。
図３（ａ）～（ｃ）は、実施形態に係る半導体装置１の製造過程を示す模式断面図である。図３（ａ）～（ｃ）は、金属層３５、３７および３８を電極３３の上に形成する過程を示す模式図である。
図３（ａ）に示すように、下地層である電極３３の上に、金属層３５、３７および３９を順に形成する。電極３３は、その表面に、例えば、アルミニウムもしくはアルミニウム合金を含む。
金属層３５は、例えば、ニッケルを主成分として含む。金属層３５は、例えば、無電解メッキ法を用いて形成される。金属層３５は、この例に限定されず、例えば、電極３３に対する所定の密着強度を得られる金属層であれば良い。
金属層３７は、例えば、パラジウム（Ｐｄ）を主成分として含む。金属層３７は、バリア層としての効果を有効に発揮させるために、例えば、０．３マイクロメートルよりも厚い層厚を有するように形成される。金属層３７は、例えば、無電解メッキ法を用いて、金属層３５を覆うように形成される。
金属層３９は、例えば、ニッケルを主成分として含む。金属層３９は、例えば、無電解メッキ法を用いて、金属層３７を覆うように形成される。金属層３９は、例えば、数１０ナノメートルの層厚を有する。
図３（ｂ）に示す過程では、電極３３の上に積層された金属層３５、３７および３９を、無電解メッキ用の金メッキ液に浸漬させる。これにより、金属層３９中のニッケル原子が、金メッキ液中の金原子に置き換えられ、ニッケル原子は、金メッキ液中に溶出される。これに伴い、金属層３９の上に金原子が析出される。この反応は、例えば、金属層３９に含まれるニッケル原子の全てが、金原子に置き換えられるまで続く。
図３（ｃ）に示すように、金属層３９は、金属層３８に置換される。金属層３８は、金を主成分として含む。結果として、金属層３８は、金属層３７の上に直接形成される。すなわち、金属層３７と金属層３８との間に、金属層３９は介在しない。これにより、金属層３８を形成した後の熱処理において、金属層３８中にニッケルが拡散することはなく、例えば、接続部材２３と金属層３８との間の密着強度の低下を回避することができる（図１参照）。また、金属層３７の表面全体が金層に覆われると、金層上に直接金が析出されるようになる。例えば、金属層３５、３７、３９の積層方向（Ｚ方向）における金属層３９の層厚よりも厚い金属層３８を形成することもできる。
なお、金属層３９は、ニッケルを主成分とする金属層に限定される訳ではない。例えば、無電解メッキの条件下において、パラジウム層上に析出可能であり、且つ、金原子と置換可能な元素を主成分とする金属層であれば良い。また、金属層３９に含まれる元素が、金属層３８を変質させないものであれば、金属層３７と金属層３８との間に金属層３９を残しても良い。
図４（ａ）および（ｂ）は、比較例に係る半導体装置１の製造過程を示す模式断面図である。図４（ａ）は、ニッケル層上に形成されたパラジウム層の上に金原子を析出させる過程を示す模式図である。図４（ｂ）は、比較例に係る半導体装置１の電極構造を示す模式断面図である。
例えば、無電解メッキ法において、パラジウムと反応した金原子を析出させることは難しい。すなわち、パラジウム原子がメッキ液中に溶出されることはなく、メッキ液とパラジウムとの反応により金原子を析出させることはできない。しかしながら、パラジウム層の層厚が薄く、例えば、０．１マイクロメートル程度であれば、パラジウム層上に金原子を析出させることが可能になる。
図４（ａ）に示すように、パラジウム層には、原子レベルのピンホールが存在する。金メッキ液は、そのピンホールを介してニッケル層に到達し、ニッケル原子を溶出させる。これにより、パラジウム層上に金原子が析出される。
これに対し、パラジウム層の層厚を０．３マイクロメートルよりも厚くすると、パラジウム層中のピンホールの密度が劇的に減少する。このため、ピンホールを介した金原子の析出速度が遅くなり、金メッキ層の形成に長時間を要するようになる。
また、図４（ｂ）に示すように、金属層３５および金属層３７をメッキ液に浸漬させた場合、例えば、絶縁層３４と金属層３７との間の隙間からメッキ液が侵入し、金属層３５のニッケルを置換する場合がある。このため、メッキ時間が長くなると、金属層３５からのニッケル原子の溶出により、意図しない空洞ＶＳが形成される場合がある。このような空洞ＶＳが形成されると、電極３３と金属層３５との間の密着強度が低下する。また、空洞ＶＳを介した不純物等の侵入により、半導体装置１の信頼性を低下させる可能性もある。
これに対し、実施形態に係る半導体装置１の製造方法では、金属層３９を介在させることにより、金属層３８を形成するためのメッキ時間を短縮することが可能となる。これにより、半導体装置１の製造効率を向上させることができる。さらに、絶縁層３４と金属層３７との間の隙間を介したメッキ液の侵入を抑制し、空洞ＶＳが形成されることを回避できる。これにより、半導体装置１の信頼性を向上させることができる。
図５（ａ）および（ｂ）は、実施形態に係る半導体装置２、３の構造を示す模式断面図である。図５（ａ）は、トレンチゲート構造を有するＩＧＢＴの断面構造を示す模式図である。図５（ｂ）は、ダイオードの断面構造を示す模式図である。
図５（ａ）に示す半導体装置２は、ゲート電極４０をさらに含む。ゲート電極４０は、半導体部３０の表面側に設けられたゲートトレンチＧＴの内部に位置する。ゲート電極４０は、ゲートトレンチＧＴの内面を覆うゲート絶縁膜４３により、半導体部３０から電気的に絶縁される。また、ゲート電極４０は、層間絶縁膜４５により電極３３から電気的に絶縁される。
半導体部３０は、例えば、ｎ形ベース層３０ａと、ｐ形ベース層３０ｂと、ｎ形エミッタ層３０ｃと、ｐ形コンタクト層３０ｄと、ｐ形コレクタ層３０ｅと、を含む。
ｐ形ベース層３０ｂは、ｎ形ベース層３０ａと電極３３との間に位置し、相互に隣接するゲート電極４０の間に設けられる。
ｎ形エミッタ層３０ｃおよびｐ形コンタクト層３０ｄは、それぞれｐ形ベース層３０ｂと電極３３との間に選択的に設けられる。電極３３は、ｎ形エミッタ層３０ｃおよびｐ形コンタクト層３０ｄに接し、電気的に接続される。
ｎ形エミッタ層３０ｃは、ｎ形ベース層３０ａのｎ形不純物よりも高濃度のｎ形不純物を含む。ｐ形コンタクト層３０ｄは、ｐ形ベース層３０ｂのｐ形不純物よりも高濃度のｐ形不純物を含む。電極３３は、ｐ形コンタクト層３０ｄを介してｐ形ベース層３０ｂに電気的に接続される。
ｐ形コレクタ層３０ｅは、ｎ形ベース層３０ａと電極３１との間に位置する。電極３１は、ｐ形コレクタ層３０ｅに接し、電気的に接続される。
図５（ｂ）に示す半導体装置３では、半導体部３０は、Ｉ層３０ｆと、アノード層３０ｇと、カソード層３０ｈと、を含む。Ｉ層３０ｆは、例えば、低濃度のｎ形不純物を含むｎ形半導体層である。
アノード層３０ｇは、Ｉ層３０ｆと電極３３との間に位置し、半導体部３０の表面側に選択的に設けられる。アノード層３０ｇは、例えば、ｐ形不純物を含むｐ形半導体層である。電極３３は、アノード層３０ｇに接し、電気的に接続される。
カソード層３０ｈは、Ｉ層３０ｆと電極３１との間に位置する。カソード層３０ｈは、Ｉ層３０ｆのｎ形不純物よりも高濃度のｎ形不純物を含む。電極３１は、カソード層３０ｈに電気的に接続される。
半導体装置３は、絶縁層３６をさらに含む。絶縁層３６は、半導体部３０と絶縁層３４との間に位置する。絶縁層３６には、例えば、シリコン酸化膜が用いられ、所謂パッシベーション膜として機能する。
本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
１、２、３…半導体装置、 １０…実装基板、 １１…マウントパッド、 １３…配線、 １５、２３、２５…接続部材、 ２０…接続導体、 ３０…半導体部、 ３０ａ…ｎ形ベース層、 ３０ｂ…ｐ形ベース層、 ３０ｃ…ｎ形エミッタ層、 ３０ｄ…ｐ形コンタクト層、 ３０ｅ…ｐ形コレクタ層、 ３０ｆ…Ｉ層、 ３０ｇ…アノード層、 ３０ｈ…カソード層、 ３１、３３…電極、 ３４、３６…絶縁層、 ３５、３７、３８、３９…金属層、 ４０…ゲート電極、 ４３…ゲート絶縁膜、 ４５…層間絶縁膜、 ＧＴ…ゲートトレンチ、 ＶＳ…空洞

Claims (7)

  1. 半導体部と、
    前記半導体部上に選択的に設けられ、前記半導体部に電気的に接続された電極と、前記電極上に設けられた多層の金属層と、を備える半導体装置の製造方法であって、
    前記電極上に第１金属層を選択的に形成し、
    前記第１金属層を覆うパラジウム層を形成し、
    前記パラジウム層を覆う第２金属層を形成し、
    前記第２金属層を金層に置き換え、前記パラジウム層に接した金層を形成する半導体装置の製造方法。
  2. 前記第１金属層および前記第２金属層は、ニッケルを含む請求項１記載の製造方法。
  3. 前記金層は、無電解メッキを用いて形成される請求項１または２に記載の製造方法。
  4. 前記第１金属層、前記パラジウム層および前記第２金属層は、無電解メッキを用いて形成される請求項３記載の製造方法。
  5. 下地層上にニッケルを含む金属層を形成し、
    前記金属層を覆うようにパラジウムを含む中間層を形成し、
    前記中間層を覆うようにニッケルを含む置換層を形成し、
    前記置換層のニッケルを、無電解メッキにより金に置換し、前記中間層に接した金層を形成する金属の積層方法。
  6. 前記金属層、前記中間層および前記置換層は、無電解メッキを用いて形成される請求項５記載の方法。
  7. 前記金属層、前記中間層および前記置換層の積層方向における前記金層の層厚は、前記金層に置換される前の前記置換層の前記積層方向における層厚よりも厚く形成される請求項５または６に記載の方法。
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