JP7142604B2 - 配線基板およびその製造方法 - Google Patents
配線基板およびその製造方法 Download PDFInfo
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- JP7142604B2 JP7142604B2 JP2019091823A JP2019091823A JP7142604B2 JP 7142604 B2 JP7142604 B2 JP 7142604B2 JP 2019091823 A JP2019091823 A JP 2019091823A JP 2019091823 A JP2019091823 A JP 2019091823A JP 7142604 B2 JP7142604 B2 JP 7142604B2
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/111—Manufacture and pre-treatment of the bump connector preform
- H01L2224/1111—Shaping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/14104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09045—Locally raised area or protrusion of insulating substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09409—Multiple rows of pads, lands, terminals or dummy patterns; Multiple rows of mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/098—Special shape of the cross-section of conductors, e.g. very thick plated conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09909—Special local insulating pattern, e.g. as dam around component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1126—Firing, i.e. heating a powder or paste above the melting temperature of at least one of its constituents
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
本実施形態では、配線基板1を例に挙げて説明する。配線基板1は、複数の接続パッド12を有しており、各種電子機器などの配線基板として利用される。
図1には、配線基板1の構成を示す。図1の上方には配線基板1の平面構成を示す。図1の下方には、上方の平面図におけるA-A線部分の断面構成を示す。
図3には、第1の実施形態のさらなる変形例にかかる配線基板1aの構成を示す。図1に示す配線基板1では、斜め方向に隣接する各接続パッド12間の領域の全てにアルミナ突起部13が形成されている。しかし、本発明はこのような構成に限定されない。
以上のように、本実施形態にかかる配線基板1では、接続パッド12の形成領域外の領域に複数のアルミナ突起部13が形成されている。このアルミナ突起部13の高さは、接続パッド12の高さよりも高くなっている。
本実施形態では、配線基板201を例に挙げて説明する。
図4には、配線基板201の構成を示す。図4の上方には配線基板201の平面構成を示す。図4の下方には、上方の平面図におけるC-C線部分の断面構成を示す。
続いて、配線基板201の製造方法について、図5(a)から(c)を参照しながら説明する。図5(a)から(c)では、上方に各製造過程における配線基板201の平面構成を示し、下方に各製造過程における配線基板201の断面構成を示す。
本実施形態では、アルミナ突起部313の形状を種々に異ならせた配線基板301について説明する。図6、図7、および図8(a)から(d)には、本実施形態にかかる配線基板301の一部分の平面構成を示す。
11 :絶縁基板
12 :接続パッド(接続用端子)
13 :アルミナ突起部(非導電性の突部)
101 :配線基板
113 :アルミナ突起部(非導電性の突部)
201 :配線基板
213 :アルミナ突起部(非導電性の突部)
213a:非導電性材料
214 :柱状部
301 :配線基板
313a:アルミナ突起部(非導電性の突部)
Claims (3)
- 絶縁基板と、
前記絶縁基板上に配列されている複数の接続用端子と、
前記接続用端子の形成領域外の領域に設けられている複数の非導電性の突部と
を備え、
前記非導電性の突部の高さは、前記接続用端子の高さよりも高くなっており、
前記非導電性の突部の下方には、前記絶縁基板の熱収縮率よりも熱収縮率の小さい材料で形成されている柱状部が設けられている、配線基板。 - 前記絶縁基板は、主成分としてセラミック材料を含み、
前記柱状部は、主成分として金属材料を含んでいる、
請求項1に記載の配線基板。 - 基板内に複数の柱状部が配置されている絶縁基板を用いて配線基板を製造する方法であって、
前記柱状部は、前記絶縁基板の熱収縮率よりも熱収縮率の小さい材料で形成されており、
前記絶縁基板上における前記柱状部の配置領域以外の領域に接続用端子を形成する工程と、
前記絶縁基板における前記柱状部の上方に非導電性材料を堆積させる工程と、
前記非導電性材料が堆積された前記絶縁基板を焼成または加熱し、前記絶縁基板と前記柱状部との熱収縮率の差によって前記絶縁基板の表面から前記柱状部を突出させることによって、前記非導電性材料を含む突部を形成する工程と、を含み、
前記突部は前記接続用端子より高くなるように形成される、配線基板の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019091823A JP7142604B2 (ja) | 2019-05-15 | 2019-05-15 | 配線基板およびその製造方法 |
US16/808,597 US10849224B1 (en) | 2019-05-15 | 2020-03-04 | Wiring board and manufacturing method thereof |
EP20166816.7A EP3740048A1 (en) | 2019-05-15 | 2020-03-30 | Wiring board and manufacturing method thereof |
CN202010305466.8A CN111952269A (zh) | 2019-05-15 | 2020-04-17 | 配线基板及其制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019091823A JP7142604B2 (ja) | 2019-05-15 | 2019-05-15 | 配線基板およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2020188134A JP2020188134A (ja) | 2020-11-19 |
JP7142604B2 true JP7142604B2 (ja) | 2022-09-27 |
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JP2019091823A Active JP7142604B2 (ja) | 2019-05-15 | 2019-05-15 | 配線基板およびその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10849224B1 (ja) |
EP (1) | EP3740048A1 (ja) |
JP (1) | JP7142604B2 (ja) |
CN (1) | CN111952269A (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20200315030A1 (en) * | 2019-03-27 | 2020-10-01 | Delphi Technologies Ip Limited | Conformal coating blockage by surface-mount technology solder features |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007324418A (ja) | 2006-06-01 | 2007-12-13 | Fujitsu Ltd | 半導体装置、はんだバンプ接続用基板の製造方法及び半導体装置の製造方法 |
JP2011142185A (ja) | 2010-01-06 | 2011-07-21 | Renesas Electronics Corp | 半導体装置 |
JP2014207347A (ja) | 2013-04-15 | 2014-10-30 | 株式会社村田製作所 | セラミック多層配線基板およびこれを備えるモジュール |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3152834B2 (ja) * | 1993-06-24 | 2001-04-03 | 株式会社東芝 | 電子回路装置 |
JPH11111766A (ja) * | 1997-09-30 | 1999-04-23 | Kyocera Corp | 配線基板およびその製造方法 |
US5969461A (en) * | 1998-04-08 | 1999-10-19 | Cts Corporation | Surface acoustic wave device package and method |
JPH11298142A (ja) * | 1998-04-09 | 1999-10-29 | Nec Corp | 多層セラミック基板の実装構造と実装方法 |
JP2008210993A (ja) * | 2007-02-26 | 2008-09-11 | Nec Corp | プリント配線板及びその製造方法 |
JP2013149948A (ja) * | 2011-12-20 | 2013-08-01 | Ngk Spark Plug Co Ltd | 配線基板及びその製造方法 |
JP5592459B2 (ja) * | 2012-11-07 | 2014-09-17 | 日本特殊陶業株式会社 | 配線基板の製造方法 |
US9497861B2 (en) * | 2012-12-06 | 2016-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for package with interposers |
WO2014199890A1 (ja) | 2013-06-14 | 2014-12-18 | 三菱製紙株式会社 | 配線基板の製造方法 |
CN104793026B (zh) * | 2014-01-20 | 2018-09-28 | 旺矽科技股份有限公司 | 应用于探针测试装置的支撑结构及其制作方法 |
JP6224525B2 (ja) | 2014-05-26 | 2017-11-01 | 京セラ株式会社 | 配線基板および電子装置 |
KR102214512B1 (ko) | 2014-07-04 | 2021-02-09 | 삼성전자 주식회사 | 인쇄회로기판 및 이를 이용한 반도체 패키지 |
JP5873152B1 (ja) | 2014-09-29 | 2016-03-01 | 日本特殊陶業株式会社 | 配線基板 |
US20190206822A1 (en) * | 2017-12-30 | 2019-07-04 | Intel Corporation | Missing bump prevention from galvanic corrosion by copper bump sidewall protection |
-
2019
- 2019-05-15 JP JP2019091823A patent/JP7142604B2/ja active Active
-
2020
- 2020-03-04 US US16/808,597 patent/US10849224B1/en active Active
- 2020-03-30 EP EP20166816.7A patent/EP3740048A1/en active Pending
- 2020-04-17 CN CN202010305466.8A patent/CN111952269A/zh active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007324418A (ja) | 2006-06-01 | 2007-12-13 | Fujitsu Ltd | 半導体装置、はんだバンプ接続用基板の製造方法及び半導体装置の製造方法 |
JP2011142185A (ja) | 2010-01-06 | 2011-07-21 | Renesas Electronics Corp | 半導体装置 |
JP2014207347A (ja) | 2013-04-15 | 2014-10-30 | 株式会社村田製作所 | セラミック多層配線基板およびこれを備えるモジュール |
Also Published As
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JP2020188134A (ja) | 2020-11-19 |
CN111952269A (zh) | 2020-11-17 |
US10849224B1 (en) | 2020-11-24 |
EP3740048A1 (en) | 2020-11-18 |
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