JP7118618B2 - 表示装置 - Google Patents
表示装置 Download PDFInfo
- Publication number
- JP7118618B2 JP7118618B2 JP2017201236A JP2017201236A JP7118618B2 JP 7118618 B2 JP7118618 B2 JP 7118618B2 JP 2017201236 A JP2017201236 A JP 2017201236A JP 2017201236 A JP2017201236 A JP 2017201236A JP 7118618 B2 JP7118618 B2 JP 7118618B2
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- JP
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- Prior art keywords
- display device
- semiconductor film
- film
- pixels
- scanning lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Images
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Theoretical Computer Science (AREA)
- Geometry (AREA)
- Electroluminescent Light Sources (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
[1.全体構成]
本発明の実施形態の一つである表示装置100の構造を説明する。図1に表示装置100の上面模式図を示す。表示装置100は基板102を有し、その上にパターニングされた種々の絶縁膜、半導体膜、導電膜を有する。これらの膜を適宜組み合わせることにより、複数の画素104や画素104を駆動するための駆動回路(走査線側駆動回路108、信号線側駆動回路110)が形成される。各画素104は色情報を与える最小単位であり、後述するように発光素子OLEDやそれを駆動するための駆動回路を含む領域である。複数の画素104は複数の行(第1から第nの行。nは1よりも大きい自然数。)と複数の列(第1から第mの列。mは1よりも大きい自然数)に配置され、表示領域106を定義する。ここで、本明細書と請求項においては、表示領域106とは、基板102上に設けられる全ての画素104、および隣接する画素104の間の領域と重なる単一の領域のうち、後述する切欠き114を除いた領域である。表示領域106を取り囲む基板102上の領域が額縁領域である。
2-1.画素回路
上述したように、各画素104には、パターニングされた種々の絶縁膜や半導体膜、導電膜によって発光素子OLEDを含む画素回路が形成される。画素回路の構成は任意に選択することができ、その一例を等価回路として図3に示す。
図4に表示装置100の模式的断面図を示す。図4では、基板102上に形成された隣接する三つの画素104の画素回路のうち、駆動トランジスタDRT、保持容量Cs、付加容量Cad、発光素子OLEDの断面構造が示されている。
上述したように、表示領域106には開いた形状を有する切欠き114が設けられ、図5に示すように、切欠き114は、複数の画素104がそれぞれ設けられる第1(k=1)行から第k行と交差する。また、これらの行の各々には、画素104と電気的に接続される各種走査線(書込制御走査線128、初期化制御走査線130、補正制御走査線132、発光制御走査線134、リセット制御線136など)が設けられる。以下の説明では、これらの走査線を総じて走査線140と記し、図5では、見やすさを考慮し、各行に対し一本の走査線140のみを示している。したがって、走査線140は上述した各種走査線の一部、あるいは全てであり、例えば走査線140は書込制御走査線128のみによって構成されていてもよい。
本実施形態では、表示装置100の作製方法について、図14(A)から図18(B)を用いて説明する。これらの図のそれぞれにおいて、左側の図は画素を示し、図4の断面図の一部に対応する。一方、右側の図は切欠き114の断面図であり、図8に相当する。第1実施形態と同一、あるいは類似する構成については説明を割愛することがある。
本実施形態では、表示装置100とは構造が異なる表示装置200について説明する。第1、第2実施形態で述べた内容と同一、あるいは類似する内容に関しては説明を割愛することがある。
(第4実施形態)
本実施形態では、表示装置100、200とは構造が異なる表示装置210について説明する。第1から第3実施形態で述べた内容と同一、あるいは類似する内容に関しては説明を割愛することがある。
本実施形態では、表示装置100、200、210とは構造が異なる表示装置230について説明する。第1から第4実施形態で述べた内容と同一、あるいは類似する内容に関しては説明を割愛することがある。
本実施形態では、表示装置100、200、210、230とは構造が異なる表示装置250について説明する。第1から第5実施形態で述べた内容と同一、あるいは類似する内容に関しては説明を割愛することがある。
Claims (11)
- 第1行乃至第n行、および第1列乃至第m列に配置された複数の画素と、
それぞれ対応する前記第1行乃至第n行の画素と電気的に接続される第1乃至第nの走査線と、
前記第1乃至第nの走査線から選択される第1乃至第kの走査線の少なくとも一つと重なる第1の半導体膜と、
前記複数の画素によって定義される表示領域に隣接するとともに、前記表示領域に外接する矩形領域よりも内側に位置する切欠きを有し、
前記第1の半導体膜は前記切欠き内に位置し、
前記複数の画素の各々は、
発光素子と、
前記発光素子と電気的に接続され、第2の半導体膜を有するトランジスタを有し、
前記第1の半導体膜と前記第2の半導体膜は同一層内に存在し、
nとmは1よりも大きい自然数であり、kはnよりも小さい自然数であり、
前記第1の半導体膜は、前記第1乃至第kの走査線の前記少なくとも一つと交差する2辺が互いに非平行である台形の形状を有する、表示装置。 - 前記複数の画素と電気的に接続される複数の電流供給線をさらに有し、
前記第1の半導体膜は、前記複数の電流供給線の少なくとも一つと電気的に接続される、請求項1に記載の表示装置。 - 前記第1乃至第kの走査線は、前記切欠きの端部に沿うように屈曲する、請求項1に記載の表示装置。
- 前記第1乃至第kの走査線の少なくとも一つと重なる前記第1の半導体膜を複数有する、請求項1に記載の表示装置。
- それぞれ対応する前記第1列乃至第m列の画素と電気的に接続される複数の信号線をさらに有し、
前記切欠きと交差する列の前記信号線は、隣接する前記第1の半導体膜に挟まれる、請求項4に記載の表示装置。 - 前記切欠きと交差する前記列の前記信号線は、前記切欠きと交差しない列の前記信号線よりも幅が広い、請求項5に記載の表示装置。
- 第1行乃至第n行、および第1列乃至第m列に配置された複数の画素と、
それぞれ対応する前記第1行乃至第n行の画素と電気的に接続される第1乃至第nの走査線と、
前記第1乃至第nの走査線を制御する走査線側駆動回路と、
前記走査線側駆動回路と、前記第1乃至第nの走査線から選択される第1乃至第kの走査線との間にそれぞれ設けられる第1乃至第kの補償トランジスタと、
前記複数の画素によって定義される表示領域に隣接するとともに、前記表示領域に外接する矩形領域よりも内側に位置する切欠きを有し、
前記第1乃至第kの補償トランジスタは前記表示領域外に位置し、
前記複数の画素の各々は、
第1の半導体膜と、
前記第1の半導体膜と重なる第1のゲート電極と、
前記第1の半導体膜と電気的に接続されるソース/ドレイン電極を有し、
前記第1乃至第kの補償トランジスタは、
第2の半導体膜と、
前記第2の半導体膜と重なる第2のゲート電極と、
前記第2の半導体膜と電気的に接続される第1の端子と第2の端子を有し、
前記第1乃至第kの補償トランジスタの前記第1の端子は、それぞれ対応する前記第1乃至第kの走査線の一部であり、
nとmは1よりも大きい自然数であり、kはnよりも小さい自然数であり、
前記第1乃至第kの補償トランジスタは、前記第1乃至第kの走査線に付与される可変抵抗として機能し、ソース・ドレイン間抵抗が異なるように構成される表示装置。 - 前記第1の半導体膜と前記第2の半導体膜は同一層内に存在する、請求項7に記載の表示装置。
- 前記ソース/ドレイン電極と前記第2のゲート電極は同一層内に存在する、請求項7に記載の表示装置。
- 前記第1乃至第kの補償トランジスタから選択される第jの補償トランジスタの前記第2の端子が延伸する方向と、前記第1乃至第kの走査線から選択される第(j+1)の走査線が延伸する方向は、同一直線上に存在し、
jはkよりも小さい自然数である、請求項7に記載の表示装置。 - 前記第1乃至第kの補償トランジスタから選択される第jの補償トランジスタのチャネル幅は、前記第1乃至第kの補償トランジスタから選択される第(j+1)の補償トランジスタのチャネル幅よりも小さく、
jはkよりも小さい自然数である、請求項7に記載の表示装置。
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