JP7080322B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7080322B2 JP7080322B2 JP2020529912A JP2020529912A JP7080322B2 JP 7080322 B2 JP7080322 B2 JP 7080322B2 JP 2020529912 A JP2020529912 A JP 2020529912A JP 2020529912 A JP2020529912 A JP 2020529912A JP 7080322 B2 JP7080322 B2 JP 7080322B2
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- printed circuit
- circuit board
- thick copper
- wiring pattern
- semiconductor device
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Description
図1は、実施の形態1に係る半導体装置の断面の模式図である。図2は図1の半導体装置の表面側の部品配置を示す図であり、図3は図1の半導体装置の裏面を示す図である。図1の断面の模式図は、図2におけるA-Aの断面の模式図である。実施の形態1の半導体装置50は、プリント基板3と、半導体チップ1、2と、電子部品4と、プリント基板3の裏面に形成された厚銅部材14と、半導体チップ1、2、電子部品4及びプリント基板3の表面(裏面と反対側の面)を封止するキャップ10とを備えている。プリント基板3は一般的に用いられる汎用のプリント基板である。プリント基板3は、FR-4(Flame Retardant Type 4)、FR-5(Flame Retardant Type 5)等の樹脂をベースとした材料を用いた樹脂基材23と、その樹脂基材23の表面又は内層に配線パターン21により形成された高周波回路と、プリント基板3の一部に貫通した穴である開口部29とを備えている。厚銅部材14は100μm以上の厚みを持つ厚銅であり、厚銅部材14により外部電極端子5、6が形成されている。外部電極端子5は半導体チップ1、2を搭載する外部電極端子であり、外部電極端子6は外部電極端子5の外周側に配置された外部電極端子である。プリント基板3の開口部29は、外部電極端子5の表面の一部を露出するように形成されている。半導体チップ1は、周波数1GHz以上の高周波信号を処理し、1W以上の電力を出力する、すなわち高電力密度で能動的な動作を行う半導体素子(能動素子)が形成された半導体チップである。半導体チップ1に形成された能動素子は、例えば、高電力密度のGaN素子である。半導体チップ2は、半導体装置50に搭載される高周波回路の一部を構成する伝送線路等の受動素子が形成された半導体チップである。半導体チップ2は、例えばGaAsなどの半導体のチップである。
図5は、実施の形態2に係る半導体装置の断面の模式図である。実施の形態1の半導体装置50と同一構成要素には同一符号を付して重複する説明を省略する。なお、他の実施の形態においても、実施の形態1の半導体装置50と同一構成要素には同一符号を付して重複する説明を省略する。実施の形態2の半導体装置50は、プリント基板3の開口部29の側面に凹部11が形成されている、すなわち開口部29の側面に凹部11を有する点で、実施の形態1の半導体装置50と異なる。なお、凹部11は、開口部29の側面のどの位置にあってもよい。
図6は、実施の形態3に係る半導体装置の断面の模式図である。実施の形態3の半導体装置50は、プリント基板3の表面に形成された第一配線パターン22aの厚銅部材14を基準にした高さが、半導体チップ1、2の厚銅部材14を基準にした高さの-10%から+10%である点で、実施の形態1の半導体装置50と異なる。図6では、プリント基板3の表面に形成された第一配線パターン22aの厚銅部材14を基準にした高さが半導体チップ1、2の厚銅部材14を基準にした高さと等しい例、すなわちプリント基板3の表面に形成された第一配線パターン22aの表面位置と半導体チップ1、2との表面位置が等しい例を示した。図6に示したように厚銅部材14を基準にした第一配線パターン22aの表面位置と半導体チップ1、2との表面位置とが等しくなっている。実施の形態3の半導体装置50は、厚銅部材14を基準にした第一配線パターン22aの表面位置と半導体チップ1、2との表面位置とが等しくなっているので、プリント基板3の第一配線パターン22aと半導体チップ1、2とを接続する金属ワイヤ12の長さを最短で形成することができる。
図7は、実施の形態4に係る半導体装置の断面の模式図である。実施の形態4の半導体装置50は、プリント基板3が多層プリント基板であり、階段状に形成された開口部29により露出された内部の第二配線パターン22bの厚銅部材14を基準にした高さが、半導体チップ1、2の厚銅部材14を基準にした高さの-10%から+10%である点で、実施の形態1の半導体装置50と異なる。図7では、階段状に形成された開口部29により露出された内部の第二配線パターン22bの厚銅部材14を基準にした高さが半導体チップ1、2の厚銅部材14を基準にした高さと等しい例、すなわち階段状に形成された開口部29により露出された内部の第二配線パターン22bの表面位置と半導体チップ1、2との表面位置が等しい例を示した。図7に示したように厚銅部材14を基準にしたプリント基板3の内部の第二配線パターン22bの表面位置と半導体チップ1、2との表面位置とが等しくなっている。実施の形態4の半導体装置50は、厚銅部材14を基準にしたプリント基板3の内部の第二配線パターン22bの表面位置と半導体チップ1、2との表面位置とが等しくなっているので、プリント基板3の第二配線パターン22bと半導体チップ1、2とを接続する金属ワイヤ12の長さを最短で形成することができる。
図8は、実施の形態5に係る半導体装置の断面の模式図である。図9は図8の接続部材の第一例を示す図であり、図10は図8の接続部材の第二例を示す図である。図11は、図8の半導体装置の裏面を示す図である。実施の形態5の半導体装置50は、厚銅部材14の表面側(半導体チップ1、2の実装面側)に配置された第一のプリント基板(表面側プリント基板)3aと、厚銅部材14の裏面側(半導体チップ1、2の実装面と反対の面側)に第二のプリント基板(裏面側プリント基板)3bとを備えた点で、実施の形態1の半導体装置50と異なる。実施の形態5の半導体装置50は、図1に示した構成において厚銅部材14の裏面に更に第二のプリント基板3bが配置されている。
図12は、実施の形態6に係る半導体装置の断面の模式図である。実施の形態6の半導体装置50は、第二のプリント基板3bが半導体チップ1の直下領域を含むように形成された開口部29と開口部29を埋める銅層24とを備える点で、実施の形態5の半導体装置50と異なる。厚銅部材14の裏面側(半導体チップ1、2の実装面と反対の面側)に配置された第二のプリント基板3bは、能動素子が形成された半導体チップ1の直下領域を含むように開口部29が形成されている。すなわち、第二のプリント基板3bに形成された開口部29は、半導体チップ1が実装された領域が厚銅部材14を基準にした対称の位置である半導体チップ対称領域を含むように形成されている。銅層24は、第二のプリント基板3bに形成された開口部29を埋めるように形成されており、すなわち半導体チップ1が実装された領域が厚銅部材14を基準にした対称の位置である半導体チップ対称領域を覆うように配置されている。図12では、第一のプリント基板3aに形成された開口部29よりも、広い範囲で第二のプリント基板3bの開口部29が形成されている例を示した。第二のプリント基板3bの開口部29は、第二のプリント基板3bの開口部形成工程にて形成される。第二のプリント基板3bの開口部形成工程は、最表面(裏面側の露出面)の第一配線パターン22aが形成される前に、レーザ或いはドリルで厚銅部材14に達する開口部29を形成する。その後、開口部29に例えばめっきにより銅層24を第一配線パターン22aの形成前の樹脂基材23と同一面になるように成長させる。樹脂基材23及び銅層24の露出面に第一配線パターン22aを形成する(外部電極端子形成工程)。外部電極端子5、6は、第二のプリント基板3bの露出面の第一配線パターン22aに形成されている。
Claims (7)
- 実装される実装対象装置に接続する複数の外部電極端子が裏面に形成されると共に、高周波信号を処理する半導体チップが搭載された半導体装置であって、
前記半導体チップが実装される厚銅部材と、
前記厚銅部材の表面に配置されると共に、前記厚銅部材の表面の一部を露出する開口部と、配線パターンと、前記配線パターンと前記厚銅部材とを接続する導電性のビアと、を備えたプリント基板と、
前記厚銅部材の裏面に配置されると共に、他の配線パターンと、前記他の配線パターンと前記厚銅部材とを接続する導電性の他のビアと、を備えた他のプリント基板であって、前記厚銅部材と逆側に露出するように形成された前記他の配線パターンが複数の前記外部電極端子を構成している裏面側プリント基板と、
前記配線パターンと前記他の配線パターンとを接続する導電性の接続部材と、
前記開口部により露出された前記厚銅部材の表面に実装されると共に、前記配線パターンに金属ワイヤで接続された前記半導体チップと、
前記厚銅部材と逆側である前記プリント基板の表面に実装されると共に前記配線パターンに接続された電子部品と、
前記厚銅部材と逆側である前記プリント基板の表面、前記半導体チップ、前記電子部品、前記金属ワイヤを封止するキャップ又はエポキシ樹脂と、を備え、
前記裏面側プリント基板は、前記厚銅部材と反対側の表面に形成された一つの前記外部電極端子と前記厚銅部材の裏面とを接続する銅層を備え、
前記銅層は、前記半導体チップが実装された領域が前記厚銅部材を基準にした対称の位置である半導体チップ対称領域を含むように、かつ前記裏面側プリント基板に形成された開口部を埋めるように形成されており、
前記銅層により埋められた前記裏面側プリント基板の開口部は、前記プリント基板の前記開口部よりも広く形成されていることを特徴とする半導体装置。 - 前記接続部材は、外周側に形成された絶縁性の樹脂と、前記樹脂の内側に形成された金属の層と、前記金属の層の内側に形成された導電性樹脂と、を備えたことを特徴とする請求項1記載の半導体装置。
- 前記接続部材は、外周側に形成された絶縁性の樹脂と、前記樹脂の内側に形成された金属の層と、前記金属の層の内側に形成された絶縁性の樹脂と、を備えたことを特徴とする請求項1記載の半導体装置。
- 前記プリント基板は、前記開口部の側面に凹部を有することを特徴とする請求項1から3のいずれか1項に記載の半導体装置。
- 前記厚銅部材と逆側である前記プリント基板の表面に形成された前記配線パターンは、前記厚銅部材を基準にした高さが、前記厚銅部材を基準にした前記半導体チップの高さの-10%から+10%の高さであることを特徴とする請求項1から4のいずれか1項に記載の半導体装置。
- 前記プリント基板は多層プリント基板であり、
前記プリント基板の前記開口部は、内部に形成された前記配線パターンの一部を露出するように階段状に形成されており、
前記開口部により露出された前記配線パターンは、前記厚銅部材を基準にした高さが、前記厚銅部材を基準にした前記半導体チップの高さの-10%から+10%の高さであることを特徴とする請求項1から4のいずれか1項に記載の半導体装置。 - 前記半導体チップは、能動素子が形成されており、
受動素子が形成された他の半導体チップ又はセラミック基板をさらに備え、
前記他の半導体チップ又は前記セラミック基板は、前記開口部により露出された前記厚銅部材の表面に実装されると共に、前記配線パターン及び前記半導体チップに金属ワイヤで接続されており、
前記他の半導体チップ又は前記セラミック基板は、前記キャップ又はエポキシ樹脂により封止されていることを特徴とする請求項1から6のいずれか1項に記載の半導体装置。
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US11557554B2 (en) | 2023-01-17 |
JPWO2020012598A1 (ja) | 2021-04-30 |
US20210242144A1 (en) | 2021-08-05 |
WO2020012598A1 (ja) | 2020-01-16 |
TW202006900A (zh) | 2020-02-01 |
TWI725426B (zh) | 2021-04-21 |
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