JP6988175B2 - 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 - Google Patents
炭化珪素半導体装置および炭化珪素半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 195
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- 229910052710 silicon Inorganic materials 0.000 description 5
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- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
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- 229910052738 indium Inorganic materials 0.000 description 1
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- 229910052716 thallium Inorganic materials 0.000 description 1
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 description 1
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 1
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Description
本発明にかかる半導体装置は、シリコンよりもバンドギャップが広い半導体(以下、ワイドバンドギャップ半導体とする)を用いて構成される。ここでは、ワイドバンドギャップ半導体として例えば炭化珪素(SiC)を用いた半導体装置(炭化珪素半導体装置)の構造を例に説明する。図1は、実施の形態1にかかる炭化珪素半導体装置の構造を示す断面図である。図1には、2つの単位セル(素子の機能単位)のみを示し、これらに隣接する他の単位セルを図示省略する(図9、図11においても同様)。図1に示す実施の形態1にかかる炭化珪素半導体装置は、炭化珪素からなる半導体基体(炭化珪素基体:半導体チップ)100のおもて面(p+型ベース領域4側の面)側にMOSゲートを備えたMOSFETである。
次に、実施の形態2にかかる炭化珪素半導体装置の構造について説明する。図9は、実施の形態2にかかる炭化珪素半導体装置の構造を示す断面図である。実施の形態2にかかる炭化珪素半導体装置が実施の形態1にかかる炭化珪素半導体装置と異なる点は、ライフタイムキラー領域15に深い準位を作る元素が注入されている点である。
次に、実施の形態3にかかる炭化珪素半導体装置の構造について説明する。図11は、実施の形態3にかかる炭化珪素半導体装置の構造を示す断面図である。実施の形態3にかかる炭化珪素半導体装置が実施の形態2にかかる炭化珪素半導体装置と異なる点は、ライフタイムキラー領域15がトレンチ18と接している点である。
2 n型ドリフト層
3 p+型領域
4 p+型ベース領域
4a 下側p+型ベース領域
4b 上側p+型ベース領域
5 n+型ドリフト領域
5a 第1n+型ドリフト領域
5b 第2n+型ドリフト領域
6 p型エピタキシャル層
7 n++型ソース領域
8 p++型コンタクト領域
9 ゲート絶縁膜
10 ゲート電極
11 層間絶縁膜
12 バリアメタル
13 ソース電極
14 ソース電極パッド
15 ライフタイムキラー領域
16 ドレイン電極
18 トレンチ
19 ボディダイオード領域
Claims (8)
- 炭化珪素基板のおもて面に設けられた第1導電型の第1半導体層と、
前記第1半導体層の、前記炭化珪素基板側に対して反対側に設けられた第2導電型の第2半導体層と、
前記第2半導体層の内部に選択的に設けられた、電子のライフタイムを制御する第2導電型の第1半導体領域と、
前記第2半導体層の内部の、前記第1半導体領域よりも浅い位置に選択的に設けられた、前記炭化珪素基板よりも不純物濃度の高い第1導電型の第2半導体領域と、
前記第2半導体層の内部の、前記第1半導体領域よりも浅い位置に選択的に設けられた、前記第2半導体層よりも不純物濃度の高い第2導電型の第3半導体領域と、
前記第2半導体領域および前記第2半導体層を貫通して前記第1半導体層に達するトレンチと、
前記トレンチの内部にゲート絶縁膜を介して設けられたゲート電極と、
前記第2半導体領域および前記第3半導体領域に接する第1電極と、
前記炭化珪素基板の裏面に設けられた第2電極と、
を備え、
前記第1半導体領域は、前記第2半導体領域および前記第3半導体領域と接していることを特徴とする炭化珪素半導体装置。 - 前記第1半導体領域は、前記トレンチから離して設けられていることを特徴とする請求項1に記載の炭化珪素半導体装置。
- 前記第1半導体領域は、前記第2半導体層よりも結晶欠陥の密度が高いことを特徴とする請求項1または2に記載の炭化珪素半導体装置。
- 前記第1半導体領域は、深い準位を作る元素が注入された領域であることを特徴とする請求項1または2に記載の炭化珪素半導体装置。
- 炭化珪素基板のおもて面に第1導電型の第1半導体層を形成する第1工程と、
前記第1半導体層の上に、第2導電型の第2半導体層を形成する第2工程と、
前記第2半導体層の内部に、電子のライフタイムを制御する第2導電型の第1半導体領域を選択的に形成する第3工程と、
前記第2半導体層の内部の、前記第1半導体領域よりも浅い位置に、前記炭化珪素基板よりも不純物濃度の高い第1導電型の第2半導体領域を選択的に形成する第4工程と、
前記第2半導体層の内部の、前記第1半導体領域よりも浅い位置に、前記第2半導体層よりも不純物濃度の高い第2導電型の第3半導体領域を選択的に形成する第5工程と、
前記第2半導体領域および前記第2半導体層を貫通して前記第1半導体層に達するトレンチを形成する第6工程と、
前記トレンチの内部にゲート絶縁膜を介してゲート電極を形成する第7工程と、
前記第2半導体領域および前記第3半導体領域に接する第1電極を形成する第8工程と、
前記炭化珪素基板の裏面に第2電極を形成する第9工程と、
を備え、
前記第1半導体領域は、前記第2半導体領域および前記第3半導体領域と接するように形成されることを特徴とする炭化珪素半導体装置の製造方法。 - 前記第3工程は、前記第1半導体領域を、前記トレンチから離して形成することを特徴とする請求項5に記載の炭化珪素半導体装置の製造方法。
- 前記第3工程は、前記第1半導体領域を、前記第2半導体層よりも結晶欠陥の密度を高くすることを特徴とする請求項5または6に記載の炭化珪素半導体装置の製造方法。
- 前記第3工程は、前記第1半導体領域を、深い準位を作る元素を注入して形成することを特徴とする請求項5または6に記載の炭化珪素半導体装置の製造方法。
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