JP6911453B2 - 半導体装置およびその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 87
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 230000007547 defect Effects 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 34
- 230000006798 recombination Effects 0.000 claims description 29
- 238000005215 recombination Methods 0.000 claims description 29
- 239000012535 impurity Substances 0.000 claims description 26
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 20
- 229910052799 carbon Inorganic materials 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 9
- 230000007774 longterm Effects 0.000 claims description 6
- 230000001737 promoting effect Effects 0.000 claims description 6
- 230000007812 deficiency Effects 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 238000010894 electron beam technology Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000000969 carrier Substances 0.000 description 15
- 238000006243 chemical reaction Methods 0.000 description 13
- 230000006866 deterioration Effects 0.000 description 9
- 230000007423 decrease Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
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- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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Description
実施の形態にかかる半導体装置の構造について説明する。図1は、実施の形態にかかる半導体装置の構造を示す断面図である。半導体装置として、半導体基板にSiCを用いたSiC PiNダイオードの例を示す。以下の説明では、第1導電型がn型であり、第2導電型がp型である例を用いて説明する。
実施の形態2のPINダイオードは、実施の形態1で説明したバッファ層6を含むほぼ同様の構造を有する。実施の形態2では、高濃度のn+型SiC基板1(例えば、濃度例1×1019/cm3)上に、n型のバッファ層6およびドリフト層2等をエピタキシャル成長中、バッファ層およびドリフト層2の全領域にわたって炭素欠損による欠陥準位を導入するようにC/Si比を調整する。
実施の形態3のPINダイオードは、実施の形態1で説明したバッファ層6を含むほぼ同様の構造を有する。実施の形態3では、高濃度のn+型SiC基板1(例えば、濃度例1×1019/cm3)上に、BPD→TED変換の変換層9をエピタキシャル成長などで形成する。そして、変換層9上に再結合を促進させるn型のバッファ層6をエピタキシャル成長などで形成する(例えば、濃度例1×1018/cm3以上、厚さ1μm以上)。
(2)ドリフト層の全領域に1×1013/cm3の欠陥準位を導入した欠陥準位が導入されたn-型ドリフト層5を持つPINダイオード(従来構造、図4)
(3)5μm厚の高不純物濃度のn型バッファ層4(5×1018/cm3)を持つPIN型ダイオード(従来構造、図5)
(4)1×1013/cm3の欠陥準位をバッファ層にのみ導入した同じ高不純物濃度のバッファ層6を持つPINダイオード(実施の形態1、図1)
2 n-型のドリフト層
3 p型層
4 n型バッファ層
5 欠陥準位が導入されたn-型のドリフト層
6 欠陥準位が導入されたn型のバッファ層
7 表面電極
8 裏面電極
9 変換層
Claims (4)
- 第1導電型の半導体基板上に形成された第1導電型で低不純物濃度の第1高抵抗半導体領域と、
前記半導体基板と対向する面に設けられた第2導電型の第2半導体領域と、
前記第1高抵抗半導体領域と前記半導体基板との間に、前記第1高抵抗半導体領域よりも高不純物濃度の第1導電型の第3半導体領域を再結合促進層として備え、
前記第3半導体領域と前記第1高抵抗半導体領域全領域にわたって炭素欠損による欠陥準位が導入され、かつ、前記第3半導体領域よりも表面側の領域のみ炭素空孔欠陥が減少しており、前記第3半導体領域内に再結合サイトとして欠陥準位が1×1012/cm3以上の高濃度で導入されていることを特徴とする半導体装置。 - 前記第3半導体領域内に前記再結合サイトとして、炭素欠乏欠陥準位であるZ1/2準位を用いることを特徴とする請求項1に記載の半導体装置。
- 第1導電型の半導体基板上に第1導電型で低不純物濃度の第1高抵抗半導体領域を形成する工程と、
前記半導体基板と対向する面に第2導電型の第2半導体領域を形成する工程と、
前記第1高抵抗半導体領域と前記半導体基板との間に、前記第1高抵抗半導体領域よりも高不純物濃度の第1導電型の第3半導体領域を再結合促進層として形成する工程と、
前記第3半導体領域と前記第1高抵抗半導体領域全領域にわたって炭素欠損による欠陥準位を導入する工程と、
炭素注入後の長時間アニールもしくはカーボンキャップした後の長時間酸化により、前記第3半導体領域よりも表面側の領域のみ炭素空孔欠陥を減少させる工程と、を含み、
前記第3半導体領域内に再結合サイトとして欠陥準位を1×1012/cm3以上の高濃度で導入したことを特徴とする半導体装置の製造方法。 - 前記第3半導体領域に電子線照射もしくはプロトンを照射し所定の欠陥準位を導入することを特徴とする請求項3に記載の半導体装置の製造方法。
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JP7023882B2 (ja) * | 2019-02-04 | 2022-02-22 | 株式会社東芝 | 半導体装置の製造方法、基板の製造方法、半導体装置、基板、及び、基板の製造装置 |
JP7443669B2 (ja) * | 2019-03-27 | 2024-03-06 | 富士電機株式会社 | 炭化珪素エピタキシャル基板、炭化珪素エピタキシャル基板の製造方法、炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
JP2021014378A (ja) * | 2019-07-11 | 2021-02-12 | 富士電機株式会社 | 多層構造体、多層構造体の製造方法及び半導体装置の製造方法 |
WO2021060369A1 (ja) | 2019-09-27 | 2021-04-01 | 学校法人関西学院 | SiC基板、SiC基板の製造方法、SiC半導体装置およびSiC半導体装置の製造方法 |
CN114792688A (zh) * | 2021-01-26 | 2022-07-26 | 上峰科技股份有限公司 | 电子***、与宽带隙半导体器件集成的可编程电阻存储器及其操作方法 |
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JP3643100B2 (ja) * | 2002-10-04 | 2005-04-27 | 松下電器産業株式会社 | 半導体装置 |
JP2009088223A (ja) | 2007-09-28 | 2009-04-23 | Hitachi Cable Ltd | 炭化珪素半導体基板およびそれを用いた炭化珪素半導体装置 |
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JP2011109018A (ja) * | 2009-11-20 | 2011-06-02 | Kansai Electric Power Co Inc:The | バイポーラ半導体素子 |
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US9590047B2 (en) * | 2012-04-04 | 2017-03-07 | Fairchild Semiconductor Corporation | SiC bipolar junction transistor with reduced carrier lifetime in collector and a defect termination layer |
US20140374882A1 (en) * | 2013-06-21 | 2014-12-25 | Infineon Technologies Austria Ag | Semiconductor Device with Recombination Centers and Method of Manufacturing |
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JP6271356B2 (ja) * | 2014-07-07 | 2018-01-31 | 株式会社東芝 | 半導体装置の製造方法 |
JP6237915B2 (ja) * | 2014-09-04 | 2017-11-29 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP2016100455A (ja) * | 2014-11-21 | 2016-05-30 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
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JP2016127177A (ja) * | 2015-01-06 | 2016-07-11 | 住友電気工業株式会社 | 炭化珪素基板、炭化珪素半導体装置および炭化珪素基板の製造方法 |
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JP6584966B2 (ja) * | 2016-01-12 | 2019-10-02 | 株式会社東芝 | 半導体装置、半導体装置の製造方法、インバータ回路、駆動装置、車両、及び昇降機 |
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