JP6870119B2 - 半導体装置および電力変換装置 - Google Patents
半導体装置および電力変換装置 Download PDFInfo
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- JP6870119B2 JP6870119B2 JP2019566712A JP2019566712A JP6870119B2 JP 6870119 B2 JP6870119 B2 JP 6870119B2 JP 2019566712 A JP2019566712 A JP 2019566712A JP 2019566712 A JP2019566712 A JP 2019566712A JP 6870119 B2 JP6870119 B2 JP 6870119B2
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- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
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Description
[装置構成]
図1は、本発明の実施の形態1に係る半導体装置であるショットキーバリアダイオード(SBD)100の部分断面図である。図2は、SBD100の平面図であり、図2のA−A線に沿った矢視断面図が図1に相当する。図1の左側部分は、SBD100のオン状態において主電流が流れる活性領域であり、図1の右側部分は、SBD100の活性領域の外側の領域である終端領域である。以下、活性領域に相当する領域を「内側領域RI」と称し、終端領域に相当する領域を「外側領域RO」と称す。
図8は、実施の形態1の変形例に係るSBD101の構成を示す断面図であり、図1に対応する図である。図8のSBD101の外側領域ROには、図7と同様に、互いに離間して入れ子状に配設された複数の終端ウェル領域2が設けられている。さらに、複数の終端ウェル領域2のそれぞれと接続するように、複数の表面電極5が入れ子状に設けられている。
実施の形態1のSBD100の動作について説明する。表面電極5の電位を基準として、裏面電極8に負の電圧が印加されると、SBD100は、表面電極5から裏面電極8に向けて電流が流れる状態、すなわち導通状態(オン状態)となる。反対に、表面電極5の電位を基準として、裏面電極8に正の電圧が印加されると、SBD100は阻止状態(オフ状態)となる。
H2O + e− → OH− + 1/2H2 ・・・(2)
実施の形態1に係るSBD100の製造方法について説明する。
以上のように、実施の形態1に係るSBD100およびその変形例に係るSBD101によれば、終端領域のコーナー部において電極パッド5bの端部で水酸化アルミニウムが生成することを抑制でき、それにより、表面保護膜6の剥離が防止される。よって、表面保護膜6の剥離に起因したリーク電流の増加および気中放電を防止でき、SBDの絶縁信頼性を高めることができる。
[装置構成]
図10は、本発明の実施の形態2に係る半導体装置であるMOSFET200の構成を示す部分断面図である。図11は、MOSFET200の平面図であり、図11のB−B線に沿った矢視断面図が図10に相当する。また、図12は、活性領域である内側領域RIに形成されるMOSFETの最小単位構造であるユニットセルUCの構成を示す断面図である。MOSFET200の内側領域RIには、図12に示すユニットセルUCが複数配列されている(図10の左端部分には最外周のユニットセルUCが示されている)。なお、図10〜図12においては、図1および図2に示した実施の形態1に係るSBD100の構成要素と同一の機能を有する要素には、それと同一の符号を付しているため、ここでは実施の形態1と重複する説明は省略する。
図13は、実施の形態2の変形例に係るMOSFET201の構成を示す平面図であり、図11に対応する図である。図13のMOSFET201は、矩形のソース電極51の一辺から設けられた凹部が、ソース電極51内に深く入り込むように延在し、さらに、ゲート配線電極52がその凹部に入り込むように延在している。つまり、図11のMOSFET200では、ソース電極51の一辺に設けられた凹部にゲートパッド52pだけが入り込み、ゲート配線52wはソース電極51を囲むように設けられていたが、図13のMOSFET201では、ソース電極51の凹部に細長いゲート配線52wが入り込み、その凹部の入口部分にゲートパッド52pが設けられている。
図10に示した実施の形態2のMOSFET200の動作を、2つの状態に分けて説明する。
次に、実施の形態2のMOSFET200の製造方法について説明する。
以上のように、実施の形態2に係るMOSFET200およびその変形例に係るMOSFET201によれば、終端領域のコーナー部において表面電極50の端部で水酸化アルミニウムが生成することを抑制でき、それにより、表面保護膜6の剥離が防止される。よって、表面保護膜6の剥離に起因したリーク電流の増加および気中放電を防止でき、MOSFETの絶縁信頼性を高めることができる。
本実施の形態は、上述した実施の形態1および2に係る半導体装置を電力変換装置に適用したものである。以下、実施の形態3として、三相のインバータに実施の形態1および2に係る半導体装置を適用した場合について説明する。
Claims (9)
- 炭化珪素から成る半導体基板(31)と、
前記半導体基板(31)上に形成された炭化珪素から成る第1導電型のドリフト層(1)と、
活性領域(RI)の前記ドリフト層(1)の表層部に形成された第2導電型のウェル領域(9)と、
前記ウェル領域(9)の表層部に形成された第1導電型のソース領域(11)と、
前記ウェル領域(9)における前記ソース領域(11)と前記ドリフト層(1)との間の領域であるチャネル領域を覆うゲート絶縁膜(12)と、
前記ゲート絶縁膜(12)上に形成されたゲート電極(13)と、
前記ゲート電極(13)を覆う層間絶縁膜(14)と、
前記活性領域(RI)の外側の終端領域(RO)において、前記ドリフト層(1)の表層部に、前記活性領域(RI)を平面視で取り囲むように形成された第2導電型の終端ウェル領域(20)と、
前記ドリフト層(1)上に、前記終端ウェル領域(20)の一部を覆うように形成されたフィールド絶縁膜(3)と、
前記フィールド絶縁膜(3)よりも内側の前記ドリフト層(1)上に形成され、前記終端ウェル領域(20)と電気的に接続した、Al、Cu、Mo、Niのいずれか1つまたは複数を含む金属、あるいは、Al合金を材料とする部分を有する表面電極(50)と、
前記フィールド絶縁膜(3)および前記表面電極(50)上に形成され、前記表面電極(50)の外側の端部を覆う上面膜(6)と、
前記半導体基板(31)の裏面に形成された裏面電極(8)と、
を備え、
前記表面電極(50)は、
前記層間絶縁膜(14)上に形成され、前記層間絶縁膜(14)に形成されたコンタクトホールを通して前記ソース領域(11)と電気的に接続したソース電極(51)と、
前記層間絶縁膜(14)上に、前記ソース電極(51)を平面視で取り囲むように形成され、前記層間絶縁膜(14)に形成されたコンタクトホールを通して前記ゲート電極(13)と電気的に接続したゲート配線(52)と、を含み、
前記終端領域(RO)は、平面視で、直線部および曲線状のコーナー部を有しており、
前記表面電極(50)の外側の端部は、前記終端ウェル領域(20)の外側の端部よりも内側に位置し、
前記終端ウェル領域(20)の外側の端部から前記表面電極(50)の外側の端部までの距離に関し、前記終端領域(RO)のコーナー部における当該距離は、前記終端領域(RO)の直線部における当該距離よりも長い、
ことを特徴とした半導体装置。 - 前記終端ウェル領域(20)は、境界領域(21)と、前記境界領域(21)から外側へ延在し前記境界領域(21)より不純物濃度が低い延長領域(22)とを備えたことを特徴とした、
請求項1に記載の半導体装置。 - 前記延長領域(22)の不純物濃度は、前記ウェル領域(9)の不純物濃度よりも低いことを特徴とした、
請求項2に記載の半導体装置。 - 前記延長領域(22)のドーズ量は、0.5×10 13 /cm 2 以上5×10 13 /cm 2 以下であることを特徴とする
請求項2または請求項3に記載の半導体装置。 - 前記延長領域(22)の不純物濃度は、1×10 17 /cm 3 以上5×10 19 /cm 3 以下であることを特徴とする
請求項2または請求項3に記載の半導体装置。 - 半導体基板(31)と、
前記半導体基板(31)上に形成された第1導電型のドリフト層(1)と、
活性領域(RI)の外側の終端領域(RO)において、前記ドリフト層(1)の表層部に、前記活性領域(RI)を平面視で取り囲むように形成された第2導電型の終端ウェル領域(2;20)と、
前記ドリフト層(1)上に、前記終端ウェル領域(2;20)の一部を覆うように形成されたフィールド絶縁膜(3)と、
前記フィールド絶縁膜(3)よりも内側の前記ドリフト層(1)上に形成され、前記終端ウェル領域(2;20)と電気的に接続した表面電極(5;50)と、
前記フィールド絶縁膜(3)および前記表面電極(5;50)上に形成され、前記表面電極(5;50)の外側の端部を覆う上面膜(6)と、
前記半導体基板(31)の裏面に形成された裏面電極(8)と、
を備え、
前記終端領域(RO)は、平面視で、直線部およびコーナー部を有しており、
前記終端ウェル領域(2;20)の外側の端部の位置を基準にして、前記終端領域(RO)のコーナー部における前記表面電極(5;50)の外側の端部は、前記終端領域(RO)の直線部における前記表面電極(5;50)の外側の端部よりも内側に位置しており、
前記表面電極(5;50)の外側の端部は、前記終端ウェル領域(2;20)の外側の端部よりも外側に位置し、
前記終端ウェル領域(2;20)の外側の端部から前記表面電極(5;50)の外側の端部までの距離に関し、前記終端領域(RO)のコーナー部における当該距離は、前記終端領域(RO)の直線部における当該距離よりも短い、
ことを特徴とした半導体装置。 - 互いに離間して入れ子状に形成された複数の前記終端ウェル領域(2;20)を備える、
請求項1から請求項6のいずれか一項に記載の半導体装置。 - 前記表面電極(5;50)は、複数の前記終端ウェル領域(2;20)のうちの少なくとも1つと電気的に接続している、
請求項7に記載の半導体装置。 - 請求項1から請求項8のいずれか一項に記載の半導体装置を有し、入力される電力を変換して出力する主変換回路(2001)と、
前記半導体装置を駆動する駆動信号を前記半導体装置に出力する駆動回路(2002)と、
前記駆動回路(2002)を制御する制御信号を前記駆動回路(2002)に出力する制御回路(2003)と、
を備えた電力変換装置。
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