JP6843570B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP6843570B2 JP6843570B2 JP2016189209A JP2016189209A JP6843570B2 JP 6843570 B2 JP6843570 B2 JP 6843570B2 JP 2016189209 A JP2016189209 A JP 2016189209A JP 2016189209 A JP2016189209 A JP 2016189209A JP 6843570 B2 JP6843570 B2 JP 6843570B2
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
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- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
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- H—ELECTRICITY
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- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
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- H—ELECTRICITY
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- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
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- Condensed Matter Physics & Semiconductors (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Description
図1は、第1実施形態に係る半導体装置の断面構造を示す模式図である。本実施形態の半導体装置は、図1に示すように、半導体基板1と支持基板2とが接着層3を介して貼り合わされた構造を有している。ここで、半導体基板1は例えばシリコン等で構成された半導体基板であり、支持基板2は例えば透光板であり得る。但し、半導体基板1及び支持基板2の材質はこれらに限定されるものではない。
次に、図3及び図4を参照しながら、第2実施形態に係る半導体装置について説明する。本実施形態では、応力緩和溝61を形成する際に、同時に貫通電極用の孔を形成する方法について説明する。以下、第1実施形態と異なる点を中心に説明する。
次に、図5及び図6を参照しながら、第3実施形態に係る半導体装置について説明する。本実施形態では、応力緩和溝61と孔70の面積に応じたエッチングレートの違いを利用して、接着層3が露出しないように応力緩和溝61及び孔70を形成する方法について説明する。以下、第2実施形態と異なる点を中心に説明する。
次に、図7及び図8を参照しながら、第4実施形態に係る半導体装置について説明する。本実施形態では、ダイシング工程を行う際にエッチングストッパ層15を除去する方法について説明する。以下、第2実施形態と異なる点を中心に説明する。
なお、上述の実施形態は、いずれも本発明を実施するにあたっての具体化の例を示したものに過ぎず、これらによって本発明の技術的範囲が限定的に解釈されてはならないものである。すなわち、本発明はその技術思想、又はその主要な特徴から逸脱することなく、様々な形で実施することができる。例えば、上述の各実施形態は、組み合わせて適用することも可能である。
2 :支持基板
3 :接着層
4 :絶縁膜
6 :スクライブ領域
10 :層間絶縁層(絶縁層)
11 :半導体素子
12 :素子分離部
13 :コンタクトホール
14 :電極部(第1の導電層)
15 :エッチングストッパ層(第2の導電層)
51 :第1のマスク
52 :第2のマスク
61 :応力緩和溝
70 :孔
71 :貫通電極
Claims (7)
- チップ領域及び該チップ領域の間のスクライブ領域を含み、第1面上に、同層に形成された第1の導電層及び第2の導電層と半導体素子とが配された半導体基板を、少なくとも接着層を介して支持基板と接合する接合ステップと、
前記半導体基板の前記第1面とは反対の第2面の側から、前記半導体基板の前記スクライブ領域に、前記接着層を露出させずに、前記第2の導電層が露出された底面を備える溝を形成する溝形成ステップと、
前記半導体基板の前記第1面とは反対の第2面の側から、前記半導体基板の前記チップ領域に、前記接着層を露出させずに、前記第1の導電層を露出させるまで孔を形成し、該孔に前記第1の導電層と接触するように貫通電極を形成する貫通電極形成ステップと、
チップが前記チップ領域を含むが前記スクライブ領域を含まないように、前記半導体基板を前記スクライブ領域内の前記溝に沿ってダイシングしてチップ化するダイシングステップと
を有することを特徴とする半導体装置の製造方法。 - 前記溝形成ステップにおいて、前記溝を、前記半導体基板と前記接着層の間の絶縁層に達するように形成する
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記溝形成ステップと前記ダイシングステップとの間に、前記溝の底面に露出する層を、前記溝を形成する際のエッチング手段とは異なるエッチング手段で除去するステップを更に有する
ことを特徴とする請求項1又は2に記載の半導体装置の製造方法。 - 前記貫通電極用の前記孔を前記溝とともに前記半導体基板に形成する
ことを特徴とする請求項1から3のいずれか1項に記載の半導体装置の製造方法。 - 前記溝形成ステップの前又は後において、前記貫通電極用の前記孔を形成する
ことを特徴とする請求項1から4のいずれか1項に記載の半導体装置の製造方法。 - 前記貫通電極形成ステップは、前記溝をマスクした上で、前記孔に導電材料を埋め込んで前記第1の導電層と前記貫通電極とを接続するステップを更に有する
ことを特徴とする請求項4又は5に記載の半導体装置の製造方法。 - 前記溝形成ステップの後に、前記半導体基板の第2面を洗浄するステップを更に有する
ことを特徴とする請求項1から6のいずれか1項に記載の半導体装置の製造方法。
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JP2016189209A JP6843570B2 (ja) | 2016-09-28 | 2016-09-28 | 半導体装置の製造方法 |
US15/711,589 US10424548B2 (en) | 2016-09-28 | 2017-09-21 | Method of manufacturing semiconductor device |
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JP2019177119A (ja) * | 2018-03-30 | 2019-10-17 | 株式会社三洋物産 | 遊技機 |
WO2020093228A1 (en) * | 2018-11-06 | 2020-05-14 | Shenzhen Xpectvision Technology Co., Ltd. | Packaging methods of semiconductor devices |
KR102677511B1 (ko) | 2019-07-19 | 2024-06-21 | 삼성전자주식회사 | 반도체 장치 및 반도체 패키지 |
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JPH05335292A (ja) | 1992-05-28 | 1993-12-17 | Nec Corp | 半導体装置の製造方法 |
JPH076982A (ja) | 1992-07-31 | 1995-01-10 | Sharp Corp | 薄層半導体基板の分割方法 |
JP3662260B2 (ja) * | 1996-09-24 | 2005-06-22 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
EP1478021B1 (en) * | 2003-05-15 | 2008-07-16 | Sanyo Electric Co., Ltd. | Semiconductor device and manufacturing method thereof |
JP2005026314A (ja) | 2003-06-30 | 2005-01-27 | Sanyo Electric Co Ltd | 固体撮像素子の製造方法 |
JP4307284B2 (ja) * | 2004-02-17 | 2009-08-05 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP2005268238A (ja) | 2004-03-16 | 2005-09-29 | Sony Corp | 裏面照射型固体撮像装置及びその製造方法 |
CN100395886C (zh) * | 2004-07-16 | 2008-06-18 | 新光电气工业株式会社 | 半导体器件的制造方法 |
US7518217B2 (en) | 2004-11-11 | 2009-04-14 | Yamaha Corporation | Semiconductor device, semiconductor wafer, chip size package, and methods of manufacturing and inspection therefor |
JP4696595B2 (ja) | 2005-02-28 | 2011-06-08 | ヤマハ株式会社 | 半導体ウェーハ及び半導体素子並びに半導体素子の製造方法 |
JP5344336B2 (ja) * | 2008-02-27 | 2013-11-20 | 株式会社ザイキューブ | 半導体装置 |
JP2009277883A (ja) | 2008-05-14 | 2009-11-26 | Sharp Corp | 電子素子ウェハモジュールおよびその製造方法、電子素子モジュール、電子情報機器 |
JP5318634B2 (ja) * | 2009-03-30 | 2013-10-16 | ラピスセミコンダクタ株式会社 | チップサイズパッケージ状の半導体チップ及び製造方法 |
KR101712630B1 (ko) * | 2010-12-20 | 2017-03-07 | 삼성전자 주식회사 | 반도체 소자의 형성 방법 |
JP6300029B2 (ja) | 2014-01-27 | 2018-03-28 | ソニー株式会社 | 撮像素子、製造装置、製造方法 |
US20160190353A1 (en) * | 2014-12-26 | 2016-06-30 | Xintec Inc. | Photosensitive module and method for forming the same |
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US20180090453A1 (en) | 2018-03-29 |
US10424548B2 (en) | 2019-09-24 |
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