JP6815880B2 - 半導体パッケージの製造方法 - Google Patents
半導体パッケージの製造方法 Download PDFInfo
- Publication number
- JP6815880B2 JP6815880B2 JP2017011165A JP2017011165A JP6815880B2 JP 6815880 B2 JP6815880 B2 JP 6815880B2 JP 2017011165 A JP2017011165 A JP 2017011165A JP 2017011165 A JP2017011165 A JP 2017011165A JP 6815880 B2 JP6815880 B2 JP 6815880B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- sealing
- semiconductor package
- shield layer
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 216
- 238000004519 manufacturing process Methods 0.000 title claims description 64
- 238000007789 sealing Methods 0.000 claims description 144
- 239000000758 substrate Substances 0.000 claims description 78
- 238000000034 method Methods 0.000 claims description 77
- 229920005989 resin Polymers 0.000 claims description 72
- 239000011347 resin Substances 0.000 claims description 72
- 238000002360 preparation method Methods 0.000 claims description 40
- 239000004020 conductor Substances 0.000 claims description 26
- 230000002093 peripheral effect Effects 0.000 claims description 10
- 239000003795 chemical substances by application Substances 0.000 claims description 7
- 230000000903 blocking effect Effects 0.000 claims description 2
- 239000000565 sealant Substances 0.000 claims description 2
- 238000005520 cutting process Methods 0.000 description 42
- 239000006258 conductive agent Substances 0.000 description 32
- 238000010586 diagram Methods 0.000 description 22
- 238000000227 grinding Methods 0.000 description 15
- 238000004544 sputter deposition Methods 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000007650 screen-printing Methods 0.000 description 4
- 238000003475 lamination Methods 0.000 description 3
- 238000010295 mobile communication Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 208000032365 Electromagnetic interference Diseases 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000002679 ablation Methods 0.000 description 2
- 239000006061 abrasive grain Substances 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000007921 spray Substances 0.000 description 2
- 229920002803 thermoplastic polyurethane Polymers 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000007733 ion plating Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 229920006337 unsaturated polyester resin Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
- H01L2924/15156—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Ceramic Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
以下、図2から図5を参照して、第1の実施の形態の半導体パッケージの製造方法について説明する。図2は、第1の実施の形態の配線基板の斜視図である。図3及び図4は、第1の実施の形態の半導体パッケージの製造方法の説明図である。図5は、第1の実施の形態の半導体パッケージの製造方法の変形例を示す図である。なお、図3Aは配線基板準備工程、図3Bはチップマウント工程、図3Cは封止基板形成工程のそれぞれ一例を示す図である。図4Aは研削工程、図4Bは個片化工程、図4Cは上面シールド層形成工程のそれぞれ一例を示す図である。
図6から図8を参照して、第2の実施の形態の半導体パッケージの製造方法について説明する。図6及び図7は、第2の実施の形態の半導体パッケージの製造方法の説明図である。図8は、第2の実施の形態の半導体パッケージの製造方法の変形例を示す図である。なお、図6Aは配線基板準備工程、図6Bはチップマウント工程、図6Cは封止基板形成工程のそれぞれ一例を示す図である。図7Aは切削工程、図7Bは個片化工程、図7Cは上面シールド層形成工程のそれぞれ一例を示す図である。なお、第2の実施の形態では、第1の実施の形態と同様な構成について極力省略して説明する。
図9を参照して、第3の実施の形態の半導体パッケージの製造方法について説明する。なお、第3の実施の形態の半導体パッケージの製造方法は、配線基板準備工程についてのみ第1、第2の実施の形態の半導体パッケージの製造方法と相違する。したがって、ここでは第3の実施の形態の配線基板準備工程について説明する。図9は、第3の実施の形態の配線基板準備工程の一例を示す図である。
図10を参照して、第4の実施の形態の半導体パッケージの製造方法について説明する。なお、第4の実施の形態の半導体パッケージの製造方法は、配線基板準備工程についてのみ第1、第2の実施の形態の半導体パッケージの製造方法と相違する。したがって、ここでは配線基板準備工程について主に説明する。図10は、第4の実施の形態の配線基板準備工程の一例を示す図である。なお、図10A及び図10Bはシーリング工程、図10Cは立設囲繞部形成工程のそれぞれ一例を示す図である。図11は、第4の実施の形態の封止基板形成工程の一例を示す図である。
図12を参照して、第5の実施の形態の半導体パッケージの製造方法について説明する。なお、第5の実施の形態の半導体パッケージの製造方法は、配線基板準備工程についてのみ第1、第2の実施の形態の半導体パッケージの製造方法と相違する。したがって、ここでは配線基板準備工程について主に説明する。図12は、第5の実施の形態の配線基板準備工程の一例を示す図である。なお、図12A及び図12Bは配設工程、図12Cは立設囲繞部形成工程のそれぞれ一例を示す図である。図13は、第5の実施の形態の封止基板形成工程の一例を示す図である。
11、41、71、81、101 配線基板(PCB)
12、42、78、89、109 半導体チップ
13、43 樹脂層(封止樹脂)
15、45、92、112 封止基板
16、46、91、111 封止樹脂
17、47、77、88、108 側面シールド層
18、48 上面シールド層
21、51、75、87、107 立設囲繞部
22 分割予定ライン
23、53、73、83、103 マウント部
74 絶縁フィルム
76、86、106 導電材
84、104 導電剤
85、105 開口インターポーザ
Claims (6)
- 封止樹脂により半導体チップが封止された半導体パッケージを作成する半導体パッケージの製造方法であって、
配線基板の上面に交差する分割予定ラインによって区画された各領域に形成され半導体チップを上面にマウントする複数のマウント部と、複数の該マウント部と該分割予定ラインとの間に各該マウント部を囲繞して形成された立設囲繞部と、該立設囲繞部内で該マウント部を囲繞し厚み方向に渡って電磁波を遮断する側面シールド層と、を備えた該配線基板を準備する配線基板準備工程と、
該配線基板上の該マウント部に複数の半導体チップをマウントするチップマウント工程と、
該半導体チップがマウントされた該配線基板の該立設囲繞部の内側に封止樹脂を供給して該半導体チップを封止樹脂で封止して封止基板を形成する封止基板形成工程と、
該封止基板形成工程を実施した後に、該分割予定ラインに沿って該封止基板を分割して個々の半導体パッケージに個片化する個片化工程と、
該封止基板形成工程を実施した後に、複数の該半導体パッケージの封止樹脂上面に電磁波を遮断する上面シールド層を形成する上面シールド層形成工程と、を備え、
該立設囲繞部の内周面は、該マウント部に向かって開口面積が徐々に狭くなるように形成されていることを特徴とする半導体パッケージの製造方法。 - 該封止基板形成工程を実施した後で且つ該上面シールド層形成工程を実施する前に、該封止樹脂の表面を平坦化するとともに該立設囲繞部上面に供給された封止樹脂を除去し、
該立設囲繞部内に形成された該側面シールド層の先端を該立設囲繞部上面に表出させる除去工程を実施する、請求項1記載の半導体パッケージの製造方法。 - 該封止基板形成工程を実施した後に、該立設囲繞部上面に供給された封止樹脂を該側面シールド層に沿って除去し、該立設囲繞部内に形成された該側面シールド層の先端を表出させる除去工程を備える請求項1記載の半導体パッケージの製造方法。
- 該配線基板準備工程は、
該配線基板上に、あらかじめ該マウント部に該半導体チップをマウントするための開口が形成されると共に該開口を囲繞する導電材が充填された複数の絶縁フィルムを積層ラミネートして該立設囲繞部及び該側面シールド層を形成すること、を特徴とする請求項1乃至3に記載の半導体パッケージの製造方法。 - 該配線基板準備工程は、
該配線基板上の複数の該マウント部をそれぞれ囲繞して導電性のシーリング剤でシーリングするシーリング工程と、
各該マウント部に該半導体チップをマウントするための開口を複数有し、該開口を囲繞する導電材を含む開口インターポーザを、該開口を該配線基板の該マウント部にそれぞれ対応させて位置付けて該導電性のシーリング剤で接着して該立設囲繞部及び該側面シールド層を形成する立設囲繞部形成工程と、から構成され、
該封止基板形成工程においては、該半導体チップがマウントされた該配線基板、該開口インターポーザ、該導電性のシーリング剤の間を封止樹脂で封止して該封止基板を形成すること、を特徴とする請求項1乃至3記載の半導体パッケージの製造方法。 - 該配線基板準備工程は、
該配線基板上の複数のマウント部をそれぞれ囲繞して導電性のシーリング剤を間隔をあけて配設する配設工程と、
各該マウント部に該半導体チップをマウントするための開口を複数有し、該開口を囲繞する導電材を含む開口インターポーザを、該開口を該配線基板の該マウント部にそれぞれ対応させて位置付けて該導電性のシーリング剤で接着して該立設囲繞部及び該側面シールド層を形成する立設囲繞部形成工程と、から構成され、該導電性のシーリング剤の間隔は、該電磁波の波長よりも狭くして電磁波を遮断し、
該封止基板形成工程においては、該半導体チップがマウントされた該配線基板、該開口インターポーザ、複数の該導電性のシーリング剤の間を封止樹脂で封止して該封止基板を形成すること、を特徴とする請求項1乃至3記載の半導体パッケージの製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017011165A JP6815880B2 (ja) | 2017-01-25 | 2017-01-25 | 半導体パッケージの製造方法 |
KR1020180006631A KR102334782B1 (ko) | 2017-01-25 | 2018-01-18 | 반도체 패키지의 제조 방법 |
CN201810058502.8A CN108364933B (zh) | 2017-01-25 | 2018-01-22 | 半导体封装的制造方法 |
TW107102321A TWI735733B (zh) | 2017-01-25 | 2018-01-23 | 半導體封裝件之製造方法 |
US15/879,082 US10431555B2 (en) | 2017-01-25 | 2018-01-24 | Method of manufacturing semiconductor package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017011165A JP6815880B2 (ja) | 2017-01-25 | 2017-01-25 | 半導体パッケージの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2018120950A JP2018120950A (ja) | 2018-08-02 |
JP6815880B2 true JP6815880B2 (ja) | 2021-01-20 |
Family
ID=62907155
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017011165A Active JP6815880B2 (ja) | 2017-01-25 | 2017-01-25 | 半導体パッケージの製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US10431555B2 (ja) |
JP (1) | JP6815880B2 (ja) |
KR (1) | KR102334782B1 (ja) |
CN (1) | CN108364933B (ja) |
TW (1) | TWI735733B (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6815880B2 (ja) * | 2017-01-25 | 2021-01-20 | 株式会社ディスコ | 半導体パッケージの製造方法 |
EP3756424A1 (en) * | 2018-02-22 | 2020-12-30 | Dexcom, Inc. | Sensor interposers employing castellated through-vias |
US10804188B2 (en) | 2018-09-07 | 2020-10-13 | Intel Corporation | Electronic device including a lateral trace |
JP7211822B2 (ja) * | 2019-01-09 | 2023-01-24 | 株式会社東京精密 | 電子部品のポッティング方法及びそれを用いた電子装置 |
US11948877B2 (en) * | 2020-03-31 | 2024-04-02 | Qualcomm Incorporated | Hybrid package apparatus and method of fabricating |
US11784130B2 (en) * | 2021-08-27 | 2023-10-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and formation method of package with underfill |
Family Cites Families (69)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US1429387A (en) * | 1921-01-22 | 1922-09-19 | Firm Gewerkschaft Hausbach Ii | Flushing hopper for shallow and deep dredgers |
US5352925A (en) * | 1991-03-27 | 1994-10-04 | Kokusai Electric Co., Ltd. | Semiconductor device with electromagnetic shield |
KR930024126A (ko) * | 1992-05-12 | 1993-12-22 | 아키라 기타하라 | 표면실장소자와 그의 반제품 |
JP2001111232A (ja) * | 1999-10-06 | 2001-04-20 | Sony Corp | 電子部品実装多層基板及びその製造方法 |
US6876071B2 (en) * | 2001-06-30 | 2005-04-05 | Texas Instruments Incorporated | Masking layer in substrate cavity |
JP3938742B2 (ja) * | 2002-11-18 | 2007-06-27 | Necエレクトロニクス株式会社 | 電子部品装置及びその製造方法 |
US7187060B2 (en) * | 2003-03-13 | 2007-03-06 | Sanyo Electric Co., Ltd. | Semiconductor device with shield |
JP4614278B2 (ja) * | 2005-05-25 | 2011-01-19 | アルプス電気株式会社 | 電子回路ユニット、及びその製造方法 |
US20070190747A1 (en) * | 2006-01-23 | 2007-08-16 | Tessera Technologies Hungary Kft. | Wafer level packaging to lidded chips |
JP4799385B2 (ja) * | 2006-05-11 | 2011-10-26 | パナソニック株式会社 | 樹脂封止型半導体装置の製造方法およびそのための配線基板 |
US8022433B2 (en) * | 2006-09-06 | 2011-09-20 | Hitachi Metals, Ltd. | Semiconductor sensor device and method for manufacturing same |
JP2009059800A (ja) * | 2007-08-30 | 2009-03-19 | Toshiba Corp | 小型モジュール |
JP5466820B2 (ja) * | 2007-10-18 | 2014-04-09 | ピーエスフォー ルクスコ エスエイアールエル | 半導体基板、及び半導体装置の製造方法 |
US7718901B2 (en) * | 2007-10-24 | 2010-05-18 | Ibiden Co., Ltd. | Electronic parts substrate and method for manufacturing the same |
JP2009117450A (ja) * | 2007-11-02 | 2009-05-28 | Rohm Co Ltd | モジュールおよびその製造方法 |
JP5395360B2 (ja) * | 2008-02-25 | 2014-01-22 | 新光電気工業株式会社 | 電子部品内蔵基板の製造方法 |
JP2009277954A (ja) * | 2008-05-16 | 2009-11-26 | Murata Mfg Co Ltd | 回路モジュールの製造方法及び回路モジュール |
JP2009283835A (ja) * | 2008-05-26 | 2009-12-03 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP5203045B2 (ja) * | 2008-05-28 | 2013-06-05 | 日本特殊陶業株式会社 | 多層配線基板の中間製品、多層配線基板の製造方法 |
WO2010023773A1 (ja) * | 2008-08-29 | 2010-03-04 | イビデン株式会社 | フレックスリジッド配線板及び電子デバイス |
JP2010080699A (ja) * | 2008-09-26 | 2010-04-08 | Panasonic Corp | 高周波モジュールとその製造方法 |
JP2010114434A (ja) * | 2008-10-08 | 2010-05-20 | Ngk Spark Plug Co Ltd | 部品内蔵配線基板及びその製造方法 |
US8921705B2 (en) * | 2008-11-28 | 2014-12-30 | Ibiden Co., Ltd. | Wiring board and fabrication method therefor |
JP2010153466A (ja) * | 2008-12-24 | 2010-07-08 | Elpida Memory Inc | 配線基板 |
JP5289996B2 (ja) * | 2009-02-16 | 2013-09-11 | 日本特殊陶業株式会社 | 補強材付き配線基板 |
JP5261255B2 (ja) * | 2009-03-27 | 2013-08-14 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2011061004A (ja) * | 2009-09-10 | 2011-03-24 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP2011165741A (ja) * | 2010-02-05 | 2011-08-25 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
US8558392B2 (en) * | 2010-05-14 | 2013-10-15 | Stats Chippac, Ltd. | Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant |
US9362196B2 (en) | 2010-07-15 | 2016-06-07 | Kabushiki Kaisha Toshiba | Semiconductor package and mobile device using the same |
JP5467959B2 (ja) * | 2010-07-21 | 2014-04-09 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9337116B2 (en) * | 2010-10-28 | 2016-05-10 | Stats Chippac, Ltd. | Semiconductor device and method of forming stepped interposer for stacking and electrically connecting semiconductor die |
JP2012109437A (ja) * | 2010-11-18 | 2012-06-07 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP2012142536A (ja) * | 2010-12-13 | 2012-07-26 | Elpida Memory Inc | 半導体装置及びその製造方法 |
WO2012137626A1 (ja) * | 2011-04-01 | 2012-10-11 | 株式会社村田製作所 | 部品内蔵樹脂基板およびその製造方法 |
JP2013098410A (ja) * | 2011-11-02 | 2013-05-20 | Ibiden Co Ltd | 多数個取り基板 |
KR101335378B1 (ko) * | 2012-04-12 | 2013-12-03 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그 제작 방법 |
EP2897166A4 (en) * | 2012-09-14 | 2016-06-29 | Renesas Electronics Corp | METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT |
US9668352B2 (en) * | 2013-03-15 | 2017-05-30 | Sumitomo Electric Printed Circuits, Inc. | Method of embedding a pre-assembled unit including a device into a flexible printed circuit and corresponding assembly |
US20150077960A1 (en) * | 2013-09-19 | 2015-03-19 | Murata Manufacturing Co., Ltd. | Low-temperature packaging methodology for electronic devices and other devices |
WO2015064642A1 (ja) * | 2013-10-30 | 2015-05-07 | 京セラ株式会社 | 配線基板およびこれを用いた実装構造体 |
TWI509767B (zh) * | 2013-12-13 | 2015-11-21 | Universal Scient Ind Shanghai | 電子封裝模組及其製造方法 |
US20170194300A1 (en) * | 2015-05-27 | 2017-07-06 | Bridge Semiconductor Corporation | Thermally enhanced semiconductor assembly with three dimensional integration and method of making the same |
WO2015145651A1 (ja) * | 2014-03-27 | 2015-10-01 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
JP2015195272A (ja) * | 2014-03-31 | 2015-11-05 | 新光電気工業株式会社 | 半導体装置及び半導体装置の製造方法 |
KR102245134B1 (ko) * | 2014-04-18 | 2021-04-28 | 삼성전자 주식회사 | 반도체 칩을 구비하는 반도체 패키지 |
JP2015222741A (ja) * | 2014-05-22 | 2015-12-10 | 京セラサーキットソリューションズ株式会社 | 多数個取り配線基板およびその製造方法 |
US9390993B2 (en) * | 2014-08-15 | 2016-07-12 | Broadcom Corporation | Semiconductor border protection sealant |
JP6473595B2 (ja) * | 2014-10-10 | 2019-02-20 | イビデン株式会社 | 多層配線板及びその製造方法 |
US9554469B2 (en) * | 2014-12-05 | 2017-01-24 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Method of fabricating a polymer frame with a rectangular array of cavities |
US20160174365A1 (en) * | 2014-12-15 | 2016-06-16 | Bridge Semiconductor Corporation | Wiring board with dual wiring structures integrated together and method of making the same |
US20180261535A1 (en) * | 2014-12-15 | 2018-09-13 | Bridge Semiconductor Corp. | Method of making wiring board with dual routing circuitries integrated with leadframe |
US10269722B2 (en) * | 2014-12-15 | 2019-04-23 | Bridge Semiconductor Corp. | Wiring board having component integrated with leadframe and method of making the same |
US9947625B2 (en) * | 2014-12-15 | 2018-04-17 | Bridge Semiconductor Corporation | Wiring board with embedded component and integrated stiffener and method of making the same |
US10306777B2 (en) * | 2014-12-15 | 2019-05-28 | Bridge Semiconductor Corporation | Wiring board with dual stiffeners and dual routing circuitries integrated together and method of making the same |
CN105789058A (zh) * | 2015-01-14 | 2016-07-20 | 钰桥半导体股份有限公司 | 中介层嵌置于加强层中的线路板及其制作方法 |
WO2016144039A1 (en) * | 2015-03-06 | 2016-09-15 | Samsung Electronics Co., Ltd. | Circuit element package, manufacturing method thereof, and manufacturing apparatus thereof |
US10177130B2 (en) * | 2015-04-01 | 2019-01-08 | Bridge Semiconductor Corporation | Semiconductor assembly having anti-warping controller and vertical connecting element in stiffener |
KR20160132751A (ko) * | 2015-05-11 | 2016-11-21 | 삼성전기주식회사 | 전자부품 패키지 및 그 제조방법 |
KR102021886B1 (ko) * | 2015-05-15 | 2019-09-18 | 삼성전자주식회사 | 전자부품 패키지 및 패키지 온 패키지 구조 |
US9659878B2 (en) * | 2015-10-20 | 2017-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer level shielding in multi-stacked fan out packages and methods of forming same |
KR101933408B1 (ko) * | 2015-11-10 | 2018-12-28 | 삼성전기 주식회사 | 전자부품 패키지 및 이를 포함하는 전자기기 |
JP2017157739A (ja) * | 2016-03-03 | 2017-09-07 | イビデン株式会社 | 電子部品付き配線板の製造方法 |
US9793222B1 (en) * | 2016-04-21 | 2017-10-17 | Apple Inc. | Substrate designed to provide EMI shielding |
JP6832666B2 (ja) * | 2016-09-30 | 2021-02-24 | 株式会社ディスコ | 半導体パッケージの製造方法 |
US10068854B2 (en) * | 2016-10-24 | 2018-09-04 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device and method of manufacturing the same |
US9953931B1 (en) * | 2016-10-25 | 2018-04-24 | Advanced Semiconductor Engineering, Inc | Semiconductor device package and a method of manufacturing the same |
JP2018074123A (ja) * | 2016-11-04 | 2018-05-10 | 株式会社ディスコ | ウエーハの加工方法 |
JP6815880B2 (ja) * | 2017-01-25 | 2021-01-20 | 株式会社ディスコ | 半導体パッケージの製造方法 |
-
2017
- 2017-01-25 JP JP2017011165A patent/JP6815880B2/ja active Active
-
2018
- 2018-01-18 KR KR1020180006631A patent/KR102334782B1/ko active IP Right Grant
- 2018-01-22 CN CN201810058502.8A patent/CN108364933B/zh active Active
- 2018-01-23 TW TW107102321A patent/TWI735733B/zh active
- 2018-01-24 US US15/879,082 patent/US10431555B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
TWI735733B (zh) | 2021-08-11 |
KR20180087844A (ko) | 2018-08-02 |
KR102334782B1 (ko) | 2021-12-02 |
CN108364933A (zh) | 2018-08-03 |
TW201841267A (zh) | 2018-11-16 |
JP2018120950A (ja) | 2018-08-02 |
US10431555B2 (en) | 2019-10-01 |
CN108364933B (zh) | 2023-09-19 |
US20180211926A1 (en) | 2018-07-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6815880B2 (ja) | 半導体パッケージの製造方法 | |
JP6800745B2 (ja) | 半導体パッケージの製造方法 | |
US10700014B2 (en) | Method of manufacturing semiconductor package | |
US8592958B2 (en) | Chip package and manufacturing method thereof | |
CN108735668B (zh) | 半导体封装的制造方法 | |
TW201838138A (zh) | 半導體裝置及其製造方法 | |
JP6887326B2 (ja) | 半導体パッケージの形成方法 | |
JP7093210B2 (ja) | 板状物の加工方法 | |
JP6955918B2 (ja) | 基板の加工方法 | |
KR102536434B1 (ko) | 반도체 패키지 및 반도체 패키지의 제조 방법 | |
US10211071B2 (en) | IC packaging method and a packaged IC device | |
JP6971093B2 (ja) | マルチブレード、加工方法 | |
JP2019068013A (ja) | パッケージ基板の加工方法、保護テープ | |
JP7075791B2 (ja) | 半導体パッケージの製造方法 | |
JP2019012714A (ja) | 半導体パッケージの製造方法 | |
JP2018067597A (ja) | 回路モジュールの製造方法および成膜装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20191108 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20200813 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20201006 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20201126 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20201208 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20201223 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6815880 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |