JP6808282B2 - インターポーザの製造方法 - Google Patents
インターポーザの製造方法 Download PDFInfo
- Publication number
- JP6808282B2 JP6808282B2 JP2016242236A JP2016242236A JP6808282B2 JP 6808282 B2 JP6808282 B2 JP 6808282B2 JP 2016242236 A JP2016242236 A JP 2016242236A JP 2016242236 A JP2016242236 A JP 2016242236A JP 6808282 B2 JP6808282 B2 JP 6808282B2
- Authority
- JP
- Japan
- Prior art keywords
- glass substrate
- interposer
- laminated body
- cutting groove
- forming step
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 35
- 239000000758 substrate Substances 0.000 claims description 139
- 239000011521 glass Substances 0.000 claims description 108
- 238000005520 cutting process Methods 0.000 claims description 86
- 238000000034 method Methods 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 35
- 239000011148 porous material Substances 0.000 claims description 9
- 238000012986 modification Methods 0.000 description 12
- 230000004048 modification Effects 0.000 description 12
- 238000012545 processing Methods 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 6
- 230000001678 irradiating effect Effects 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000006061 abrasive grain Substances 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 3
- 238000003754 machining Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000001351 cycling effect Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 238000007630 basic procedure Methods 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000005361 soda-lime glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/38—Removing material by boring or cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Optics & Photonics (AREA)
- Plasma & Fusion (AREA)
- Mechanical Engineering (AREA)
- Re-Forming, After-Treatment, Cutting And Transporting Of Glass Products (AREA)
- Laser Beam Processing (AREA)
- Processing Of Stones Or Stones Resemblance Materials (AREA)
Description
3 インターポーザ
11 ガラス基板
11a 第1面(表面)
11b 第2面(裏面)
11c 貫通孔
13 分割予定ライン(ストリート)
15 積層体
15a 露出した面
15b 切削溝
15c レーザー加工溝
17 配線層
19 絶縁層
21 電極
23 改質層
25 シールドトンネル
25a 細孔
25b 非晶質領域
2 切削ブレード
4 レーザー照射ユニット
6 レーザー照射ユニット
L1,L2,L3 レーザービーム
Claims (2)
- 格子状に設定された複数の分割予定ラインによって複数の領域に区画されるガラス基板と、該ガラス基板の第1面又は該第1面とは反対側の第2面に積層され絶縁層と配線層とを含む積層体と、を備える材料基板から複数のインターポーザを製造するインターポーザの製造方法であって、
該分割予定ラインに沿って該積層体の露出した面に切削ブレードを切り込ませ、該ガラス基板に達しない深さの切削溝を該積層体に形成する切削溝形成工程と、
該ガラス基板に対して透過性を有する波長のレーザービームの集光点を該切削溝に沿って該ガラス基板の内部に位置付け改質層を形成する改質層形成工程と、
該ガラス基板に外力を付与して該改質層に沿って該ガラス基板を分割し、複数のインターポーザを製造する分割工程と、を含むことを特徴とするインターポーザの製造方法。 - 格子状に設定された複数の分割予定ラインによって複数の領域に区画されるガラス基板と、該ガラス基板の第1面又は該第1面とは反対側の第2面に積層され絶縁層と配線層とを含む積層体と、を備える材料基板から複数のインターポーザを製造するインターポーザの製造方法であって、
該分割予定ラインに沿って該積層体の露出した面に切削ブレードを切り込ませ、該ガラス基板に達しない深さの切削溝を該積層体に形成する切削溝形成工程と、
該ガラス基板に対して透過性を有する波長のレーザービームの集光点を該切削溝に沿って該ガラス基板の内部に位置付けて、該ガラス基板の厚さ方向に延びる細孔と該細孔を囲む非晶質領域とを有するシールドトンネルを形成するシールドトンネル形成工程と、
該ガラス基板に外力を付与して該シールドトンネルに沿って該ガラス基板を分割し、複数のインターポーザを製造する分割工程と、を含むことを特徴とするインターポーザの製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016242236A JP6808282B2 (ja) | 2016-12-14 | 2016-12-14 | インターポーザの製造方法 |
TW106138540A TWI743244B (zh) | 2016-12-14 | 2017-11-08 | 中介載板的製造方法 |
KR1020170166942A KR20180068862A (ko) | 2016-12-14 | 2017-12-06 | 인터포저의 제조 방법 |
CN201711282902.9A CN108231570A (zh) | 2016-12-14 | 2017-12-07 | 中介层的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016242236A JP6808282B2 (ja) | 2016-12-14 | 2016-12-14 | インターポーザの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2018098379A JP2018098379A (ja) | 2018-06-21 |
JP6808282B2 true JP6808282B2 (ja) | 2021-01-06 |
Family
ID=62633129
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016242236A Active JP6808282B2 (ja) | 2016-12-14 | 2016-12-14 | インターポーザの製造方法 |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP6808282B2 (ja) |
KR (1) | KR20180068862A (ja) |
CN (1) | CN108231570A (ja) |
TW (1) | TWI743244B (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7164411B2 (ja) * | 2018-11-15 | 2022-11-01 | 株式会社ディスコ | 積層体の加工方法 |
JP7164412B2 (ja) * | 2018-11-16 | 2022-11-01 | 株式会社ディスコ | 積層体の加工方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6617681B1 (en) | 1999-06-28 | 2003-09-09 | Intel Corporation | Interposer and method of making same |
JP2005012203A (ja) * | 2003-05-29 | 2005-01-13 | Hamamatsu Photonics Kk | レーザ加工方法 |
JP5352624B2 (ja) * | 2005-11-10 | 2013-11-27 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP5608521B2 (ja) * | 2010-11-26 | 2014-10-15 | 新光電気工業株式会社 | 半導体ウエハの分割方法と半導体チップ及び半導体装置 |
JP6151557B2 (ja) * | 2013-05-13 | 2017-06-21 | 株式会社ディスコ | レーザー加工方法 |
JP6246534B2 (ja) * | 2013-09-11 | 2017-12-13 | 株式会社ディスコ | ウエーハの加工方法 |
JP2015198212A (ja) | 2014-04-03 | 2015-11-09 | 凸版印刷株式会社 | ガラスインターポーザ |
JP2015207580A (ja) * | 2014-04-17 | 2015-11-19 | 凸版印刷株式会社 | 配線基板およびその製造方法 |
-
2016
- 2016-12-14 JP JP2016242236A patent/JP6808282B2/ja active Active
-
2017
- 2017-11-08 TW TW106138540A patent/TWI743244B/zh active
- 2017-12-06 KR KR1020170166942A patent/KR20180068862A/ko not_active IP Right Cessation
- 2017-12-07 CN CN201711282902.9A patent/CN108231570A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
TW201826455A (zh) | 2018-07-16 |
TWI743244B (zh) | 2021-10-21 |
JP2018098379A (ja) | 2018-06-21 |
CN108231570A (zh) | 2018-06-29 |
KR20180068862A (ko) | 2018-06-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6779574B2 (ja) | インターポーザの製造方法 | |
TWI756437B (zh) | 玻璃中介層之製造方法 | |
JP3795040B2 (ja) | 半導体装置の製造方法 | |
KR102349663B1 (ko) | 웨이퍼의 가공 방법 | |
JP2015207604A (ja) | ウェーハの加工方法 | |
TWI824139B (zh) | 層積晶圓之加工方法 | |
JP2013197108A (ja) | ウエーハのレーザー加工方法 | |
JP6808282B2 (ja) | インターポーザの製造方法 | |
JP2011210915A (ja) | 単結晶基板の切断装置、および単結晶基板の切断方法 | |
JP6012185B2 (ja) | 半導体デバイスの製造方法 | |
US20180308711A1 (en) | Workpiece processing method | |
JP5453123B2 (ja) | 切削方法 | |
JP6981800B2 (ja) | 積層型素子の製造方法 | |
JP5969214B2 (ja) | 半導体デバイスの製造方法 | |
JP6925902B2 (ja) | 積層型素子の製造方法 | |
TW201923860A (zh) | 層疊型元件的製造方法 | |
JP7223828B2 (ja) | 積層型素子の製造方法 | |
JP2013157449A (ja) | 半導体デバイスの製造方法 | |
JP6440558B2 (ja) | 被加工物の加工方法 | |
JP2022024591A (ja) | ウェーハ加工方法及びシステム | |
JP2013157455A (ja) | 半導体デバイスの製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20191018 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20200813 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20200818 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20200925 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20201208 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20201208 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6808282 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |