JP6798728B2 - 半導体モジュール - Google Patents
半導体モジュール Download PDFInfo
- Publication number
- JP6798728B2 JP6798728B2 JP2019521921A JP2019521921A JP6798728B2 JP 6798728 B2 JP6798728 B2 JP 6798728B2 JP 2019521921 A JP2019521921 A JP 2019521921A JP 2019521921 A JP2019521921 A JP 2019521921A JP 6798728 B2 JP6798728 B2 JP 6798728B2
- Authority
- JP
- Japan
- Prior art keywords
- ram
- interposer
- semiconductor module
- unit
- pair
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 65
- 230000015654 memory Effects 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 16
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 230000000694 effects Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 241000724291 Tobacco streak virus Species 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/041—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L31/00
- H01L25/042—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L31/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06589—Thermal management, e.g. cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/112—Mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1431—Logic devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Life Sciences & Earth Sciences (AREA)
- Sustainable Development (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
各実施形態に係る半導体モジュールは、例えば、演算装置(以下、論理チップという)と、積層型RAMとをインタポーザ上に配置したSIP(system in a package)である。半導体モジュールは、他のインタポーザ上に配置され、マイクロバンプを用いて電気的に接続される。半導体モジュールは、他のインタポーザから電源を得るとともに、他のインタポーザとの間でデータ送受信が可能な装置である。なお、以下の各実施形態において、MPUを論理チップの一例として説明する。
次に、本発明の第1実施形態に係る半導体モジュール1について、図1〜図5を参照して説明する。
半導体モジュール1は、図1〜図4に示すように、第1インタポーザ10と、MPU20と、一対のRAM部30と、接続部40と、ヒートシンク部50と、を備える。
まず、図5に示すように、第1インタポーザ10から、MPU20に電源W1が供給される。また、第1インタポーザ10から、一方のRAM部30aに電源W2が供給される。一方のRAM部30aに供給された電源W1は、接続部40を介して他方のRAM部30bにも供給される。また、MPU20は、第1インタポーザ10とグラウンド接続される(グラウンドG1)。一対のRAM部30は、第1インタポーザ10とグラウンド接続(グラウンドG2)される。なお、接続部40を介してインタフェースチップ32からMPU20に電源W4とグラウンドG4を供給しても良い。
(1)半導体モジュール1を、MPU20(論理チップ)と、それぞれが積層型RAMモジュールから構成される一対のRAM部30と、MPU20及び一対のRAM部30のそれぞれに電気的に接続される第1インタポーザ10と、MPU20と一対のRAM部30のそれぞれとの間を通信可能に接続する接続部40と、を含んで構成した。そして、一対のRAM部30の一方の一端部を、接続部40を介してMPU20の一端部と積層方向Cで重ねて配置し、一対のRAM部30の他方を、接続部40を介して一方のRAM部30aに重ね合わされるとともに、MPU20の外周のすくなくとも1辺に沿って配置した。これにより、MPU20と一対のRAM部30のそれぞれとを接続部40により直接的に接続可能であるので、MPU20と一対のRAM部30のそれぞれとの間の信号線を短くすることができる。よって、MPU20と一対のRAM部30との間のバンド幅を広くすることができる。また、RAM部30を積層型RAMモジュールで一対に構成することによりRAM部30の容量を容易に増加させることができる。さらに、積層型RAMモジュールを別々に製作でき、単体の積層型RAMモジュールでRAM部30を製作する場合に比べ歩留りを向上できる。
次に、本発明の第2実施形態に係る半導体モジュール1Aについて、図6及び図7を参照して説明する。第2実施形態の説明にあたって、同一構成要件については同一符号を付し、その説明を省略もしくは簡略化する。
第2実施形態に係る半導体モジュール1Aは、図6に示すように、一対のRAM部30のそれぞれが、インタフェースチップ32を対向させて配置される点で第1実施形態と異なる。第2実施形態に係る半導体モジュール1Aは、図7に示すように、一方のRAM部30aのインタフェースチップ32と他方のRAM部30bのそれぞれのインタフェースチップ32が、それぞれのRAM部30のメモリ部31を管理する点で第1実施形態と異なる。
(7)一対のRAM部30のそれぞれを、インタフェースチップ32を対向させて配置した。これにより、一対のRAM部30のそれぞれを別々のインタフェースチップ32で制御することができる。
次に、本発明の第3実施形態に係る半導体モジュール1Bについて、図8及び図9を参照して説明する。第3実施形態の説明にあたって、同一構成要件については同一符号を付し、その説明を省略もしくは簡略化する。
第3実施形態に係る半導体モジュール1Bは、図8に示すように、他方のRAM部30bが、メモリ部31のみで構成されている点で第1及び第2実施形態と異なる。第3実施形態に係る半導体モジュール1Bでは、図9に示すように、第1実施形態と同様に、一方のRAM部30aのインタフェースチップ32が一対のRAM部30の双方を管理する。
(8)他方のRAM部30bを、メモリ部31のみで構成した。これにより、半導体モジュール1Bの歩留まりを向上できるとともに、製作コストを低減できる。
次に、本発明の第4実施形態に係る半導体モジュール1Cについて、図10〜図13を参照して説明する。第4実施形態の説明にあたって、同一構成要件については同一符号を付し、その説明を省略もしくは簡略化する。
第4実施形態に係る半導体モジュール1Cは、図10〜図12に示すように、第2インタポーザ60と、第3インタポーザ又はパッケージ基板80と、ボンディングワイヤ70と、を備える点で第2実施形態と異なる。
第3インタポーザ又はパッケージ基板80は、第1インタポーザ10を載置する。第3インタポーザ又はパッケージ基板80は、第1インタポーザ10とマイクロバンプM1を用いて電気的に接続される。
図13に示すように、第2インタポーザ60には、ボンディングワイヤ70を介して第3インタポーザ又はパッケージ基板80から電源W3が供給される。他方のRAM部30bには、第2インタポーザ60から電源W3が供給される。他方のRAM部30bは、第2インタポーザ60とグラウンド接続(グラウンドG3)される。
(9)半導体モジュール1Cを更に、他方のRAM部30bに載置される第2インタポーザ60と、第1インタポーザ10を載置する第3インタポーザ又はパッケージ基板80と、第2インタポーザ60及び第3インタポーザ又はパッケージ基板80を電気的に接続するボンディングワイヤ70と、を含んで構成した。これにより、一対のRAM部30のそれぞれに別々に電力を供給できるので、電力をRAM部30に安定供給できる。
次に、本発明の第5実施形態に係る半導体モジュール1Dについて、図14を参照して説明する。第5実施形態の説明にあたって、同一構成については同一符号を付し、その説明を省略もしくは簡略化する。
第5実施形態に係る半導体モジュール1Dは、図14に示すように、ボンディングワイヤ70に代えて、導電性の柱状部90を備える点で第5実施形態と異なる。
図14に示すように、第2インタポーザ60には、柱状部90を介して第1インタポーザ10から電源W5が供給される。また、第2インタポーザ60は、第1インタポーザ10とグラウンド接続(グラウンドG5)される。
(10)半導体モジュール1Dを更に、他方のRAM部30bに載置される第2インタポーザ60と、第1インタポーザ10及び第2インタポーザ60を電気的に接続する柱状部90と、を含んで構成した。これにより、一対のRAM部30のそれぞれに別々に電力を供給できるので、電力をRAM部30に安定供給できる。また、柱状部90の他端が他方のRAM部30bに対向する第2インタポーザ60の下面に接続されるので、第2インタポーザ60の下面側に、柱状部90の接続位置と、他方のRAM部30bの接続位置との両者を配置できる。これにより、第2インタポーザ60を貫通させることなく、柱状部90から他方のRAM部30bに電源(電源W3,W5)及びグラウンド(グラウンドG3,G5)を供給できるので、半導体モジュール1Dの製作コストを低下させることができる。
次に、本発明の第6実施形態に係る半導体モジュールについて説明する。第6実施形態の説明にあたって、同一構成要件については同一符号を付し、その説明を省略もしくは簡略化する。
第5実施形態に係る半導体モジュールは、ヒートシンク部50がスペーサ部(図示せず)を備える点で第1〜第5実施形態と異なる。
スペーサ部は、MPU20の上面と、他方のRAM部30bとの上面との間に段差がある場合に、段差を埋める厚さで形成される。スペーサ部は、少なくとも他方のRAM部30b及びMPU20のいずれか一方に隣接する。スペーサ部は、他方のRAM部30b又はMPU20の上面と接触可能なように対向面を平面で形成される。
(11)ヒートシンク部を、少なくとも他方のRAM部30b及びMPU20のいずれか一方に隣接するスペーサ部を含んで構成した。これにより、RAM部及びMPU20の間が面一でない場合であっても、ヒートシンク部を設置することができる。
10 第1インタポーザ
20 MPU
30 一対のRAM部
30a 一方のRAM部
30b 他方のRAM部
31 メモリ部
32 インタフェースチップ
40 接続部
50 ヒートシンク部
60 第2インタポーザ
70 ボンディングワイヤ
80 第3インタポーザ又はパッケージ基板
Claims (10)
- 論理チップと、
それぞれが積層型RAMモジュールから構成される一対のRAM部と、
前記論理チップ及び一対の前記RAM部のそれぞれに電気的に接続される第1インタポーザと、
前記論理チップと一対の前記RAM部のそれぞれとの間を通信可能に接続する接続部と、
を備え、
一方の前記RAM部は、前記第1インタポーザに載置されるとともに、一端部が前記接続部を介して前記論理チップの一端部と積層方向で重なって配置され、
他方の前記RAM部は、前記接続部を介して一方の前記RAM部に重ね合わされるとともに、前記論理チップの外周の少なくとも1辺に沿って配置されることを特徴とする半導体モジュール。 - 一対の前記RAM部のそれぞれは、
メモリ回路が積層されたメモリ部と、
前記メモリ部の一端側に積層されるインタフェースチップと、
を備える請求項1に記載の半導体モジュール。 - 一対の前記RAM部のそれぞれは、前記インタフェースチップを対向させて配置される請求項2に記載の半導体モジュール。
- 一対の前記RAM部のそれぞれは、前記第1インタポーザに対向する面とは逆の面側に前記インタフェースチップが配置される請求項2に記載の半導体モジュール。
- 前記他方のRAM部は、前記メモリ部のみで構成される請求項2に記載の半導体モジュール。
- 前記他方のRAM部に載置される第2インタポーザと、
前記第1インタポーザを載置する第3インタポーザ又はパッケージ基板と、
前記第2インタポーザ及び、前記第3インタポーザ又はパッケージ基板を電気的に接続するボンディングワイヤと、
を更に備える請求項1〜5のいずれかに記載の半導体モジュール。 - 前記他方のRAM部に載置される第2インタポーザと、
前記第1インタポーザ及び前記第2インタポーザを電気的に接続する柱状部と、
を更に備える請求項1〜5のいずれかに記載の半導体モジュール。 - 前記他方のRAM部と前記論理チップとに載置されるヒートシンク部を更に備える請求項1〜7のいずれかに記載の半導体モジュール。
- 前記ヒートシンク部は、少なくとも前記他方のRAM部及び前記論理チップのいずれか一方に隣接するスペーサ部を備える請求項8に記載の半導体モジュール。
- 一対の前記RAM部のそれぞれは、平面視同じ形状及び大きさの積層型RAMモジュールを含む請求項1〜9のいずれかに記載の半導体モジュール。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2017/020686 WO2018220846A1 (ja) | 2017-06-02 | 2017-06-02 | 半導体モジュール |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2020188980A Division JP6993023B2 (ja) | 2020-11-12 | 2020-11-12 | 半導体モジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2018220846A1 JPWO2018220846A1 (ja) | 2019-11-21 |
JP6798728B2 true JP6798728B2 (ja) | 2020-12-09 |
Family
ID=64455312
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2019521921A Active JP6798728B2 (ja) | 2017-06-02 | 2017-06-02 | 半導体モジュール |
Country Status (4)
Country | Link |
---|---|
US (2) | US10741525B2 (ja) |
JP (1) | JP6798728B2 (ja) |
CN (2) | CN110720125B (ja) |
WO (1) | WO2018220846A1 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018220846A1 (ja) * | 2017-06-02 | 2018-12-06 | ウルトラメモリ株式会社 | 半導体モジュール |
US11139270B2 (en) | 2019-03-18 | 2021-10-05 | Kepler Computing Inc. | Artificial intelligence processor with three-dimensional stacked memory |
US11836102B1 (en) | 2019-03-20 | 2023-12-05 | Kepler Computing Inc. | Low latency and high bandwidth artificial intelligence processor |
US11043472B1 (en) | 2019-05-31 | 2021-06-22 | Kepler Compute Inc. | 3D integrated ultra high-bandwidth memory |
US11844223B1 (en) | 2019-05-31 | 2023-12-12 | Kepler Computing Inc. | Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging |
JPWO2022215237A1 (ja) * | 2021-04-08 | 2022-10-13 | ||
US11721685B2 (en) * | 2021-05-26 | 2023-08-08 | Avago Technologies International Sales Pte. Limited | Copper-bonded memory stacks with copper-bonded interconnection memory systems |
US11791233B1 (en) | 2021-08-06 | 2023-10-17 | Kepler Computing Inc. | Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging |
WO2023119450A1 (ja) * | 2021-12-21 | 2023-06-29 | ウルトラメモリ株式会社 | 半導体モジュール及び積層モジュール |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5790384A (en) * | 1997-06-26 | 1998-08-04 | International Business Machines Corporation | Bare die multiple dies for direct attach |
EP1840964A1 (en) * | 2006-03-31 | 2007-10-03 | Irvine Sensors Corp. | Semiconductor device with protected access |
KR100855855B1 (ko) * | 2006-10-04 | 2008-09-01 | 주식회사 하이닉스반도체 | 비휘발성 메모리 소자 및 그 제조방법 |
JP5137179B2 (ja) | 2007-03-30 | 2013-02-06 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8399973B2 (en) | 2007-12-20 | 2013-03-19 | Mosaid Technologies Incorporated | Data storage and stackable configurations |
JP5331427B2 (ja) | 2008-09-29 | 2013-10-30 | 株式会社日立製作所 | 半導体装置 |
US20100244276A1 (en) | 2009-03-25 | 2010-09-30 | Lsi Corporation | Three-dimensional electronics package |
US9466561B2 (en) * | 2009-08-06 | 2016-10-11 | Rambus Inc. | Packaged semiconductor device for high performance memory and logic |
US8304881B1 (en) * | 2011-04-21 | 2012-11-06 | Tessera, Inc. | Flip-chip, face-up and face-down wirebond combination package |
US8841765B2 (en) | 2011-04-22 | 2014-09-23 | Tessera, Inc. | Multi-chip module with stacked face-down connected dies |
US9449941B2 (en) * | 2011-07-07 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Connecting function chips to a package to form package-on-package |
US8502390B2 (en) * | 2011-07-12 | 2013-08-06 | Tessera, Inc. | De-skewed multi-die packages |
US8976610B2 (en) * | 2012-10-11 | 2015-03-10 | Everspin Technologies, Inc. | Memory device with timing overlap mode |
US9087765B2 (en) * | 2013-03-15 | 2015-07-21 | Qualcomm Incorporated | System-in-package with interposer pitch adapter |
US9263370B2 (en) * | 2013-09-27 | 2016-02-16 | Qualcomm Mems Technologies, Inc. | Semiconductor device with via bar |
US9379074B2 (en) | 2013-11-22 | 2016-06-28 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
US9287248B2 (en) | 2013-12-12 | 2016-03-15 | Intel Corporation | Embedded memory and power management subpackage |
US20150255411A1 (en) * | 2014-03-05 | 2015-09-10 | Omkar G. Karhade | Die-to-die bonding and associated package configurations |
KR20150120570A (ko) * | 2014-04-17 | 2015-10-28 | 에스케이하이닉스 주식회사 | 반도체 패키지 및 그 제조 방법 |
US20150364422A1 (en) * | 2014-06-13 | 2015-12-17 | Apple Inc. | Fan out wafer level package using silicon bridge |
US9640521B2 (en) * | 2014-09-30 | 2017-05-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-die package with bridge layer and method for making the same |
US9768145B2 (en) | 2015-08-31 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming multi-die package structures including redistribution layers |
US9761533B2 (en) * | 2015-10-16 | 2017-09-12 | Xilinx, Inc. | Interposer-less stack die interconnect |
KR102413441B1 (ko) * | 2015-11-12 | 2022-06-28 | 삼성전자주식회사 | 반도체 패키지 |
US9553071B1 (en) | 2016-01-11 | 2017-01-24 | Invensas Corporation | Multi-chip package with interconnects extending through logic chip |
WO2017160284A1 (en) * | 2016-03-16 | 2017-09-21 | Intel Corporation | Stairstep interposers with integrated shielding for electronics packages |
US11151042B2 (en) * | 2016-09-27 | 2021-10-19 | Integrated Silicon Solution, (Cayman) Inc. | Error cache segmentation for power reduction |
US10109616B2 (en) * | 2016-12-22 | 2018-10-23 | Intel Corporation | High bandwidth, low profile multi-die package |
WO2018220846A1 (ja) * | 2017-06-02 | 2018-12-06 | ウルトラメモリ株式会社 | 半導体モジュール |
-
2017
- 2017-06-02 WO PCT/JP2017/020686 patent/WO2018220846A1/ja active Application Filing
- 2017-06-02 CN CN201780091509.3A patent/CN110720125B/zh active Active
- 2017-06-02 CN CN202110068074.9A patent/CN112802835A/zh active Pending
- 2017-06-02 JP JP2019521921A patent/JP6798728B2/ja active Active
- 2017-06-02 US US16/618,765 patent/US10741525B2/en active Active
-
2020
- 2020-06-26 US US16/913,524 patent/US11410970B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US11410970B2 (en) | 2022-08-09 |
US20200135696A1 (en) | 2020-04-30 |
JPWO2018220846A1 (ja) | 2019-11-21 |
US10741525B2 (en) | 2020-08-11 |
CN110720125A (zh) | 2020-01-21 |
CN110720125B (zh) | 2021-02-05 |
US20200328184A1 (en) | 2020-10-15 |
CN112802835A (zh) | 2021-05-14 |
WO2018220846A1 (ja) | 2018-12-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6798728B2 (ja) | 半導体モジュール | |
KR101639989B1 (ko) | 윈도우 인터포저를 갖는 3d 집적 회로 패키지 | |
JP6339222B2 (ja) | 改良された熱性能を有する積層半導体ダイアセンブリならびに関連するシステムおよび方法 | |
JP5066302B2 (ja) | 半導体装置 | |
US8680652B2 (en) | Stack package | |
WO2010035376A1 (ja) | 半導体装置の製造方法 | |
JP2005217205A (ja) | チップ積層構成の3次元半導体装置及び該装置に用いられるスペーサチップ | |
US20120049361A1 (en) | Semiconductor integrated circuit | |
JP7210051B2 (ja) | 半導体モジュール、半導体部材、及びその製造方法 | |
JP7033332B2 (ja) | 半導体モジュール | |
JP7210066B2 (ja) | 半導体モジュール、その製造方法、及び半導体モジュールの実装体 | |
US9853015B1 (en) | Semiconductor device with stacking chips | |
JP7222564B2 (ja) | 半導体モジュール及びその製造方法 | |
US20120168933A1 (en) | Wafer level molding structure | |
US8304879B2 (en) | Spiral staircase shaped stacked semiconductor package and method for manufacturing the same | |
JP6993023B2 (ja) | 半導体モジュール | |
JP2014222728A (ja) | 半導体パッケージ | |
WO2023119450A1 (ja) | 半導体モジュール及び積層モジュール | |
WO2023084737A1 (ja) | モジュール及びその製造方法 | |
KR100851108B1 (ko) | 웨이퍼 레벨 시스템 인 패키지 및 그 제조 방법 | |
WO2023223472A1 (ja) | 半導体モジュール及びその製造方法 | |
US20240030209A1 (en) | Partitioned overlapped copper-bonded interposers |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20190808 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20201013 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20201112 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6798728 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |