JP6795032B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6795032B2 JP6795032B2 JP2018520742A JP2018520742A JP6795032B2 JP 6795032 B2 JP6795032 B2 JP 6795032B2 JP 2018520742 A JP2018520742 A JP 2018520742A JP 2018520742 A JP2018520742 A JP 2018520742A JP 6795032 B2 JP6795032 B2 JP 6795032B2
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Description
本発明にかかる半導体装置は、ワイドバンドギャップ半導体を用いて構成される。実施の形態1においては、ワイドバンドギャップ半導体として例えば炭化珪素(SiC)を用いて作製された炭化珪素半導体装置について説明する。図1Aは、実施の形態1にかかる半導体装置の平面レイアウトの一例を示す平面図である。図1Bは、図1Aの要部の平面レイアウトを示す平面図である。図1Aに示すように、実施の形態1にかかる半導体装置は、炭化珪素からなる同一の半導体基体(以下、炭化珪素基体(半導体基板(半導体チップ))とする)100に、メイン半導体素子10と、このメイン半導体素子10を保護・制御する複数の回路部と、を備える。
(図2)。
次に、実施の形態2にかかる半導体装置の構造について説明する。図4は、実施の形態2にかかる半導体装置の構造を示す断面図である。実施の形態2にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、ゲートパッド19、アノードパッド44およびカソードパッド45の直下にMOSゲート構造部50aを構成する半導体領域を配置せずに無効領域とした点である。この場合、電流センス部30のMOSゲート構造部50bの周囲を囲むように、メイン半導体素子10のMOSゲート構造部50aが配置される。
次に、実施の形態3にかかる半導体装置の構造について説明する。図5は、実施の形態3にかかる半導体装置の構造を示す断面図である。実施の形態3にかかる半導体装置が実施の形態2にかかる半導体装置と異なる点は、分離部60を構成するトレンチ61の内部を絶縁膜62のみで埋め込んだ点である。トレンチ61を絶縁膜62で完全に埋め込むことができれば、トレント61内にポリシリコンを埋め込まなくても分離部60としての機能が得られる。例えば、CVD法等の堆積法を用いることにより、トレンチ61の内部を絶縁膜62で完全に埋め込むことができる。このため、トレンチ61の内部にポリシリコン層を埋め込まなくても、トレンチ61の内部を完全に埋め込むことができる。
2 n-型炭化珪素層
3 p型ベース領域
4 n+型ソース領域
5 p+型コンタクト領域
6 n型JFET領域
7 ゲート絶縁膜
8 ゲート電極
9 層間絶縁膜
10 メイン半導体素子
11 酸化膜
12 ソースパッド
13 めっき膜
14 半田膜
15 端子ピン
16,17 保護膜
18 裏面電極
19 ゲートパッド
20 ゲートパッド部
30 電流センス部
31 OCパッド
40 温度センス部
41 p型ポリシリコン層
42 n型ポリシリコン層
43 ダイオード
44 アノードパッド
45 カソードパッド
50a,50b MOSゲート構造部
60 分離部
61 トレンチ
62 絶縁膜
63 ポリシリコン層
100 炭化珪素基体
101 活性領域
102 エッジ終端領域
X,Y 基体おもて面に平行な方向
Z 深さ方向
Claims (6)
- シリコンよりもバンドギャップの広い半導体からなる第1導電型の半導体基板と、
前記半導体基板の表面に設けられたプレーナゲート構造の半導体素子と、
前記半導体基板の表面において、前記半導体素子に囲まれるように設けられたプレーナゲート構造の電流センス部と、
前記半導体基板の表面において、前記半導体素子と前記電流センス部との間に設けられた分離部と、
を備え、
前記分離部は、
前記半導体基板のおもて面に設けられたトレンチと、
前記トレンチの内部に設けられた絶縁膜と、
前記トレンチの内部に前記絶縁膜を介して埋め込まれた導電体層と、を有し、
前記半導体素子は、
前記半導体基板のおもて面に設けられた第2導電型の第1半導体領域と、
前記第1半導体領域の内部に選択的に設けられた第1導電型の第2半導体領域と、
前記第1半導体領域および前記第2半導体領域に接して設けられた第1ゲート絶縁膜と、
前記第1ゲート絶縁膜の、前記第1半導体領域と反対側の表面に設けられた第1ゲート電極と、
前記第1半導体領域および前記第2半導体領域に接する第1電極と、
前記半導体基板の裏面に設けられた第2電極と、を有し、
前記半導体基板は、
前記第2電極に接する第1導電型の第3半導体領域と、
前記半導体基板の、前記第1半導体領域および前記第3半導体領域以外の部分であり、前記第3半導体領域よりも不純物濃度の低い第1導電型の第4半導体領域と、からなり、
前記電流センス部は、
前記半導体基板のおもて面に設けられた第2導電型の第5半導体領域と、
前記第5半導体領域の内部に選択的に設けられた第1導電型の第6半導体領域と、
前記第5半導体領域および前記第6半導体領域に接して設けられた第2ゲート絶縁膜と、
前記第2ゲート絶縁膜の前記第5半導体領域と反対側の表面に設けられ、前記第1ゲート電極と電気的に接続された第2ゲート電極と、
前記第5半導体領域および前記第6半導体領域に接する第3電極と、
前記第2電極と、を有し、
前記第1ゲート電極と前記第2ゲート電極とはつながっており、かつ前記分離部を覆い、
前記トレンチの深さは、前記第3半導体領域と前記第4半導体領域との界面までの深さ以上で、かつ前記第3半導体領域と前記第2電極との界面までの深さよりも浅く、
前記トレンチの短手方向における前記導電体層の幅は、前記第1ゲート電極と前記第2ゲート電極とがつながった部分のゲート電極の厚さよりも厚いことを特徴とする半導体装置。 - 前記第5半導体領域の不純物濃度および底面の深さは、それぞれ前記第1半導体領域の不純物濃度および底面の深さと同じであり、
前記第6半導体領域の不純物濃度および底面の深さは、それぞれ前記第2半導体領域の不純物濃度および底面の深さと同じであり、
前記第2ゲート絶縁膜は前記第1ゲート絶縁膜と同じ材料であり、かつ同じ厚さであることを特徴とする請求項1に記載の半導体装置。 - 前記半導体基板のおもて面に所定の平面レイアウトに配置された複数の電極パッドをさらに備え、
前記第1電極および前記第3電極は、それぞれ異なる前記電極パッドに電気的に接続されていることを特徴とする請求項1〜2のいずれか一つに記載の半導体装置。 - 前記第5半導体領域および前記第6半導体領域は、前記電流センス部に電気的に接続された前記電極パッドに深さ方向に対向することを特徴とする請求項3に記載の半導体装置。
- 前記電極パッドの電位を外部に取り出す端子ピンを、すべての前記電極パッド上にそれぞれめっき膜を介して半田接合したことを特徴とする請求項4に記載の半導体装置。
- シリコンよりもバンドギャップの広い半導体は、炭化珪素であることを特徴とする請求項1〜5のいずれか一つに記載の半導体装置。
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