JP6790372B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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Description
しかしながら、半導体装置では、主回路配線パターンの厚さを大きくすると、当該主回路配線パターンの形成のエッチングのため、また、沿面距離を要することから主回路配線パターン間にはある程度の幅を設ける必要がある。このため、結果として、半導体装置の大型化を招いてしまう。
実施の形態の半導体装置について、図1及び図2を用いて説明する。
図1は、実施の形態の半導体装置の断面図であり、図2は、実施の形態の半導体装置の上面図である。
半導体装置100は、セラミックス等で構成される絶縁板111と、絶縁板111のおもて面に形成され、導電性の回路パターン112a〜112dを含む回路板112とを有する積層基板110と、絶縁板111の裏面に形成された、アルミニウム等の金属で構成された放熱板120とを有する。
半導体装置100は、このような構成を成している。
なお、図3は、図4における一点鎖線X−Xにおける断面図である。また、図4では、図3に関する構成に符号を付している。
ケース560が積層基板510の外周縁に取り付けられて、積層基板510と、半導体素子540と、後述するワイヤ571,572を内部に収納する。
ワイヤ571が、半導体素子540とリードフレーム552とを電気的に接続し、ワイヤ572が、リードフレーム551と回路パターン512cとを電気的に接続している。
図5及び図6は、実施の形態の半導体装置の製造方法を説明するための図である。
次いで、積層基板110の回路板112の回路パターン112a,112bの所定の領域上に、絶縁性を備える、例えば、エポキシ樹脂等で構成される絶縁層131,132をそれぞれ塗布する。絶縁層131,132はディスペンサー等を用いて塗布してもよく、スクリーン印刷を用いて塗布してもよい。
なお、この場合、はんだ141,142に代わって、導電性接着剤を用いることも可能である。
次いで、半導体素子180を、リードフレーム151の回路パターン112c上の領域にはんだ170を介して配置する。なお、はんだ170の融点は、はんだ141,142の融点よりも低いものを用いる。この場合、例えば、はんだ141,142は、錫−アンチモン系が、はんだ170は、錫−銀系がそれぞれ用いられる。そして、はんだ141,142の融点よりも低い温度で加熱して、はんだ170を溶融させた後に凝固させる。これにより、半導体素子180がはんだ170を介してリードフレーム151の回路パターン112c上の領域に接続する。
次いで、ケース160内に封止樹脂200を充填して、ケース160内の積層基板110、リードフレーム151,152、半導体素子180、ワイヤ190を封止する。
また、このような半導体装置100の製造方法としては、図5(B)の後、例えば、図7で示される工程を行うことも可能である。
リードフレーム151,152が予め取り付けられたケース160を用意する。リードフレーム151の所定領域にはんだ170を介して半導体素子180を配置する。そして、所定の温度で加熱して、はんだ170を溶融させた後に凝固させる。これにより、リードフレーム151の一端部と半導体素子180とが接続する(図7(A))。
次いで、ケース160内に封止樹脂200を充填して、ケース160内の積層基板110、リードフレーム151,152、半導体素子180、ワイヤ190を封止する。
図3及び図4の半導体装置500では、半導体素子540の裏面電極と、リードフレーム551とをワイヤ572で電気的に接続するようにしている。一方、半導体装置100では、半導体素子180の裏面電極と、リードフレーム151とが直接電気的に接続されている。このため、半導体装置100では、半導体装置500と比べてワイヤボンディング工程を減らすことができ、製造コストが削減される。
110 積層基板
111 絶縁板
112 回路板
112a,112b,112c,112d 回路パターン
120 放熱板
131,132 絶縁層
133 隙間
141,142,170 はんだ
151,152 リードフレーム
160 ケース
180 半導体素子
190 ワイヤ
200 封止樹脂
Claims (7)
- 絶縁板と、前記絶縁板の主面に設けられた、第1回路パターン及び第2回路パターンを含む回路板とを有する積層基板と、
前記積層基板の外周縁に設けられた、前記外周縁を取り囲むケースと、
他方が前記第1回路パターンに接続され、一方が前記ケースから外部に設けられ、前記第2回路パターン上を前記第2回路パターンに対して間隙を空けて通過する第1リードフレームと、
前記第2回路パターンを埋設して、前記第2回路パターンと前記第1リードフレームとの前記間隙に設けられた絶縁層と、
前記ケース内の前記第1リードフレーム上に設けられた半導体素子と、
を有する半導体装置。 - 前記半導体素子は、
前記第1リードフレームの前記第1回路パターン上に対する領域に設けられている、
請求項1記載の半導体装置。 - 前記絶縁層と、前記第1回路パターンの側部との間に隙間が設けられている、
請求項1記載の半導体装置。 - 前記第1リードフレームは、前記第1回路パターンよりも厚い、
請求項1乃至3のいずれかに記載の半導体装置。 - 前記回路板に含まれて、前記絶縁板の主面に設けられ、前記第1回路パターンを挟んで前記第2回路パターンの反対側に配置された第3回路パターンと、
前記第3回路パターンに他方が接続され、一方が前記ケースから外部に設けられた第2リードフレームと、
前記半導体素子と、前記第2リードフレームの前記第3回路パターン上に対する領域とを接続するワイヤと、
を有する請求項1乃至4のいずれかに記載の半導体装置。 - 前記第2リードフレームは、前記第3回路パターンよりも厚い、
請求項5記載の半導体装置。 - 前記第2リードフレームと前記第3回路パターンは、はんだまたは導電性接着剤によって接続されている、
請求項5記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016020743A JP6790372B2 (ja) | 2016-02-05 | 2016-02-05 | 半導体装置 |
CN201611232698.5A CN107046009B (zh) | 2016-02-05 | 2016-12-28 | 半导体装置 |
US15/397,692 US10461024B2 (en) | 2016-02-05 | 2017-01-03 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2016020743A JP6790372B2 (ja) | 2016-02-05 | 2016-02-05 | 半導体装置 |
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AU2018305075A1 (en) | 2017-07-18 | 2019-11-14 | Komatsu Ltd. | Parameter identifying device, simulation device, and parameter identifying method |
WO2019235097A1 (ja) * | 2018-06-06 | 2019-12-12 | 富士電機株式会社 | 半導体装置 |
JP7247574B2 (ja) * | 2018-12-19 | 2023-03-29 | 富士電機株式会社 | 半導体装置 |
JP7338204B2 (ja) * | 2019-04-01 | 2023-09-05 | 富士電機株式会社 | 半導体装置 |
JP7494521B2 (ja) * | 2020-03-30 | 2024-06-04 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
JP2022037739A (ja) | 2020-08-25 | 2022-03-09 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
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US5559374A (en) * | 1993-03-25 | 1996-09-24 | Sanyo Electric Co., Ltd. | Hybrid integrated circuit |
JP3429921B2 (ja) * | 1995-10-26 | 2003-07-28 | 三菱電機株式会社 | 半導体装置 |
CN100440500C (zh) * | 2003-03-11 | 2008-12-03 | 古河电气工业株式会社 | 印刷配线基板、其制造方法、引线框封装件以及光模块 |
JP2005064479A (ja) * | 2003-07-31 | 2005-03-10 | Sanyo Electric Co Ltd | 回路モジュール |
US7440286B2 (en) * | 2005-04-21 | 2008-10-21 | Super Talent Electronics, Inc. | Extended USB dual-personality card reader |
KR20110124372A (ko) | 2004-04-05 | 2011-11-16 | 미쓰비시 마테리알 가부시키가이샤 | Al/AlN 접합체, 전력 모듈용 기판 및 전력 모듈, 그리고 Al/AlN 접합체의 제조 방법 |
JP4492257B2 (ja) | 2004-08-26 | 2010-06-30 | 富士電機システムズ株式会社 | 半導体モジュールおよびその製造方法 |
KR20080031446A (ko) * | 2005-08-31 | 2008-04-08 | 산요덴키가부시키가이샤 | 회로 장치 및 그 제조 방법 |
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KR101489325B1 (ko) * | 2007-03-12 | 2015-02-06 | 페어차일드코리아반도체 주식회사 | 플립-칩 방식의 적층형 파워 모듈 및 그 파워 모듈의제조방법 |
JP4934559B2 (ja) * | 2007-09-27 | 2012-05-16 | オンセミコンダクター・トレーディング・リミテッド | 回路装置およびその製造方法 |
JP5749468B2 (ja) * | 2010-09-24 | 2015-07-15 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 回路装置およびその製造方法 |
JP2012209469A (ja) | 2011-03-30 | 2012-10-25 | Mitsubishi Electric Corp | 電力用半導体装置 |
JP5682511B2 (ja) * | 2011-08-31 | 2015-03-11 | サンケン電気株式会社 | 半導体モジュール |
JP2013138087A (ja) | 2011-12-28 | 2013-07-11 | Sanken Electric Co Ltd | 半導体モジュール及びその製造方法 |
JP2013258321A (ja) | 2012-06-13 | 2013-12-26 | Fuji Electric Co Ltd | 半導体装置 |
CN104465603A (zh) * | 2013-09-23 | 2015-03-25 | 台达电子企业管理(上海)有限公司 | 功率模块 |
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