CN107046009B - 半导体装置 - Google Patents
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Abstract
本发明的半导体装置能抑制大型化,并确保可允许来自半导体元件的发热的热容量。半导体装置(100)中,引线框架(151)的一端部经由焊料(141)连接到电路图案(112c),另一端部从壳体(160)向外侧延伸。同样,引线框架(152)的一端部经由焊料(142)连接到电路图案(112d),另一端部从壳体(160)向外侧延伸。此时,被引线框架(151)覆盖的电路图案(112a、112b)分别埋设在绝缘层(131、132)中。另外,半导体元件(180)隔着焊料(170)设置在引线框架(151)的电路图案(112c)上方的区域。引线(190)将半导体元件(180)与引线框架(152)的电路图案(112d)上方的区域电连接。
Description
技术领域
本发明涉及半导体装置。
背景技术
半导体装置包含功率半导体元件,用作功率转换装置或开关装置。例如,半导体装置连接有包含IGBT(Insulated Gate Bipolar Transistor:绝缘栅双极晶体管)、MOSFET(Metal Oxide Semiconductor Field Effect Transistor:金属氧化物半导体场效应晶体管)等的半导体元件,能起到开关装置的作用。
这种半导体装置中,具有:主电路基板,该主电路基板具备绝缘层,该绝缘层的正面形成有主电路布线图案,背面形成有金属板;以及半导体元件,该半导体元件隔着焊料设置在主电路布线图案上(例如参照专利文献1)。半导体元件所产生的热量从金属板释放。
此外,半导体装置中,为了充分确保来自半导体元件的发热,优选增大主电路布线图案的厚度,来增加能允许的热容量。
然而,半导体装置中,若增大主电路布线图案的厚度,则由于形成该主电路布线图案的蚀刻、以及需要爬电距离,从而需要在主电路布线图案之间设置一定程度的宽度。因此,其结果会导致半导体装置的大型化。
现有技术文献
专利文献
专利文献1:日本专利特开2013-258321号公报
发明内容
发明所要解决的技术问题
半导体装置中,若为了抑制大型化而例如限制主电路布线图案的厚度,则如上所述,主电路布线图案的可允许半导体元件发热的热容量也会受到限制。因此,半导体装置存在如下问题:若使半导体元件工作,则温度会立即升高并会超过工作温度范围,可能会产生故障、误动作。
本发明鉴于上述情况而完成,其目的在于提供一种能抑制大型化并能确保可允许来自半导体元件的发热的热容量的半导体装置。
解决技术问题所采用的技术方案
根据本发明的一个观点,提供一种半导体装置,包括:层叠基板,该层叠基板具有绝缘板以及设置在所述绝缘板的主面且包含第一电路图案的电路板;壳体,该壳体设置于所述层叠基板的外周缘并包围所述外周缘;第一引线框架,该第一引线框架的一侧从所述壳体向外部设置,另一侧与所述第一电路图案相连;以及半导体元件,该半导体元件设置在所述壳体内的所述第一引线框架上。
发明效果
根据本发明所揭示的技术,能抑制大型化并抑制半导体装置的可靠性降低。
附图说明
图1是实施方式的半导体装置的剖视图。
图2是实施方式的半导体装置的俯视图。
图3是参考例的半导体装置的剖视图。
图4是参考例的半导体装置的俯视图。
图5是用于说明实施方式的半导体装置的制造方法的图(其一)。
图6是用于说明实施方式的半导体装置的制造方法的图(其二)。
图7是用于说明实施方式的半导体装置的其它制造方法的图。
具体实施方式
下面,使用附图对实施方式进行说明。
利用图1和图2对实施方式的半导体装置进行说明。
图1是实施方式的半导体装置的剖视图,图2是实施方式的半导体装置的俯视图。
另外,图1是图2中单点划线X-X处的剖视图。图2中,对与图1有关的结构标注了标号。
半导体装置100具有:层叠基板110,该层叠基板110具有由陶瓷等构成的绝缘板111以及形成在绝缘板111的正面且包含导电性的电路图案112a~112d的电路板112;以及形成在绝缘板111背面且由铝等金属构成的散热板120。
引线框架151的一端部经由焊料141连接到电路板112的电路图案112c上,引线框架151的另一端部从后述的壳体160与绝缘板111的正面平行地向外侧延伸。同样,引线框架152的一端部经由焊料142连接到电路板112的电路图案112d上,引线框架152的另一端部从后述的壳体160与绝缘板111的正面平行地向外侧延伸。由于引线框架152的一端经由焊料142连接到电路图案112d上,因此容易将从半导体元件180传递到引线190的热量释放到电路基板112的背面。
由具有绝缘性的树脂构成的绝缘层131、132分别埋设有电路板112中的、引线框架151下部的绝缘板111上的电路图案112a、112b。此外,上述绝缘层131、132如图2(由单点划线包围的斜线部)所示,仅埋设了电路图案112a、112b的被引线框架151覆盖的部位。因此,电路图案112a、112b与引线框架151保持了绝缘性。另外,绝缘层131、132之间也可用树脂埋设。
此外,假设绝缘层132与电路图案112c或焊料141中任一方的表面接触,则半导体元件180的发热的传导路径被堵塞,热传导性会下降。因此,优选设置间隙133,以使绝缘层132不与电路图案112c或焊料141的任一方的表面接触。
半导体元件180隔着焊料170设置在引线框架151的电路图案112c上方的区域。此外,半导体元件180通过引线190与引线框架152电连接。
壳体160在内部收纳层叠基板110、引线框架151、152、半导体元件180以及引线190,并设置在层叠基板110的外周缘。并且,密封树脂200填充在壳体160内,以将壳体160内的层叠基板110、引线框架151、152、半导体元件180、引线190密封。
另外,对于间隙133,与空洞状态相比,填充密封树脂200更有利于热传导,因此优选在间隙133内填充密封树脂200。
半导体装置100构成这种结构。
这里,作为针对实施方式的半导体装置100的参考例,利用图3和图4对引线框架不与电路图案相连来安装于壳体、且半导体元件设置在电路图案上的半导体装置进行说明。
图3是参考例的半导体装置的剖视图,图4是参考例的半导体装置的俯视图。
另外,图3是图4中单点划线X-X处的剖视图。图4中,对与图3有关的结构标注了标号。
半导体装置500具有:层叠基板510,该层叠基板510具有由陶瓷等构成的绝缘板511以及形成在绝缘板511的正面且包含导电性的电路图案512a~512c的电路板512;以及形成在绝缘板511背面且由铝等金属构成的散热板520。
半导体元件540经由焊料530设置在电路板512的电路图案512c上。
壳体560安装于层叠基板510d的外周缘,并在内部收纳层叠基板510、半导体元件540以及后述的引线571、572。
引线框架551、552的一端部配置在壳体560上,另一端部向壳体560的外部延伸。
引线571将半导体元件540与引线框架552电连接,引线572将引线框架551与电路图案512c电连接。
密封树脂580填充在壳体560内,以将层叠基板510、半导体元件540、引线框架551、552(的一端部)以及引线571、572密封。
这种半导体装置500中,半导体元件540工作时的发热通过焊料530传导到电路图案512c。并且,该发热被保持在电路图案512c上。
半导体装置500中,为了抑制大型化,使其厚度减薄。优选使例如电路板512的电路图案512a~512c的厚度减薄。若将电路图案512a~512c的厚度减薄,则可允许来自半导体元件540的发热的热容量会减少。因此,半导体装置500中,若半导体元件540工作,则温度会立即升高并会超过工作温度范围,可能会产生故障、误动作。
为此,实施方式的半导体装置100具有:层叠基板110,该层叠基板110具有绝缘板111以及形成在绝缘板111的正面并由电路图案112a~112d构成的电路板112;以及散热板120,该散热板120形成在绝缘板111的背面,层叠基板110的外周缘上安装有壳体160。半导体装置100中,引线框架151的一端部经由焊料141连接到电路图案112c,另一端部从壳体160向外侧延伸。同样,引线框架152的一端部经由焊料142连接到电路图案112d,另一端部从壳体160向外侧延伸。此时,被引线框架151覆盖的电路图案112a、112b分别埋设在绝缘层131、132中。另外,半导体元件180隔着焊料170设置在引线框架151的电路图案112c上方的区域。引线190将半导体元件180与引线框架152的电路图案112d上方的区域电连接。
这种半导体装置100中,半导体元件180的发热在焊料170、引线框架151、焊料141、电路图案112c中传导。特别是由于引线框架151比电路图案112c厚,因此例如与图3和图4的半导体装置500的情况相比,允许从半导体元件180发热的热容量增加。因此,半导体装置100能充分确保可允许半导体元件180发热的热容量。因此,半导体装置100中,即使半导体元件180工作,温度也不会立即上升,温度控制在工作温度范围内,故障、误动作的产生得到抑制,从而能防止半导体装置100的可靠性降低。
将半导体元件180与引线框架152的电路图案112d上方的区域连接的引线190也与上述相同。即,若半导体元件180的发热在引线190中传导,则会在引线框152、焊料142、电路图案112d中传导。在该情况下,半导体装置100也能充分确保可允许半导体元件180发热的热容量。
此外,半导体装置100中,使引线框架151的一端部与层叠基板110的电路图案112c相连,另一端部向壳体160的外侧延伸,此外,使引线框架152的一端部与层叠基板110的电路图案112d相连,另一端部向壳体160的外侧延伸。因此,半导体装置100与图3和图4的半导体装置500的情况相比,能减小俯视时的面积。例如,图3所示的半导体装置500的宽度为40mm~50mm左右。另一方面,图1所示的半导体装置100的宽度为25mm~35mm左右,比半导体装置500小。
接着,使用图5和图6对这种半导体装置100的制造方法进行说明。
图5和图6是用于说明实施方式的半导体装置的制造方法的图。
首先,在绝缘板111上形成金属板。将该金属板蚀刻成所期望的图案,在绝缘板111上形成由电路图案112a~112d构成的电路板112,从而构成层叠基板110。
接着,在层叠基板110(绝缘板111)的背面形成由铝等构成的散热板120(图5(A))。
接着,在层叠基板110的电路板112的电路图案112a、112b的规定区域上分别涂布具有绝缘性的例如由环氧树脂等构成的绝缘层131、132。绝缘层131、132也可以利用点胶机等涂布,也可以利用丝网印刷涂布。
接着,在层叠基板110的电路板112的电路图案112c、112d上分别涂布焊料141、142(图5(B))。
另外,在该情况下,也能使用导电性粘接剂来代替焊料141、142。
接着,准备通过嵌入成形而预先安装有引线框架151、152的壳体160。将这种壳体160安装到层叠基板110的外周缘,并将引线框架151的一端部配置在焊料141上,将引线框架152的一端部配置在焊料142上。然后在规定的温度下加热,使焊料141、142熔融然后使其凝固。由此,引线框架151的一端部与焊料141相连,引线框架152的一端部与焊料142相连(图6(A))。
另外,壳体160经由粘接剂安装于层叠基板110。
接着,将半导体元件180隔着焊料170配置在引线框架151的电路图案112c上方的区域。另外,焊料170使用熔点低于焊料141、142的材料。该情况下,例如焊料141、142使用锡-锑类,焊料170使用锡-银类。并且,在比焊料141、142的熔点低的温度下进行加热,来使焊料170熔融,然后使其凝固。由此,半导体元件180经由焊料170与引线框架151的电路图案112c上方的区域相连。
接着,利用引线190将半导体元件180与引线框架152的电路图案112d上方的区域电连接(图6(B))。
接着,在壳体160内填充密封树脂200,以将壳体160内的层叠基板110、引线框架151、152、半导体元件180、引线190密封。
由此形成图1所示的半导体装置100。
此外,作为这种半导体装置100的制造方法,在图5(B)之后,例如也能进行图7所示的工序。
图7是用于说明实施方式中的半导体装置的其它制造方法的图。
准备预先安装了引线框架151、152的壳体160。隔着焊料170在引线框架151的规定区域配置半导体元件180。然后在规定的温度下加热,使焊料170熔融然后使其凝固。由此将引线框架151的一端部与半导体元件180连接(图7(A))。
接着,在图5(B)的层叠基板110上安装图7(A)的壳体160,将引线框架151的一端部设置在电路图案112c上的焊料141上,并将引线框架152的一端部设置在电路图案112d上的焊料142上。另外,壳体160经由粘接剂安装于层叠基板110。此外,该情况下,焊料141、142使用熔点低于焊料170的材料。例如焊料141、142使用锡-银类,焊料170使用锡-锑类。并且,在比焊料170的熔点低的温度下进行加热,来使焊料141、142熔融,然后使其凝固。由此,引线框架151、152的一端部分别经由焊料141、142与电路图案112c、112d相连(图7(B))。
接着,利用引线190将半导体元件180与引线框架152的电路图案112d上方的区域电连接。
接着,在壳体160内填充密封树脂200,以将壳体160内的层叠基板110、引线框架151、152、半导体元件180、引线190密封。
由此形成图1所示的半导体装置100。
在图3和图4的半导体装置500中,利用引线572将半导体元件540的背面电极与引线框架551电连接。另一方面,在半导体装置100中,半导体元件180的背面电极与引线框架151直接电连接。因此,在半导体装置100中,与半导体装置500相比能减少引线键合工序,制造成本得以削减。
标号说明
100 半导体装置
110 层叠基板
111 绝缘板
112 电路板
112a、112b、112c、112d 电路图案
120 散热板
131、132 绝缘层
133 间隙
141、142、170 焊料
151、152 引线框架
160 壳体
180 半导体元件
190 引线
200 密封树脂
Claims (5)
1.一种半导体装置,其特征在于,具有:
层叠基板,该层叠基板具有绝缘板以及设置在所述绝缘板的主面且包含第一电路图案的电路板;
壳体,该壳体设置于所述层叠基板的外周缘并包围所述外周缘;
第一引线框架,该第一引线框架的一侧从所述壳体向外部设置,另一侧与所述第一电路图案相连;
以及
半导体元件,该半导体元件设置在所述壳体内的所述第一引线框架上,
该半导体装置还具有:
第二电路图案,该第二电路图案包含于所述电路板且设置于所述绝缘板的主面,并配置在所述绝缘板的主面与所述第一引线框架之间;以及
绝缘层,该绝缘层中埋设有所述第二电路图案,并设置于所述第二电路图案与所述第一引线框架的间隙,该绝缘层与所述第一电路图案的侧部之间设置有间隙,
所述半导体元件的发热在所述第一引线框架和所述第一电路图案中传导,
所述第一引线框架比所述第一电路图案厚。
2.如权利要求1所述的半导体装置,其特征在于,
所述半导体元件设置在所述第一引线框架的与所述第一电路图案上方相对的区域。
3.如权利要求1至2的任一项所述的半导体装置,其特征在于,具有:
第三电路图案,该第三电路图案包含于所述电路板且设置于所述绝缘板的主面,并夹着所述第一电路图案配置在所述第二电路图案的相反侧;
第二引线框架,该第二引线框架的一侧从所述壳体向外部设置,另一侧与所述第三电路图案相连;以及
引线,该引线将所述半导体元件与所述第二引线框架的与所述第三电路图案上方相对的区域连接。
4.如权利要求3所述的半导体装置,其特征在于,
所述第二引线框架比所述第三电路图案厚。
5.如权利要求3所述的半导体装置,其特征在于,
所述第二引线框架与所述第三电路图案通过焊料或导电性粘接剂相连。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5559374A (en) * | 1993-03-25 | 1996-09-24 | Sanyo Electric Co., Ltd. | Hybrid integrated circuit |
US5767573A (en) * | 1995-10-26 | 1998-06-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
CN101253627A (zh) * | 2005-08-31 | 2008-08-27 | 三洋电机株式会社 | 电路装置及其制造方法 |
CN100562999C (zh) * | 2003-07-31 | 2009-11-25 | 三洋电机株式会社 | 电路模块 |
CN102420223A (zh) * | 2010-09-24 | 2012-04-18 | 安森美半导体贸易公司 | 电路装置及其制造方法 |
CN104465603A (zh) * | 2013-09-23 | 2015-03-25 | 台达电子企业管理(上海)有限公司 | 功率模块 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100440500C (zh) * | 2003-03-11 | 2008-12-03 | 古河电气工业株式会社 | 印刷配线基板、其制造方法、引线框封装件以及光模块 |
US7440286B2 (en) * | 2005-04-21 | 2008-10-21 | Super Talent Electronics, Inc. | Extended USB dual-personality card reader |
US7532481B2 (en) | 2004-04-05 | 2009-05-12 | Mitsubishi Materials Corporation | Al/AlN joint material, base plate for power module, power module, and manufacturing method of Al/AlN joint material |
JP4492257B2 (ja) | 2004-08-26 | 2010-06-30 | 富士電機システムズ株式会社 | 半導体モジュールおよびその製造方法 |
WO2007036944A2 (en) * | 2005-09-30 | 2007-04-05 | Hydro-Industries Tynat Ltd. | Self-powered non-contact water appliance |
US7957158B2 (en) * | 2006-10-31 | 2011-06-07 | Sanyo Electric Co., Ltd. | Circuit device |
KR101489325B1 (ko) * | 2007-03-12 | 2015-02-06 | 페어차일드코리아반도체 주식회사 | 플립-칩 방식의 적층형 파워 모듈 및 그 파워 모듈의제조방법 |
JP4934559B2 (ja) * | 2007-09-27 | 2012-05-16 | オンセミコンダクター・トレーディング・リミテッド | 回路装置およびその製造方法 |
JP2012209469A (ja) | 2011-03-30 | 2012-10-25 | Mitsubishi Electric Corp | 電力用半導体装置 |
JP5682511B2 (ja) * | 2011-08-31 | 2015-03-11 | サンケン電気株式会社 | 半導体モジュール |
JP2013138087A (ja) | 2011-12-28 | 2013-07-11 | Sanken Electric Co Ltd | 半導体モジュール及びその製造方法 |
JP2013258321A (ja) | 2012-06-13 | 2013-12-26 | Fuji Electric Co Ltd | 半導体装置 |
-
2016
- 2016-02-05 JP JP2016020743A patent/JP6790372B2/ja active Active
- 2016-12-28 CN CN201611232698.5A patent/CN107046009B/zh active Active
-
2017
- 2017-01-03 US US15/397,692 patent/US10461024B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5559374A (en) * | 1993-03-25 | 1996-09-24 | Sanyo Electric Co., Ltd. | Hybrid integrated circuit |
US5767573A (en) * | 1995-10-26 | 1998-06-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
CN100562999C (zh) * | 2003-07-31 | 2009-11-25 | 三洋电机株式会社 | 电路模块 |
CN101253627A (zh) * | 2005-08-31 | 2008-08-27 | 三洋电机株式会社 | 电路装置及其制造方法 |
CN102420223A (zh) * | 2010-09-24 | 2012-04-18 | 安森美半导体贸易公司 | 电路装置及其制造方法 |
CN104465603A (zh) * | 2013-09-23 | 2015-03-25 | 台达电子企业管理(上海)有限公司 | 功率模块 |
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