JP6657035B2 - 昇圧回路 - Google Patents
昇圧回路 Download PDFInfo
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- JP6657035B2 JP6657035B2 JP2016127622A JP2016127622A JP6657035B2 JP 6657035 B2 JP6657035 B2 JP 6657035B2 JP 2016127622 A JP2016127622 A JP 2016127622A JP 2016127622 A JP2016127622 A JP 2016127622A JP 6657035 B2 JP6657035 B2 JP 6657035B2
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- Prior art keywords
- voltage
- circuit
- booster
- test
- signal
- Prior art date
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- 230000010355 oscillation Effects 0.000 claims description 15
- 238000010586 diagram Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/06—Acceleration testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/02—Shaping pulses by amplifying
- H03K5/023—Shaping pulses by amplifying using field effect transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Dc-Dc Converters (AREA)
- Semiconductor Integrated Circuits (AREA)
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Description
なお、PMOSトランジスタ21は、起動時など昇圧電圧VPPが低い時はオフして、分圧電圧VFBが接地電圧VSSになるように、即ち昇圧部25が動作するように機能する。また、発振回路24や昇圧部25は、イネイブル端子の信号ENによって動作が制御される。
テスト信号を入力するテスト端子と、を備え、前記分圧回路は、前記テスト信号に応じて分圧比が変更可能であり、前記テスト信号がテスト状態を示す時に、前記比較回路の出力する前記信号が前記昇圧部を連続動作させることを特徴とする。
図1は、本発明の実施形態の昇圧回路10を示す回路図である。
本実施形態の昇圧回路10は、PMOSトランジスタ11と、分圧回路12と、比較回路13と、発振回路14と、昇圧部15と、リミット回路16とを備える。分圧回路12は、直列に接続された抵抗1〜3と、ソースとドレインが抵抗3の両端に接続され、ゲートがテスト端子に接続されたNMOSトランジスタ4を備えている。テスト端子は、テスト信号である信号TESTが入力される。リミット回路16は、ソースとゲートを接地端子に接続したNMOSトランジスタ5で構成される。
通常動作時は、テスト端子にローレベルの信号TESTが入力され、分圧回路12のNMOSトランジスタ4はオフする。即ち、分圧電圧VFBは、抵抗1と抵抗2及び3で昇圧電圧VPPを分圧した電圧である。
イネイブル端子の信号ENがハイレベルになると、比較回路13と発振回路14と昇圧部15は動作を開始する。
例えば、リミット回路16は、NMOSトランジスタのブレークダウン電圧を用いたが、ダイオードを用いても良い。
また、昇圧回路10は、電源電圧VCCを昇圧するように説明したが、電源電圧VCCに限らず入力される電圧を昇圧すれば良い。
また、昇圧回路10は、イネイブル端子の信号ENによって起動停止するように説明したが、イネイブル端子は備えなくても良い。
13 比較回路
14 発振回路
15 昇圧部
16 リミット回路
Claims (3)
- 入力電圧を昇圧して昇圧電圧を出力する昇圧回路であって、
入力される信号に応じて間欠動作する発振回路と、
前記発振回路のパルス信号を受けて前記入力電圧を昇圧する昇圧部と、
前記昇圧電圧を分圧して分圧電圧を出力する分圧回路と、
前記分圧電圧と基準電圧を比較し、比較結果の前記信号を出力する比較回路と、
前記昇圧電圧をクランプするリミット回路と、
テスト信号を入力するテスト端子と、を備え、
前記分圧回路は、前記テスト信号に応じて分圧比が変更可能であり、
前記テスト信号がテスト状態を示す時に、前記比較回路の出力する前記信号が前記昇圧部を連続動作させる
ことを特徴とする昇圧回路。 - 前記分圧回路は、前記テスト信号がテスト状態を示す時に、前記分圧電圧が低くなるように分圧比が変更される
ことを特徴とする請求項1記載の昇圧回路。 - 前記リミット回路は、前記昇圧電圧を、通常動作時の昇圧電圧より高く、テスト状態時の昇圧電圧より低い電圧にクランプする
ことを特徴とする請求項1または請求項2記載の昇圧回路。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016127622A JP6657035B2 (ja) | 2016-06-28 | 2016-06-28 | 昇圧回路 |
US15/627,720 US9923458B2 (en) | 2016-06-28 | 2017-06-20 | Booster circuit including a booster section configured to operate intermittently |
CN201710493650.8A CN107546978B (zh) | 2016-06-28 | 2017-06-26 | 升压电路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016127622A JP6657035B2 (ja) | 2016-06-28 | 2016-06-28 | 昇圧回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2018007333A JP2018007333A (ja) | 2018-01-11 |
JP6657035B2 true JP6657035B2 (ja) | 2020-03-04 |
Family
ID=60678041
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016127622A Active JP6657035B2 (ja) | 2016-06-28 | 2016-06-28 | 昇圧回路 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9923458B2 (ja) |
JP (1) | JP6657035B2 (ja) |
CN (1) | CN107546978B (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110211623B (zh) * | 2019-07-04 | 2021-05-04 | 合肥联诺科技股份有限公司 | 一种nor flash存储单元阵列的电源*** |
CN112737329B (zh) * | 2020-12-25 | 2022-05-03 | 上海贝岭股份有限公司 | 电压控制、高电压产生电路及方法、设备和存储介质 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0153542B1 (ko) * | 1993-11-26 | 1998-10-15 | 김광호 | 반도체 집적장치의 기준전압 발생회로 |
JPH08153390A (ja) * | 1994-11-30 | 1996-06-11 | Matsushita Electron Corp | 半導体集積回路 |
JPH10241388A (ja) * | 1996-12-29 | 1998-09-11 | Sony Corp | 電圧供給回路および半導体不揮発性記憶装置 |
JP4384541B2 (ja) * | 2004-05-21 | 2009-12-16 | 株式会社ケーヒン | アクチュエータ駆動装置 |
US20060279268A1 (en) * | 2005-06-10 | 2006-12-14 | Advanced Analogic Technologies, Inc. | Method for Operational Amplifier Output Clamping for Switching Regulators |
JP2007323376A (ja) * | 2006-06-01 | 2007-12-13 | Rohm Co Ltd | 電源装置及びこれを備えた電気機器 |
JP2008027509A (ja) * | 2006-07-20 | 2008-02-07 | Seiko Epson Corp | 昇圧回路及び不揮発性メモリ装置 |
JP2010124590A (ja) * | 2008-11-19 | 2010-06-03 | Seiko Instruments Inc | 昇圧回路 |
JP5448477B2 (ja) * | 2009-02-04 | 2014-03-19 | ルネサスエレクトロニクス株式会社 | 昇圧回路、この昇圧回路を用いた表示装置、この昇圧回路を用いた昇圧方法およびこの昇圧方法を用いた表示装置への電力供給方法 |
JP2011193579A (ja) * | 2010-03-12 | 2011-09-29 | Elpida Memory Inc | 半導体装置 |
KR20130012795A (ko) * | 2011-07-26 | 2013-02-05 | 에스케이하이닉스 주식회사 | 반도체 집적회로 |
JP2013114546A (ja) * | 2011-11-30 | 2013-06-10 | Renesas Electronics Corp | 半導体装置 |
JP6220263B2 (ja) * | 2013-09-19 | 2017-10-25 | 株式会社東芝 | 基準電圧発生装置およびスイッチング電源装置 |
-
2016
- 2016-06-28 JP JP2016127622A patent/JP6657035B2/ja active Active
-
2017
- 2017-06-20 US US15/627,720 patent/US9923458B2/en active Active
- 2017-06-26 CN CN201710493650.8A patent/CN107546978B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
US9923458B2 (en) | 2018-03-20 |
JP2018007333A (ja) | 2018-01-11 |
CN107546978B (zh) | 2020-12-04 |
US20170373591A1 (en) | 2017-12-28 |
CN107546978A (zh) | 2018-01-05 |
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