JP6647830B2 - 半導体装置及びそれを用いた半導体集積回路 - Google Patents
半導体装置及びそれを用いた半導体集積回路 Download PDFInfo
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Description
以下、本発明の第1の実施の形態について図面を参照しながら説明する。図1は、本発明の第1の実施の形態に係る半導体装置100の構成を示す模式的平面図である。図2は、図1の半導体装置100のF−F線における模式的断面図である。図3は、図1の半導体装置100のG−G線における模式的断面図である。図4は、図1の半導体装置100の主トランジスタと寄生トランジスタを示す模式的平面図である。図5は、図1の半導体装置100の主トランジスタと寄生トランジスタとの関係を示す回路図である。
次に、本発明の第2の実施の形態について図面を参照しながら説明する。図6は、本発明の第2の実施の形態に係る半導体装置200の構成を示す模式的平面図である。図7は、図6の半導体装置200のH−H線における模式的断面図である。図8は、図6の半導体装置200のI−I線における模式的断面図である。図9は、図6の半導体装置200のJ−J線における斜視断面図である。図10は、図6の半導体装置200のトランジスタと寄生トランジスタを示す模式的平面図である。図11は、図6の半導体装置200のトランジスタと寄生トランジスタとの関係を示す回路図である。
次に、本発明の第3の実施の形態について図面を参照しながら説明する。図12は、本発明の第3の実施の形態に係る半導体装置の構成を示す模式的平面図である。図13は、図12の半導体装置のK−K線における模式的断面図である。図14は、図12の半導体装置のL−L線における模式的断面図である。図15は、図12の半導体装置のM−M線における斜視断面図である。図16は、図12の半導体装置のトランジスタと寄生トランジスタを示す模式的平面図である。図17は、図12の半導体装置のトランジスタと寄生トランジスタとの関係を示す回路図である。
次に、本発明の第4の実施の形態について図面を参照しながら説明する。図18は、本発明の第4の実施の形態に係る半導体集積回路の構成を示す模式的回路図である。図18の半導体集積回路は、第1の実施の形態から第3の実施の形態で述べた半導体装置を半導体集積回路に適用した一例を示している。第1の実施の形態から第3の実施の形態で述べた半導体装置は、例えば、差動対トランジスタ、差動増幅器、カレントミラー回路、コンパレータ、演算増幅器等に採用され、半導体集積回路に作り込まれる。差動対トランジスタとは、同じ導電型の2つのトランジスタで構成され、両トランジスタの入力信号の差分、入力電圧の差分及び入力電流の差分に応じて動作する回路の総称である。差動増幅器は差動対トランジスタを主体とし、さらに別の差動対トランジスタ、定電流源、抵抗及びキャパシタを含む場合がある。コンパレータは基本的には複数段(一段以上)の差動増幅器で構成される。本発明の半導体集積回路には、これらの構成に加え、論理回路等が含まれてもよい。
本発明の第1の実施の形態から第3の実施の形態に係る半導体装置が半導体集積回路に用いられる一例は図18、図19で説明したが、ここからは、本発明の第1の実施の形態から第3の実施の形態に係る半導体装置がMOS型回路及び他の半導体集積回路全般に用いられる場合について説明する。
11,21,101,201,301 素子分離領域
12,22a,22b,102,202a,202b,302a,302b ソース領域(ドレイン領域)
13,23a,23b,103,203a,203b,303a,303b ドレイン領域(ソース領域)
14,24a,24b,104,204a,204b,304a,304b ゲート電極
15,25,105,205,305 半導体領域
16,26a,26b,106,206a,206b,306a,306b ゲート絶縁膜
17,27,107,207,307 半導体基板
20a,20b,200a,200b,300a,300b トランジスタ
100a,100b,400,400a〜400d,500a,500b,600a,600b,700a〜700f,800a〜800g,900a,900b MOSトランジスタ
100c 差動対トランジスタ
C キャパシタ
ch チャネル領域
CMP コンパレータ
D,Da〜Dd ドレイン
G,Ga〜Gd ゲート
GND グランド端子(低電位端子)
IN 入力端子
Id1,ids ドレイン電流
Iss,Idd1,ICC1,ICC2 定電流源
iss,Idd2 定電流
L1,L2a,L2b,L3,L4a,L4b,L5a,L5b,L6 チャネル長
OUT,OUT1,OUT2 出力端子
Pa,Pb 配線
Q10,Q20a,Q20b,Q100,Q200a,Q200b,Q300a,Q300b 主トランジスタ
Q11,Q12,Q21a,Q22a,Q21b,Q22b,Q101〜Q104,Q201a〜Q204a,Q201b〜Q204b,Q301a,Q302a,Q301b,Q302b,Q303,Q304 寄生トランジスタ
Ra,Rb 負荷抵抗
S,Sa〜Sd ソース
Suba〜Subd 基板電極
t10〜t12,t20a〜t22a,t20b〜t22b,t100〜t104,t200a〜t204a,t200b〜t204b,t300a〜t302a,t300b〜t302b,t303,t304 ゲート厚
V1,V2,Vi,Vi1,Vi2,Vin 入力電圧
Va,Vb,Vo,Vo1,Vo2,Vout 出力電圧
Vgs,Vgs1,Vgs2 ゲート・ソース間電圧
Vref 参照電圧
Vss,VDD 電源端子(高電位端子)
W1〜W10,ΔW ゲート幅
Claims (6)
- 第1導電型の第1領域と、
前記第1領域を挟むように形成される第1導電型の第2領域及び第1導電型の第3領域と、
前記第1領域と前記第2領域との間に形成される第2導電型の第1チャネル領域と、
前記第1領域と前記第3領域との間に形成される第2導電型の第2チャネル領域と、
前記第1チャネル領域上に形成される第1ゲート絶縁膜と、
前記第1ゲート絶縁膜上に形成される第1ゲート電極と、
前記第2チャネル領域上に形成される第2ゲート絶縁膜と、
前記第2ゲート絶縁膜上に形成される第2ゲート電極と、
前記第1領域、前記第2領域、前記第3領域、前記第1チャネル領域及び前記第2チャネル領域を取り囲む素子分離領域とを備え、
前記第1ゲート電極は前記第1チャネル領域と前記素子分離領域との境界部を跨いで配線され、
前記第2ゲート電極は前記第2チャネル領域と前記素子分離領域との境界部を跨いで配線され、
前記第1領域、前記第2領域及び前記第3領域のチャネル幅方向において、前記第1領域の幅は前記第2領域の幅及び前記第3領域の幅よりも短く、
前記第1領域、前記第2領域及び前記第3領域のチャネル幅方向において、前記第1領域の両端は、前記第2領域及び前記第3領域の両端よりも内側に位置し、
前記第1領域、前記第2領域及び前記第3領域のチャネル幅方向において、前記第1領域の両端は、前記第1ゲート絶縁膜及び前記第2ゲート絶縁膜の両端よりも内側に位置し、
前記第1ゲート絶縁膜と前記第2ゲート絶縁膜は、前記第1領域を取り囲むことなく、互いに分離して形成されており、
前記第1ゲート電極と前記第2ゲート電極は、前記第1領域を取り囲むことなく、互いに分離して形成されている、半導体装置。 - 請求項1に記載の半導体装置による少なくとも2つのトランジスタが用いられ、前記少なくとも2つのトランジスタがソース共通結合又はドレイン共通結合がされた差動対トランジスタを含む、半導体集積回路。
- 前記トランジスタはMOSトランジスタ動作領域の弱反転領域(サブスレッショルド領域)で作動する、請求項2に記載の半導体集積回路。
- 前記トランジスタはMOSトランジスタ動作領域の強反転領域で作動する、請求項2に記載の半導体集積回路。
- 前記トランジスタは差動増幅器、カスコード回路、カレントミラー回路、コンパレータ及び演算増幅器の少なくとも1つに使用される、請求項3又は請求項4に記載の半導体集積回路。
- 前記トランジスタに基板バイアス効果が生じるように基板電極が所定の電位に固定されている、請求項2〜5のいずれか一項に記載の半導体集積回路。
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