JP6524533B2 - Substrate for mounting semiconductor element, semiconductor device, optical semiconductor device, and manufacturing method thereof - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 233
- 239000000758 substrate Substances 0.000 title claims description 148
- 230000003287 optical effect Effects 0.000 title claims description 67
- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 238000007747 plating Methods 0.000 claims description 102
- 239000011347 resin Substances 0.000 claims description 89
- 229920005989 resin Polymers 0.000 claims description 89
- 238000007789 sealing Methods 0.000 claims description 42
- 238000011161 development Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 description 25
- 230000008569 process Effects 0.000 description 13
- 230000000052 comparative effect Effects 0.000 description 12
- 239000000463 material Substances 0.000 description 11
- 238000000576 coating method Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 230000002093 peripheral effect Effects 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 239000007769 metal material Substances 0.000 description 4
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 230000001154 acute effect Effects 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000029 sodium carbonate Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Led Device Packages (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
本発明は、半導体素子搭載用基板、半導体装置及び光半導体装置、並びにそれらの製造方法に関する。 The present invention relates to a substrate for mounting a semiconductor element, a semiconductor device, an optical semiconductor device, and a method of manufacturing them.
近年、携帯電話に代表されるように、電子機器の小型化・軽量化が急速に進み、それら電子機器に用いられる半導体装置も小型化・軽量化・高機能化が要求されている。特に、半導体装置の厚みについて、薄型化が要求されている。かかる要求に応えるため、ＱＦＮ（Quad Flat No-Lead）等の金属材料を加工したリードフレームを用いた半導体装置から、導電性基板を最終的に除去する態様の半導体装置が開発されてきている。 2. Description of the Related Art In recent years, as represented by cellular phones, the miniaturization and weight reduction of electronic devices has rapidly progressed, and the semiconductor devices used for the electronic devices have also been required to be smaller, lighter, and highly functional. In particular, thinning of the thickness of the semiconductor device is required. In order to meet such requirements, semiconductor devices have been developed in which a conductive substrate is finally removed from a semiconductor device using a lead frame obtained by processing a metal material such as QFN (Quad Flat No-Lead).
具体的には、導電性を有する基板の一面側に、所定のパターニングを施したレジストマスクを形成する。レジストマスクから露出した導電性基板に金属をめっきし、半導体素子搭載用のダイパッド部と、半導体素子と接続する内部端子及び外部機器と接続するための外部端子として機能するリード部とを形成した後、レジストマスクを除去することにより、半導体素子搭載用基板を形成する。形成した半導体素子搭載用基板に半導体素子を搭載し、ワイヤーボンディングした後に樹脂封止を行い、導電性基板を除去してダイパッド部やリード部を露出させ、半導体装置を完成させている（例えば、特許文献１、２参照）。 Specifically, a resist mask subjected to predetermined patterning is formed on one surface side of a substrate having conductivity. After plating a metal on the conductive substrate exposed from the resist mask to form a die pad portion for mounting a semiconductor element, and a lead portion functioning as an internal terminal connected to the semiconductor element and an external terminal for connecting to an external device Then, the resist mask is removed to form a semiconductor element mounting substrate. The semiconductor element is mounted on the formed semiconductor element mounting substrate, and after wire bonding, resin sealing is performed, the conductive substrate is removed, and the die pad portion and the lead portion are exposed (for example, the semiconductor device is completed). Patent Documents 1 and 2).
しかしながら、これらの半導体装置は、封止樹脂との密着度が低いため、封止樹脂から端子部が脱落したり、脱落しないものの剥離し、半導体装置の信頼性が低下したりするという問題があり、種々の改善がなされてきた。 However, since these semiconductor devices have a low degree of adhesion to the sealing resin, there is a problem that the terminal portion is detached from the sealing resin, or those which do not fall off are peeled off, and the reliability of the semiconductor device is lowered. Various improvements have been made.
例えば、特許文献１には、形成したレジストマスクを超えて導電性金属を電着させることで、半導体素子搭載用の金属層と、外部接続用の電極層の上端部周縁に張り出し部を有する半導体素子搭載用基板を得て、樹脂封止の際に金属層と電極層の張り出し部が樹脂に食い込む形となり、確実に樹脂側に残るようにする方法が記載されている。 For example, Patent Document 1 discloses a semiconductor having a metal layer for mounting a semiconductor element and a protruding portion at the upper end periphery of an electrode layer for external connection by electrodepositing a conductive metal over the formed resist mask. There is described a method of obtaining a substrate for mounting an element and making a protruding portion of a metal layer and an electrode layer bite into a resin at the time of resin sealing so as to surely remain on the resin side.
特許文献１に記載されたレジストマスクを超えて導電性金属を電着させる方法においては、レジストマスクをオーバーハングさせてめっき層を形成するが、オーバーハング量をコントロールすることは難しく、形成するめっき層の全てが同じ張り出し長さにならない問題や、張り出し部が大きくなると隣のめっき層と繋がってしまう問題が発生している。また、めっき層が薄くなると、張り出し部の幅も厚みも小さくなることから、封止樹脂との密着性が低下する問題も抱えている。さらに、オーバーハングさせためっき層の上面は、めっきの縦方向と横方向の成長比率の関係で球状となるため、ボンディングの信頼性を低下させる要因ともなる。 In the method of electrodepositing a conductive metal over the resist mask described in Patent Document 1, the resist mask is overhanged to form a plating layer, but it is difficult to control the amount of overhang, and plating is performed There is a problem that all of the layers do not have the same overhang length, or a problem in which when the overhang portion becomes large, it is connected to the adjacent plating layer. In addition, when the plating layer becomes thin, the width and thickness of the overhanging portion also become small, which causes a problem that the adhesion to the sealing resin is lowered. Furthermore, the upper surface of the overhanging plated layer is spherical due to the relationship between the growth ratio in the longitudinal direction and the lateral direction of the plating, which also causes a reduction in the reliability of bonding.
また、特許文献２には、レジストマスクを形成する際に、散乱紫外光を用いてレジストマスクを台形に形成することで、金属層あるいは電極層を逆台形の形状に形成する方法が記載されている。 Further, Patent Document 2 describes a method of forming a metal layer or an electrode layer in an inverted trapezoidal shape by forming a resist mask in a trapezoidal shape using scattered ultraviolet light when forming a resist mask. There is.
特許文献２に記載された、散乱紫外光を用いてレジスト層の開口部の断面形状を台形に形成する方法は、電極層の断面形状が逆台形に形成されているため、封止樹脂との密着度は向上し、封止樹脂から金属層や電極層の脱落や剥離の発生はなく、効果はあった。 The method of forming the cross-sectional shape of the opening of the resist layer into a trapezoidal shape using scattered ultraviolet light described in Patent Document 2 is that the cross-sectional shape of the electrode layer is formed into an inverted trapezoidal shape. The degree of adhesion is improved, and the sealing resin does not come off or peel off the metal layer or the electrode layer, which is effective.
しかしながら、電極層の断面形状を逆台形にしたことで、半導体素子を搭載し、ワイヤーボンディングした後に樹脂封止する際、電極層の側面部が導電性基板に対して鋭角になり、封止樹脂が回り込みづらくなった。このため、場合によっては、ボイド等封止樹脂の未充填が発生する場合があった。また、電極層基部付近の封止樹脂は、当然、この角度に倣い形成されるため、先端が鋭角な形状となり強度的にも弱く、封止樹脂部の先端の欠けや剥がれが発生し易いという問題があった。 However, when the cross-sectional shape of the electrode layer is inverted trapezoidal, when the semiconductor element is mounted and wire-bonded and then resin-sealed, the side portion of the electrode layer has an acute angle with respect to the conductive substrate, and the sealing resin It became hard to get around. For this reason, depending on the case, there may be a case where unfilled of sealing resin such as void occurs. Also, since the sealing resin in the vicinity of the base of the electrode layer is naturally formed following this angle, the tip has an acute-angled shape and is weak in strength, and chipping or peeling of the tip of the sealing resin is likely to occur. There was a problem.
また、散乱光を使用するため、レジスト層は半露光状態になりテーパー形状を形成するが、半露光状態のため、底面の寸法精度は、平行光を用いてレジストを露光・現像して作製した寸法精度よりもばらつきが大きく、寸法精度が劣るという問題もあった。特に、半導体装置の小型化、薄型化により、リード形状が小さくなる傾向ある中では、底面寸法精度の向上は重要であり、特許文献２に記載の構成では、この要請に十分応えることが困難であった。 In addition, because the scattered light is used, the resist layer is in the semi-exposure state and forms a tapered shape, but because of the semi-exposure state, the dimensional accuracy of the bottom surface is manufactured by exposing and developing the resist using parallel light. There is also a problem that the variation is larger than the dimensional accuracy and the dimensional accuracy is inferior. In particular, when the lead shape tends to be smaller due to the miniaturization and thinning of the semiconductor device, it is important to improve the bottom dimension accuracy, and it is difficult to sufficiently meet this requirement with the configuration described in Patent Document 2. there were.
そこで、本発明は、半導体素子を搭載後、樹脂封止し導電性基板を除去して完成する半導体装置において、封止樹脂とリード部等の密着度が適切であり、樹脂封止後、導電性基板の除去時等に封止樹脂からリード部等が脱落したり剥離したりする不具合がなく、かつ、リード底面の寸法精度が良好な半導体素子搭載用基板、半導体装置及び光半導体装置、並びにそれらの製造方法を提供することを目的とする。 Therefore, in the semiconductor device of the present invention, which is completed by resin sealing after mounting the semiconductor element and removing the conductive substrate, the degree of adhesion between the sealing resin and the lead portion is appropriate. For mounting a semiconductor element, a semiconductor device, an optical semiconductor device, and a semiconductor element mounting substrate in which there is no problem that the lead portion etc. falls off or peels off the sealing resin at the time of removal of the conductive substrate, etc. It aims at providing those manufacturing methods.
上記目的を達成するため、本発明の一態様に係る半導体素子搭載用基板は、半導体素子搭載後に除去可能な導電性基板と、
該導電性基板の表面上に設けられた半導体素子搭載領域と、
該半導体素子搭載領域の周囲の前記導電性基板の前記表面上の所定領域に設けられためっき層からなるリード部と、を有し、
該リード部は、前記導電性基板の前記表面と略垂直な側面を有して前記表面から柱状に上方に延びる下段部と、
該下段部の上面上に底面を有し、該底面からテーパー状に上方及び側方に広がる側面を有する上段部と、を有し、
前記リード部の前記下段部の前記側面は凹凸を有する平面形状を有し、
前記リード部の前記上段部の前記底面は、前記下段部の上面を包含する平面形状を有し、前記凹凸の凹部を覆う領域が露出した平坦面を有する。
In order to achieve the above object, a substrate for mounting a semiconductor device according to an aspect of the present invention is a conductive substrate that can be removed after mounting the semiconductor device;
A semiconductor element mounting region provided on the surface of the conductive substrate;
And a lead portion comprising a plating layer provided on a predetermined area on the surface of the conductive substrate around the semiconductor element mounting area;
The lead portion has a side surface substantially perpendicular to the surface of the conductive substrate, and a lower portion extending upward from the surface in a columnar shape;
Has a bottom surface on the upper surface of the lower step portion, it has a, and upper portion having a side surface extending upwardly and laterally tapered from the bottom surface,
The side surface of the lower portion of the lead portion has a planar shape having unevenness,
Wherein the upper portion of the lead portion bottom surface has a planar shape including upper surface of the lower portion, the area covering the recess of the uneven to have a flat surface that is exposed.
本発明の他の態様に係る半導体装置は、半導体素子と、
該半導体素子の周囲の所定領域に設けられ、形状の異なる上段部と下段部とを有するめっき層からなるリード部と、
前記半導体素子の電極と前記リード部の前記上段部の上面とを電気的に接続する接続手段と、
少なくとも前記リード部の前記下段部の底面が露出するように前記半導体素子、前記リード部及び前記接続手段を封止する樹脂と、を有し、
前記リード部の前記下段部は、前記底面から上方に垂直に延びる側面を有する柱状形状を有し、
前記リード部の前記上段部は、前記下段部の上面上に底面を有し、該底面からテーパー状に上方及び側方に側面が広がるテーパー形状を有し、
前記リード部の前記下段部の前記側面は波型の凹凸を有する平面形状を有し、
前記リード部の前記上段部の前記底面は、前記下段部の上面を包含する平面形状を有し、前記波型の凹部を覆う領域が露出した平坦面を有する。
A semiconductor device according to another aspect of the present invention is a semiconductor element;
A lead portion comprising a plated layer provided in a predetermined region around the semiconductor element and having an upper portion and a lower portion having different shapes;
Connection means for electrically connecting the electrode of the semiconductor element and the upper surface of the upper portion of the lead portion;
A resin sealing the semiconductor element, the lead portion, and the connection unit such that at least a bottom surface of the lower portion of the lead portion is exposed;
The lower portion of the lead portion has a columnar shape having side surfaces extending vertically upward from the bottom surface,
The upper portion of the lead portion has a bottom surface on an upper surface of the lower portion, it has a tapered shape in which side surfaces extending upwardly and laterally tapered from the bottom surface,
The side surface of the lower portion of the lead portion has a planar shape having a corrugated unevenness,
It said bottom surface of said upper portion of said lead portion has a planar shape including upper surface of the lower portion, the area covering the recess of the wave to have a flat surface that is exposed.
本発明の他の態様に係る光半導体装置は、光半導体素子を搭載する領域を有するダイパッド部と、
前記ダイパッド部と対に設けられ、形状の異なる上段部と下段部とを有するめっき層からなるリード部と、
前記ダイパッド部に搭載された光半導体素子と、
該光半導体素子の電極と前記リード部の前記上段部の上面とを電気的に接続する接続手段と、
前記光半導体素子及び前記接続手段を含む前記ダイパッド部上及び前記リード部上の所定の中央領域を封止する透明樹脂と、
前記ダイパッド部及び前記リード部の底面が露出するように、前記ダイパッド部及び前記リード部の底面以外の前記ダイパッド部と前記リード部との間の領域と、前記ダイパッド部及び前記リード部の所定の外側領域とを封止する外部樹脂と、を有し、
前記リード部の前記下段部は、前記底面から上方に垂直に延びる側面を有する柱状形状を有し、前記リード部の前記上段部は、前記下段部の上面上に底面を有し、該底面からテーパー状に上方及び側方に側面が広がるテーパー形状を有し、
前記リード部の前記下段部の前記側面は凹凸を有する平面形状を有し、
前記リード部の前記上段部の前記底面は、前記下段部の上面を包含する平面形状を有し、前記凹凸の凹部を覆う領域が露出した平坦面を有する。
An optical semiconductor device according to another aspect of the present invention is a die pad portion having a region for mounting an optical semiconductor element;
A lead portion comprising a plated layer provided in pairs with the die pad portion and having an upper portion and a lower portion of different shapes;
An optical semiconductor element mounted on the die pad portion;
Connection means for electrically connecting the electrode of the optical semiconductor element and the upper surface of the upper portion of the lead portion;
A transparent resin for sealing a predetermined central region on the die pad portion including the optical semiconductor element and the connection means and on the lead portion;
A region between the die pad portion and the lead portion other than the die pad portion and the bottom surface of the lead portion so that the bottom surface of the die pad portion and the lead portion is exposed, and a predetermined portion of the die pad portion and the lead portion And an outer resin sealing the outer region,
The lower portion of the lead portion has a columnar shape having a side surface extending vertically upward from the bottom surface, and the upper portion of the lead portion has a bottom surface on the upper surface of the lower portion, and the bottom portion have a tapered shape in which side surfaces extending upwardly and laterally tapered,
The side surface of the lower portion of the lead portion has a planar shape having unevenness,
Wherein the upper portion of the lead portion bottom surface has a planar shape including upper surface of the lower portion, the area covering the recess of the uneven to have a flat surface that is exposed.
本発明の他の態様に係る半導体素子搭載用基板の製造方法は、導電性基板の表面上に、第１の感光波長を有する第１のレジストで被覆した第１のレジスト層、該第１のレジスト層上に第２の感光波長を有する第２のレジストで被覆した第２のレジスト層、該第２のレジスト層上に前記第１のレジストで被覆した第３のレジスト層を順次形成する工程と、
第１の露光により、前記第１及び第３のレジスト層を硬化させるとともに、前記第２のレジスト層を硬化させていない状態で現像を行い、前記第２のレジスト層の上部が前記第１及び第３のレジスト層よりも内側に削れ、テーパー状の形状を有するパターンを形成する工程と、
第２の露光により、第２のレジスト層を硬化させる工程と、
前記第１乃至第３のレジスト層からなるパターンをめっきマスクとしてめっきを行い、前記第１のレジスト層により形成された部分が柱状形状を有し、前記第２のレジスト層により形成された部分がテーパー形状を有するめっき層を形成する工程と、
前記めっきマスクを除去する工程と、を有する。
In a method of manufacturing a semiconductor device mounting substrate according to another aspect of the present invention, a first resist layer coated on a surface of a conductive substrate with a first resist having a first photosensitive wavelength, the first resist layer Forming a second resist layer coated with a second resist having a second photosensitive wavelength on the resist layer, and sequentially forming a third resist layer coated with the first resist on the second resist layer When,
While the first and third resist layers are cured by the first exposure, development is performed in a state where the second resist layer is not cured, and the upper portion of the second resist layer is the first and second resist layers. Forming a pattern having a tapered shape by being scraped inward of the third resist layer;
Curing the second resist layer by the second exposure;
Plating is performed using the pattern formed of the first to third resist layers as a plating mask, the portion formed of the first resist layer has a columnar shape, and the portion formed of the second resist layer is Forming a plating layer having a tapered shape;
And removing the plating mask.
本発明によれば、導電性基板の除去時におけるリード部の脱落及び剥離を防止できるとともに、リード部底面の寸法精度を向上させることができる。 According to the present invention, it is possible to prevent the detachment and peeling of the lead portion at the time of removing the conductive substrate, and to improve the dimensional accuracy of the bottom surface of the lead portion.
以下、図面を参照して、本発明を実施するための形態の説明を行う。 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
［半導体素子搭載用基板及び半導体装置］
図１は、本発明の実施形態に係る半導体素子搭載用基板の一例を示す断面図である。本実施形態に係る半導体素子搭載用基板５０は、導電性基板１０と、その表面１１上に配置された半導体素子搭載用のダイパッド部２１と外部機器と接続するためのリード部２２とで構成されている。リード部２２は、半導体素子搭載領域であるダイパッド部２１の周囲に配置される。
[Semiconductor element mounting substrate and semiconductor device]
FIG. 1 is a cross-sectional view showing an example of a semiconductor device mounting board according to an embodiment of the present invention. The semiconductor element mounting substrate 50 according to the present embodiment includes the conductive substrate 10, the die pad portion 21 for semiconductor element mounting disposed on the surface 11, and the lead portion 22 for connecting to an external device. ing. The lead portion 22 is disposed around the die pad portion 21 which is a semiconductor element mounting region.
また、パターンによっては、半導体素子搭載領域を確保した上で、ダイパッド部２１を作製しないパターンもある。例えば、導電性基板１０に半導体素子を直接搭載するもの、あるいは、半導体素子の電極をリード部に直接接合するフリップチップ接続タイプ等がある。つまり、本実施形態において、ダイパッド部２１を設けることは必須ではなく、半導体素子を搭載可能な半導体素子搭載領域が確保されていればよい。但し、以下の説明においては、半導体素子搭載領域として、ダイパッド部２１が設けられている例について説明する。なお、ダイパッド部２１が設けられる場合、ダイパッド部２１とリード部２２は、同一のめっき層２０で構成されてもよい。なお、ダイパッド部２１及びリード部２２とめっき層２０とは、符号が重複するが、半導体素子搭載用基板５０の構成要素の観点から説明する場合にはダイパッド部２１、リード部２２と呼び、製造上の観点及び構成材料の観点から説明する場合には、めっき層２０と呼んでもよいこととする。 Further, depending on the pattern, there is also a pattern in which the die pad portion 21 is not manufactured after securing the semiconductor element mounting region. For example, there is a type in which the semiconductor element is directly mounted on the conductive substrate 10, or a flip chip connection type in which the electrode of the semiconductor element is directly bonded to the lead portion. That is, in the present embodiment, the provision of the die pad portion 21 is not essential, as long as the semiconductor element mounting area on which the semiconductor element can be mounted is secured. However, in the following description, an example in which the die pad portion 21 is provided as a semiconductor element mounting region will be described. When the die pad portion 21 is provided, the die pad portion 21 and the lead portion 22 may be configured by the same plating layer 20. Although the die pad portion 21 and the lead portion 22 and the plating layer 20 have the same reference numerals, they will be referred to as the die pad portion 21 and the lead portion 22 in the description from the viewpoint of the components of the semiconductor element mounting substrate 50 The plating layer 20 may be referred to in the description from the above viewpoint and the viewpoint of the constituent materials.
導電性基板１０は、表面１１上にめっき層２０が形成される基板であり、電気めっきによりめっき層２０を形成することが可能なように、導電性を有する材料から構成される。使用する導電性基板１０の材質は、導電性が得られれば特に限定はないが、一般的には金属材料が用いられ、例えば、ＣｕまたはＣｕ合金等が使用される。導電性基板を引き剥がし除去する場合は、ＳＵＳ材が使用されることもある。 The conductive substrate 10 is a substrate on which the plating layer 20 is formed on the surface 11, and is made of a material having conductivity so that the plating layer 20 can be formed by electroplating. The material of the conductive substrate 10 to be used is not particularly limited as long as conductivity can be obtained, but generally, a metal material is used, and for example, Cu or a Cu alloy is used. In the case of peeling and removing the conductive substrate, a SUS material may be used.
ダイパッド部２１やリード部２２は、導電性基板１０の片面（表面１１）にめっき加工により形成されためっき層２０から構成される。本発明の実施形態に係る半導体素子搭載用基板５０は、リード部２２の形状に特徴がある。具体的には、リード部２２は、柱状の下段部２２ｂと、テーパー状の上段部２２ａとを有する。また、同様に、ダイパッド部２１も、柱状の下段部２１ｂと、テーパー状の上段部２１ａとを有してもよい。なお、ダイパッド部２１及びリード部２２の構成の詳細については、後述する。 The die pad portion 21 and the lead portion 22 are each formed of a plating layer 20 formed by plating on one surface (surface 11) of the conductive substrate 10. The semiconductor element mounting substrate 50 according to the embodiment of the present invention is characterized by the shape of the lead portion 22. Specifically, the lead portion 22 has a columnar lower portion 22 b and a tapered upper portion 22 a. Similarly, the die pad portion 21 may have a columnar lower portion 21 b and a tapered upper portion 21 a. The details of the configuration of the die pad portion 21 and the lead portion 22 will be described later.
次に、図２を用いて、本発明の実施形態に係る半導体素子搭載用基板５０を用いた半導体装置１００の一例について説明する。図２は、本発明の実施形態に係る半導体装置１００の一例の断面図である。 Next, an example of the semiconductor device 100 using the semiconductor element mounting substrate 50 according to the embodiment of the present invention will be described with reference to FIG. FIG. 2 is a cross-sectional view of an example of the semiconductor device 100 according to the embodiment of the present invention.
図２に示すように、本発明の実施形態に係る半導体装置１００は、ダイパッド部２１に半導体素子６０が搭載され、半導体素子６０の電極６１とリード部２２とがボンディングワイヤー７０等を介して接続されている。また、半導体素子６０及びボンディングワイヤー７０等の接続手段を含めて全体が樹脂８０により封止されている。ダイパッド部２１及びリード部２２は、上面２３及び側面２４は樹脂８０により覆われているが、底面２５は露出している。また、図１で存在していた導電性基板１０は存在しない。導電性基板１０は、樹脂８０により封止が行われた後、除去されている。つまり、図１で示した半導体素子搭載用基板５０のダイパッド部２１上に半導体素子６０が搭載され、半導体素子６０の電極６１とリード部２２とがワイヤーボンディングによりボンディングワイヤー７０を介して接続された後、半導体素子搭載用基板５０上で樹脂８０により封止が行われる。樹脂封止の後、導電性基板１０が除去されることにより、図２に示すような半導体装置１００が作製される。導電性基板１０の除去により露出したリード部２２の底面２５は、外部機器とのはんだ接合するための外部端子となる。 As shown in FIG. 2, in the semiconductor device 100 according to the embodiment of the present invention, the semiconductor element 60 is mounted on the die pad portion 21 and the electrode 61 of the semiconductor element 60 and the lead portion 22 are connected via the bonding wire 70 or the like. It is done. In addition, the whole is sealed by a resin 80 including connecting means such as the semiconductor element 60 and the bonding wire 70. The upper surface 23 and the side surface 24 of the die pad portion 21 and the lead portion 22 are covered with the resin 80, but the bottom surface 25 is exposed. Moreover, the conductive substrate 10 which existed in FIG. 1 does not exist. The conductive substrate 10 is removed after sealing with the resin 80. That is, the semiconductor element 60 is mounted on the die pad portion 21 of the semiconductor element mounting substrate 50 shown in FIG. 1, and the electrode 61 of the semiconductor element 60 and the lead portion 22 are connected via the bonding wire 70 by wire bonding. Thereafter, sealing is performed with a resin 80 on the semiconductor element mounting substrate 50. After resin sealing, the conductive substrate 10 is removed, whereby the semiconductor device 100 as shown in FIG. 2 is manufactured. The bottom surface 25 of the lead portion 22 exposed by the removal of the conductive substrate 10 serves as an external terminal for solder bonding to an external device.
次に、図３を用いて、本発明の実施形態に係る半導体素子搭載用基板５０及び半導体装置１００の特徴であるリード部２２の形状について説明する。 Next, with reference to FIG. 3, the shapes of the semiconductor element mounting substrate 50 and the lead portion 22 which is a feature of the semiconductor device 100 according to the embodiment of the present invention will be described.
図３は、本発明の実施形態に係る半導体素子搭載用基板１００のリード部２２の一例を示した図である。図３（ａ）は、リード部２２の一例を示した平面図である。図３（ｂ）は、図３（ａ）に示したリード部２２のｘ−ｘ断面図である。 FIG. 3 is a view showing an example of the lead portion 22 of the semiconductor element mounting substrate 100 according to the embodiment of the present invention. FIG. 3A is a plan view showing an example of the lead portion 22. FIG. FIG.3 (b) is xx sectional drawing of the lead part 22 shown to Fig.3 (a).
図３に示されるように、本発明の実施形態に係る半導体素子搭載用基板５０の第１の特徴は、リード部２２の断面形状である。図３（ａ）、（ｂ）で示すように、リード部２２は、形状の異なる上段部２２ａと下段部２２ｂとを有する。下段部２２ｂの断面は、垂直方向に直線部を有する形状となっている。上段部２２ａの断面は、リード部周縁に沿い上部が広がるテーパー形状を有する。 As shown in FIG. 3, the first feature of the semiconductor element mounting substrate 50 according to the embodiment of the present invention is the cross-sectional shape of the lead portion 22. As shown in FIGS. 3A and 3B, the lead portion 22 has an upper portion 22a and a lower portion 22b different in shape. The cross section of the lower portion 22b has a shape having a straight portion in the vertical direction. The cross section of the upper portion 22a has a tapered shape in which the upper portion extends along the periphery of the lead portion.
より詳細に説明すると、下段部２２ｂは、導電性基板１０の表面１１から、表面１１に垂直に上方に延びる柱状の形状を有する。図３（ａ）、（ｂ）に示されるように、下段部２２ｂは、略長方形の平面形状又は水平断面形状を有し、略四角柱の形状を有する。下段部２２ｂの側面２４ｂは、鉛直方向に沿って延びているので、下段部２２ｂにおける平面形状及び水平断面形状は、底面、上面、底面と上面の中間で切ったいずれの場合も総て同じである。このように、下段部２２ｂは、平面形状及び水平断面形状が一定な柱状の形状を有する。 More specifically, lower portion 22 b has a columnar shape extending upward from surface 11 of conductive substrate 10 perpendicularly to surface 11. As shown in FIGS. 3A and 3B, the lower portion 22b has a substantially rectangular planar shape or a horizontal cross-sectional shape, and has a substantially rectangular prism shape. Since the side surface 24b of the lower portion 22b extends along the vertical direction, the plane shape and the horizontal cross-sectional shape in the lower portion 22b are all the same in all cases cut at the bottom, top, middle between the bottom and top is there. Thus, the lower portion 22b has a columnar shape having a constant planar shape and horizontal cross-sectional shape.
上段部２２ａは、下段部２２ｂの上面上に、下段部２２ｂと連続的かつ一体的に設けられる。即ち、上段部２２ａの底面（下面）は、下段部２２ｂの上面と同一水平面上に設けられる。しかしながら、上段部２２ａの底面は、下段部２２ｂの上面と必ずしも合同である必要は無く、例えば、上段部２２ａの底面が、下段部２２ｂよりも広く形成され、上段部２２ａの底面が下段部２２ｂの上面を包含するように形成されてもよい。但し、図３（ａ）、（ｂ）の例においては、上段部２２ａの底面は、下段部２２ｂの上面と略同一の形状を有し、角が丸い長方形の形状となっている。 The upper part 22a is provided continuously and integrally with the lower part 22b on the upper surface of the lower part 22b. That is, the bottom surface (lower surface) of the upper portion 22a is provided on the same horizontal plane as the upper surface of the lower portion 22b. However, the bottom surface of the upper portion 22a does not necessarily have to be congruent with the upper surface of the lower portion 22b. For example, the bottom surface of the upper portion 22a is wider than the lower portion 22b, and the bottom surface of the upper portion 22a is lower than the lower portion 22b. It may be formed to include the upper surface of. However, in the example of FIGS. 3A and 3B, the bottom surface of the upper portion 22a has substantially the same shape as the upper surface of the lower portion 22b, and has a rectangular shape with rounded corners.
上段部２２ａの側面２４ａは、その底面からテーパー状に上方及び側方に広がるような形状を有する。図３（ａ）に示されるように、上段部２２ａの上面は、下段部２２ｂと類似した形状を有し、略長方形に構成されている。これは、図３の構成においては、上段部２２ａの底面から側面２４ａが全体にテーパー状に略同じ割合で広がり、上段部２２ａの上面の平面形状は下段部２２ｂの上面よりも大きくなったことを意味する。上段部２２ａの側面２４ａがこのようなテーパー形状を有することにより、樹脂８０への食い付き、引っ掛かりができ、導電性基板１０を樹脂８０から剥離する際等に、リード部２２の樹脂８０からの脱落等を防止することができる。 The side surface 24a of the upper portion 22a has a shape that extends upward and laterally in a tapered manner from the bottom surface thereof. As shown in FIG. 3A, the upper surface of the upper portion 22a has a shape similar to that of the lower portion 22b, and is configured in a substantially rectangular shape. This is because in the configuration of FIG. 3, the side surface 24 a spreads from the bottom surface of the upper portion 22 a in a tapered manner at substantially the same rate, and the planar shape of the upper surface of the upper portion 22 a is larger than the upper surface of the lower portion 22 b. Means When the side surface 24a of the upper portion 22a has such a tapered shape, the resin 80 can bite and get stuck, and when peeling the conductive substrate 10 from the resin 80, the resin 80 of the lead 22 can be used. It is possible to prevent falling off and the like.
なお、図１、２に示すように、リード部２２のみならず、ダイパッド部２１も上段部２１ａ及び下段部２１ｂを有する構成としてもよい。これにより、ダイパッド部２１についても、樹脂８０からの脱落等を防止することができる。 As shown in FIGS. 1 and 2, not only the lead portion 22 but also the die pad portion 21 may have an upper portion 21a and a lower portion 21b. Thus, the die pad portion 21 can be prevented from coming off the resin 80 or the like.
次に、図４を用いて、リード部２２の形成方法について説明する。図４は、リード部２２の形成方法を説明するための図である。図４（ａ）は、めっき用レジストマスク３５の一例を示した図である。図４（ｂ）は、めっき用レジストマスク３５を用いためっき加工の一例を示した図である。 Next, a method of forming the lead portion 22 will be described with reference to FIG. FIG. 4 is a view for explaining a method of forming the lead portion 22. As shown in FIG. FIG. 4A is a view showing an example of the plating resist mask 35. FIG. 4B is a view showing an example of plating using the plating resist mask 35.
リード部２２は、図４（ａ）に示すように、導電性基板１０の上に３枚のレジスト層３１、３２、３３を被覆し、露光、現像してめっき用レジストマスク３５を作製し、これを用いてめっき加工を行い形成している。導電性基板１０に接触するレジスト層から第１のレジスト層３１とし、最上位のレジストを第３のレジスト層３３とする。中間のレジスト層は第２のレジスト層３２となる。第１のレジスト層３１と第３のレジスト層３３のパターンは、リード部２２の底面形状のパターンとする。また、第１のレジスト層３１と第３のレジスト層３３には、感光する波長が略同一な同種のレジストを使用し、第２のレジスト層３２には、第１及び第３のレジスト層３１、３３と感光する波長が異なる種類のレジストを使用する。これらのレジスト層３１〜３３を露光する際、第１及び第３のレジスト層３１、３３は感光し、第２のレジスト層３２は感光しない波長にて露光することにより、第１と第３のレジスト層３１、３３を硬化させ、第２のレジスト層３２を未露光状態にする。これを現像することにより、第１のレジスト層３１と第３のレジスト層３３は、リード部２２の底面形状と略同一で、垂直方向断面の垂直方向の辺（側面２４ｂ）は直線となる。第２のレジスト層３２は、第３のレジスト層３３の開口部３４から第１のレジスト３１の方向に現像されるため、図４（ａ）に示されるように、垂直方向断面の垂直方向の辺は上面側が狭くなる様な（開口部３４の形状は上面側が広がる）テーパー形状になる。第２のレジスト層３２は、未露光状態であり、現像後、露光により硬化処理を行う。このようにして、第２のレジスト層３２がテーパー形状を有するめっき用レジストマスク３５を作製する。 As shown in FIG. 4A, the lead portion 22 covers the three resist layers 31, 32, and 33 on the conductive substrate 10, and is exposed and developed to form a plating resist mask 35, It is plated and formed using this. The resist layer in contact with the conductive substrate 10 is referred to as a first resist layer 31, and the uppermost resist is referred to as a third resist layer 33. The intermediate resist layer becomes the second resist layer 32. The pattern of the first resist layer 31 and the third resist layer 33 is a bottom surface pattern of the lead portion 22. Further, the first resist layer 31 and the third resist layer 33 use the same kind of resist having substantially the same wavelength to be exposed, and the second resist layer 32 has the first and third resist layers 31. , 33 and different types of resists having different wavelengths. When the resist layers 31 to 33 are exposed, the first and third resist layers 31 and 33 are exposed, and the second resist layer 32 is exposed at a wavelength not exposed to light. The resist layers 31 and 33 are cured to leave the second resist layer 32 in an unexposed state. By developing this, the first resist layer 31 and the third resist layer 33 have substantially the same shape as the bottom surface of the lead portion 22, and the side in the vertical direction (side surface 24b) becomes straight. The second resist layer 32 is developed from the opening 34 of the third resist layer 33 in the direction from the opening 34 to the first resist 31, and therefore, as shown in FIG. The side is tapered such that the upper surface side is narrowed (the shape of the opening 34 is expanded on the upper surface side). The second resist layer 32 is in an unexposed state, and after development, is cured by exposure. Thus, the plating resist mask 35 in which the second resist layer 32 has a tapered shape is manufactured.
次に、図４（ｂ）に示されるように、作製されためっき用レジストマスク３５を用いてめっき層２０を形成する。めっき層２０の厚さは、めっき層２０の上面が第３のレジスト層３３に至る前であって、第２のレジスト層３２の間になるように設定する。めっき層２０が第３レジスト層３３までめっきされると、第２のレジスト層３２で上面側が広がるテーパー形状を形成したのに、第３のレジスト層３３でテーパー形状が小さくなってしまう。逆に、第１のレジスト層３１までのめっき層２０では、張り出し形状が形成されず、樹脂８０との密着性を向上させることができない。好ましくは、第２のレジスト層３２の１／２から４／５までにめっき層２０の上面が来るようにめっき厚さを設定する。 Next, as shown in FIG. 4B, the plating layer 20 is formed using the produced resist mask 35 for plating. The thickness of the plating layer 20 is set so that the top surface of the plating layer 20 is between the second resist layer 32 before reaching the third resist layer 33. When the plating layer 20 is plated to the third resist layer 33, the tapered shape of the third resist layer 33 becomes smaller although the second resist layer 32 forms a tapered shape in which the upper surface side is broadened. On the contrary, in the plating layer 20 up to the first resist layer 31, the overhanging shape is not formed, and the adhesion to the resin 80 can not be improved. Preferably, the plating thickness is set so that the upper surface of the plating layer 20 is on 1/2 to 4/5 of the second resist layer 32.
第２のレジスト層３２のテーパー形状は、第２のレジスト層３２の厚みや現像工程での現像時間、現像液の吐出圧力等によりテーパーの角度を調整することができる。テーパー角度は、水平方向を基準に任意に設定することができるが、樹脂８０との密着性を考慮すると、３０°〜８０°に設定することが好ましく、３０°〜６０°に設定することがより好ましい。 The taper shape of the second resist layer 32 can be adjusted by the thickness of the second resist layer 32, the developing time in the developing step, the discharge pressure of the developing solution, and the like. The taper angle can be set arbitrarily based on the horizontal direction, but in consideration of adhesion with the resin 80, it is preferably set to 30 ° to 80 °, and may be set to 30 ° to 60 °. More preferable.
リード部２２は、上述の３層のレジストマスク３５を使用し、レジストマスク３５の開口部３４にめっきを行い、めっき層２０を形成することにより形成される。めっき層２０は、レジストマスク３５の形状に倣い形成されるので、めっき層２０の側面は、上段部２０ａ（第２レジスト層部）と下段部２０ｂ（第１レジスト層部）に分かれ、下段部２０ｂの側面は垂直方向に直線部を有し、上段部２０ａの側面は、めっき層２０の周縁に沿い上部が広がるテーパー形状となる。 The lead portion 22 is formed by plating the opening 34 of the resist mask 35 using the three-layer resist mask 35 described above to form the plating layer 20. Since the plating layer 20 is formed following the shape of the resist mask 35, the side surface of the plating layer 20 is divided into the upper portion 20a (second resist layer portion) and the lower portion 20b (first resist layer portion), and the lower portion The side surface 20 b has a straight portion in the vertical direction, and the side surface of the upper portion 20 a has a tapered shape in which the upper portion extends along the periphery of the plating layer 20.
リード部２２のめっき層２０の下段部２０ｂの厚みは、第１のレジスト層３１の厚みとなる。めっき層２０の下段部２０ｂの厚みは特に限定はないが、第１のレジスト層３１の厚みを考慮すると、１０μｍ〜２５μｍが好ましい。上段部２０ａの厚みは、特に限定はないが、上述のように、めっき層２０は、第２のレジスト層３２の２／５から４／５までの厚さとすることが好ましいことや、このテーパー部が樹脂８０との密着性を向上させることから、２０μｍ〜５０μｍに設定することが好ましい。 The thickness of the lower portion 20 b of the plating layer 20 of the lead portion 22 is the thickness of the first resist layer 31. The thickness of the lower portion 20b of the plating layer 20 is not particularly limited, but in consideration of the thickness of the first resist layer 31, 10 μm to 25 μm is preferable. The thickness of the upper portion 20a is not particularly limited, but as described above, it is preferable that the thickness of the plating layer 20 be 2/5 to 4/5 of the second resist layer 32, or the taper Since the part improves the adhesion to the resin 80, the thickness is preferably set to 20 μm to 50 μm.
これにより、リード部２２の断面形状が上段部２２ａ（第２レジスト層部）と下段部２２ｂ（第１レジスト層部）に分かれ、下段部２２ｂの側面２４ｂは垂直方向に直線部を有し、上段部２２ａの側面２４ａは、めっき層周縁に沿い上部が広がるテーパー形状となるリード部２２を形成できる。 As a result, the cross-sectional shape of the lead portion 22 is divided into the upper portion 22a (second resist layer portion) and the lower portion 22b (first resist layer portion), and the side surface 24b of the lower portion 22b has a straight portion in the vertical direction The side surface 24 a of the upper stage portion 22 a can form a lead portion 22 having a tapered shape in which the upper portion spreads along the periphery of the plating layer.
本発明の実施形態に係る半導体素子搭載用基板５０及び半導体装置１００のリード部２０の形状は、例えば、特許文献１に記載された発明と比較して以下の利点がある。特許文献１では、形成したレジストマスクを超えて導電性金属を電着させることで、リード部の上端部周縁に張り出し部を有する形状が記載されている。この方法では、オーバーハング量をコントロールすることは難しく、形成するめっき層の全てが同じ張り出し長さにならない問題や、張り出し部が大きくなると隣のめっき層と繋がってしまう問題が発生している。 The shapes of the semiconductor element mounting substrate 50 and the lead portions 20 of the semiconductor device 100 according to the embodiment of the present invention have, for example, the following advantages as compared with the invention described in Patent Document 1. Patent Document 1 describes a shape in which a protruding portion is provided on the periphery of the upper end portion of the lead portion by electrodepositing a conductive metal over the formed resist mask. In this method, it is difficult to control the overhang amount, and there is a problem that all of the plating layers to be formed do not have the same overhang length, or a problem that if the overhang portion becomes large, it is connected to the next plating layer.
本発明の実施形態に係る半導体素子搭載用基板５０及び半導体装置１００では、リード部２２が上段部２２ａと下段部２２ｂに分かれ、上段部２２ａはテーパー形状になっている。上段部２２ａのテーパー形状は、第２のレジスト層３２で形成されるので、形状を制御することが可能であり、張り出し部の厚さ、長さ、テーパー角度を任意に設定できる。また、内部端子として機能する上段部２２ａの上面は、ほぼフラットな面を得ることができる。また、特許文献１の形状においては、張り出し部が大きくなると、めっき後にレジスト層を除去する際、張り出し部の根元部にレジストが残りやすいが、本発明の実施形態に係る半導体素子搭載用基板５０及び半導体装置１００のリード部２０の形状であれば、張り出し部は上側部が上方及び側方に広がる様なテーパー形状であり、レジストマスク３５は除去されやすい。 In the semiconductor element mounting substrate 50 and the semiconductor device 100 according to the embodiment of the present invention, the lead portion 22 is divided into an upper portion 22a and a lower portion 22b, and the upper portion 22a has a tapered shape. The tapered shape of the upper portion 22a is formed by the second resist layer 32, so that the shape can be controlled, and the thickness, length, and taper angle of the overhang can be set arbitrarily. Further, the upper surface of the upper portion 22a functioning as an internal terminal can obtain a substantially flat surface. Further, in the shape of Patent Document 1, when the overhang portion becomes large, when removing the resist layer after plating, the resist tends to remain at the root portion of the overhang portion. However, the semiconductor element mounting substrate 50 according to the embodiment of the present invention And in the case of the shape of the lead portion 20 of the semiconductor device 100, the overhanging portion has a tapered shape such that the upper side portion spreads upward and to the side, and the resist mask 35 is easily removed.
特許文献２では、リード部の断面形状をテーパー形状にする記載がある。この場合、リード部の断面形状を逆台形にしたことで、半導体素子を搭載し、ワイヤーボンディングした後に樹脂封止する際、電極層の側面部は導電性基板に対して鋭角になり、封止樹脂が回り込みづらくなり、場合によっては、ボイド等未充填が発生する場合があった。また、リード部基部付近の封止樹脂は、当然、この角度に倣い形成されるため、先端が鋭角な形状となり強度的にも弱く、この封止樹脂部の先端の欠けや剥がれが発生し易いという問題があった。また、レジスト層はテーパー形状を形成するため、底面の寸法精度は劣っていた。 Patent Document 2 describes that the cross-sectional shape of the lead portion is tapered. In this case, by making the cross-sectional shape of the lead portion inverted trapezoidal, when mounting the semiconductor element and wire-bonding and then resin-sealing, the side portion of the electrode layer has an acute angle with respect to the conductive substrate, and sealing is performed. In some cases, unfilled resin such as a void may occur. In addition, since the sealing resin in the vicinity of the lead portion base is naturally formed following this angle, the tip has an acute-angled shape and is weak in strength, and chipping or peeling of the tip of the sealing resin portion is likely to occur. There was a problem that. Moreover, since the resist layer forms a tapered shape, the dimensional accuracy of the bottom surface is inferior.
本発明の実施形態に係る半導体素子搭載用基板５０及び半導体装置１００では、リード部２２が上段部２２ａと下段部２２ｂとに分かれ、下段部２２ｂの側面は、垂直方向に直線部を有しており、リード部２２の底面において導電性基板１０と鋭角になることはなく、樹脂８０の回り込み不具合等の発生を防止できる。また、下段部２２ｂの底面の寸法精度は、第１のレジスト層で露光、現像するため上記テーパー形状に比べて向上する。 In the semiconductor element mounting substrate 50 and the semiconductor device 100 according to the embodiment of the present invention, the lead portion 22 is divided into the upper portion 22a and the lower portion 22b, and the side surface of the lower portion 22b has a straight portion in the vertical direction. In addition, the bottom surface of the lead portion 22 does not have an acute angle with the conductive substrate 10, and the occurrence of a wraparound defect of the resin 80 can be prevented. Further, the dimensional accuracy of the bottom surface of the lower portion 22b is improved as compared with the above-described tapered shape because the exposure and development are performed with the first resist layer.
図５は、図３と異なる形状を有するリード部２６を説明するための図である。図５（ａ）は、リード部２６の一例を示した平面図である。図５（ｂ）は、図５（ａ）に示したリード部２６のｙ−ｙ断面図である。図５（ｃ）は、図５（ａ）に示したリード部２６のｚ−ｚ断面図である。 FIG. 5 is a view for explaining a lead portion 26 having a shape different from that of FIG. FIG. 5A is a plan view showing an example of the lead portion 26. FIG. FIG. 5B is a yy cross-sectional view of the lead portion 26 shown in FIG. FIG. 5C is a z-z cross-sectional view of the lead portion 26 shown in FIG.
リード部の底面形状は、一般的には、図３（ａ）に示すように略矩形である。しかしながら、図５（ａ）、（ｃ）に示すように、リード部２６の側面２７を構成する各辺に凹凸形状を付加してもよい。凹凸形状を付加することで、樹脂８０との密着性をより向上させることができる。凹凸形状は、例えば、波型、山形形状を連続させたジグザク形状、のこぎり形状等を含む。なお、ジグザク形状の各頂点は丸みを帯びた曲線形状とする。 The bottom surface shape of the lead portion is generally substantially rectangular as shown in FIG. 3 (a). However, as shown in FIGS. 5A and 5C, an uneven shape may be added to each side constituting the side surface 27 of the lead portion 26. The adhesion with the resin 80 can be further improved by adding the uneven shape. The uneven shape includes, for example, a wave shape, a zigzag shape in which a mountain shape is continued, a saw shape, and the like. In addition, each vertex of the zigzag shape has a rounded curved shape.
また、図５（ａ）に示すように、上段部２６ａの底面２６ｄ及び上面２６ｃの形状は、底面２６ｄが略長方形の形状であり、上面２６ｃは凹凸形状を有している。上段部２６ａの底面２６ｄは、下段部２６ｂの上面の凹凸形状を包含する長方形状となっている。 Further, as shown in FIG. 5A, the bottom surface 26d and the top surface 26c of the upper portion 26a have a substantially rectangular bottom surface 26d, and the top surface 26c has an uneven shape. The bottom surface 26d of the upper portion 26a has a rectangular shape including the uneven shape of the upper surface of the lower portion 26b.
また、リード部２６の断面形状は、図５（ａ）、（ｂ）で示したように、リード部２６は、上段部２６ａと下段部２６ｂに分かれ、下段部２６ｂの側面２７ｂは垂直方向に直線部を有し、上段部２６ａの側面２７ａは、リード部周縁に沿い上部が広がるテーパー形状を有すると同時に、図５（ａ）、（ｃ）に示すように、上段部２６ａの底面２６ｄの一部には、上段部２６ａと下段部２６ｂの境界に水平部２６ｅを有してもよい。上段部２６ａの底面２６ｄ（上段部と下段部の境界）の一部に水平部２６ｅを有する箇所は、前述のリード部２６の底面形状の各辺に凹凸形状を付加した場合の凹部２７ｃに形成することができる。この凹部２７ｃに形成することで、凹部２７ｃの下面にも樹脂８０を充填することができ、より樹脂８０との密着性を向上させることができる。この凹凸部の凹部の凹み量、つまり凹凸の波の上端と下端の間の振幅の大きさ（長さ）は、下段部２６ｂの厚さ１／２〜下段部２６ｂの厚さの３倍程度が好ましい。下段部２６ｂの厚さ１／２未満だと密着性の効果が小さく、３倍を超えると、第１のレジスト層３１を剥離する時、レジスト残りが発生する可能性が高くなる。好ましくは、下段部２６ｂの厚さ程度である。なお、水平部２６ｅは、平坦面を有するので、平坦面２６ｅと呼んでもよいこととする。 Further, as shown in FIGS. 5A and 5B, the cross-sectional shape of the lead portion 26 is divided into the upper portion 26a and the lower portion 26b, and the side surface 27b of the lower portion 26b is in the vertical direction. The side surface 27a of the upper portion 26a has a tapered shape in which the upper portion extends along the periphery of the lead portion, and at the same time, as shown in FIGS. 5 (a) and 5 (c), of the bottom surface 26d of the upper portion 26a. It may have a horizontal part 26e in the boundary of upper part 26a and lower part 26b in part. The portion having the horizontal portion 26e at a part of the bottom surface 26d of the upper portion 26a (the boundary between the upper portion and the lower portion) is formed as a recess 27c in the case where an uneven shape is added to each side of the bottom shape of the lead portion 26 described above. can do. By forming the recess 27 c, the resin 80 can be filled also on the lower surface of the recess 27 c, and the adhesion to the resin 80 can be further improved. The amount of depression of the concave portion of the uneven portion, that is, the magnitude (length) of the amplitude between the upper end and the lower end of the uneven wave is about half the thickness of the lower portion 26b to 3 times the thickness of the lower portion 26b. Is preferred. If the thickness of the lower portion 26b is less than 1/2, the adhesion effect is small, and if it is more than 3 times, there is a high possibility of resist remaining when the first resist layer 31 is peeled off. Preferably, the thickness is about the thickness of the lower portion 26b. In addition, since the horizontal part 26e has a flat surface, suppose that you may call it the flat surface 26e.
本発明の実施形態に係る半導体装置１００は、上で説明したように、ダイパッド部２１及びリード部２２、２６を上述の形状にすることで、樹脂８０とダイパッド部２１及びリード部２２、２６との密着性を向上することが可能であり、従来の半導体装置に比べ、より小型化、薄型化を図ることが可能となる。 In the semiconductor device 100 according to the embodiment of the present invention, as described above, the resin 80 and the die pad portion 21 and the lead portions 22 and 26 are formed by forming the die pad portion 21 and the lead portions 22 and 26 as described above. It is possible to improve the adhesion of the semiconductor device, and to achieve further downsizing and thinning as compared with the conventional semiconductor device.
［半導体素子搭載用基板の製造方法］
次に、図６を参照して本発明の実施形態に係る半導体素子搭載用基板の製造方法について説明する。図６は、本発明の実施形態に係る半導体素子搭載用基板の製造方法の一例の一連の工程を示した図である。
[Method of Manufacturing Substrate for Mounting Semiconductor Device]
Next, with reference to FIG. 6, a method of manufacturing a semiconductor element mounting substrate according to the embodiment of the present invention will be described. FIG. 6 is a diagram showing a series of steps in an example of a method of manufacturing a semiconductor element mounting substrate according to the embodiment of the present invention.
図６（ａ）は、基板用意工程の一例を示した図である。図６（ａ）に示されるように、本発明の実施形態に係る半導体素子搭載用基板５０を製造するに当たり、まずは導電性基板１０を用意する。使用する導電性基板１０の材質は、導電性が得られるものであれば特に限定はないが、一般的には金属材料が用いられ、例えば、ＳＵＳ材またはＣｕあるいはＣｕ合金等が使用される。 FIG. 6A is a view showing an example of the substrate preparation process. As shown in FIG. 6A, in manufacturing the semiconductor element mounting substrate 50 according to the embodiment of the present invention, first, the conductive substrate 10 is prepared. The material of the conductive substrate 10 to be used is not particularly limited as long as conductivity can be obtained. Generally, a metal material is used, and for example, a SUS material or Cu or a Cu alloy is used.
図６（ｂ）は、レジスト被覆工程の一例を示した図である。レジスト被覆工程では、導電性基板１０の表・裏面全体を、レジストで被う。なお、表面側は、３枚のレジスト層３１〜３３を被覆する。裏面は１枚のレジスト層３０を被覆する。表面側は３枚のレジスト層３１〜３３は、導電性基板１０側より、第１のレジスト層３１、第２のレジスト層３２、第３のレジスト層３３とする。第１のレジスト層３１、第３のレジスト層３３は、感光する波長が略同一の同種のレジスト層とする。第２のレジスト層３２は感光する波長が第１及び第３のレジスト層３１、３３と異なる種類のレジスト層を使用する。使用するレジストとしては、ドライフィルムレジストのラミネート、又は液状レジストの塗布及び乾燥によるレジスト層の被覆等、従来からの公知の方法を用いて行うことができる。 FIG. 6B is a view showing an example of the resist coating process. In the resist coating step, the entire front and back surfaces of the conductive substrate 10 are covered with a resist. The surface side covers the three resist layers 31 to 33. The back side covers one resist layer 30. The three resist layers 31 to 33 on the front side are the first resist layer 31, the second resist layer 32, and the third resist layer 33 from the side of the conductive substrate 10. The first resist layer 31 and the third resist layer 33 are made of the same type of resist layer having the same photosensitive wavelength. The second resist layer 32 uses a resist layer of a type different in sensitized wavelength from the first and third resist layers 31 and 33. The resist to be used may be a conventionally known method such as lamination of a dry film resist or coating of a liquid resist and coating of a resist layer by drying.
図６（ｃ）は、レジストマスク形成工程の一例を示した図である。詳細には、レジストマスク形成工程は、露光工程、現像工程及び硬化処理工程を有する。露光工程では、前のレジスト被覆工程で導電性基板１０の表・裏面にレジストを被覆した後、表面側は第１のレジスト層３１、第３のレジスト層３３が感光し、第２のレジスト層３２が感光しない波長で、及び裏面側は、裏面のレジスト層３０が感光する波長で露光する。この時、そのレジスト上に表面は所望のダイパッド部２１やリード部２２を組とした複数の組を配置したパターン、裏面は全面を覆うパターンが形成されたマスク（紫外光遮蔽ガラスマスク）を被せ、露光を行う。 FIG. 6C is a view showing an example of the resist mask forming process. In detail, the resist mask formation step includes an exposure step, a development step, and a curing treatment step. In the exposure step, after the front and back surfaces of the conductive substrate 10 are coated with the resist in the previous resist coating step, the first resist layer 31 and the third resist layer 33 are exposed on the front side, and the second resist layer is formed. The back side is exposed at a wavelength at which the resist layer 30 on the back side is exposed. At this time, a mask (ultraviolet light shielding glass mask) having a pattern in which a plurality of sets of desired die pad portions 21 and lead portions 22 are arranged is disposed on the surface on the resist, and a pattern covering the entire surface is formed. , Exposure.
なお、第２のレジスト層３２は、第１のレジスト層３１と感光の波長が違うため未露光状態となる。現像工程では、マスクを除去してレジスト層３０〜３３を現像する。まず第３レジスト層３３の開口部３４より未露光が除去され、次に第２のレジスト層３２、第１にレジスト層３１と現像されるため、第２のレジスト層３２は、未露光部であるため第３レジスト層３３側（上部側）から水平方向にも除去されていく。開口部３４の形状は、上面側が広がるテーパー形状になる。第２のレジスト層３２のテーパー形状については、第２のレジスト層３２の厚みや現像工程での現像時間、現像液の吐出圧力等により、現像速度を制御することによりテーパーの角度を調整することができる。その後、第２レジスト層の硬化処理を行う。第２のレジスト層３２の未露光状態であり、露光により硬化させる。このようにして、第２のレジスト層３２にテーパー形状を有するめっき用レジストマスク３５を作製する。 The second resist layer 32 is unexposed because it has a photosensitive wavelength different from that of the first resist layer 31. In the development step, the mask is removed and the resist layers 30 to 33 are developed. First, the unexposed area is removed from the opening 34 of the third resist layer 33, and then the second resist layer 32 and the first resist layer 31 are developed, so the second resist layer 32 is unexposed area. Since it exists, it is also removed in the horizontal direction from the third resist layer 33 side (upper side). The shape of the opening 34 is a tapered shape in which the upper surface side spreads. The taper shape of the second resist layer 32 is adjusted by controlling the developing speed by the thickness of the second resist layer 32, the developing time in the developing step, the discharge pressure of the developing solution, etc. Can. Thereafter, the second resist layer is cured. The unexposed state of the second resist layer 32 is cured by exposure. In this manner, a plating resist mask 35 having a tapered shape in the second resist layer 32 is manufactured.
なお、図５で説明したように、リード部２６の底面形状の各辺を凹凸形状にする場合には、露光工程で、リード形状がその旨のパターンになるようにマスクを（紫外光遮蔽ガラスマスク）を被せ、露光を行う。また、各辺の凹凸部の凹部２７ｃの箇所の上段部２６ａの底面２６ｄに水平部２６ｅを有してもよい。この場合は、現像工程において、第２レジスト層３２を現像する際、テーパー形状より現像時間を長くすることで、凹部２７ｃに該当する上段部２６ａと下段部２６ｂの境界である上段部２６ａの底面２６ｄに水平部２６ｅを設けることが可能である。現像時間を調整することで、水平部２６ｅの長さを調整することができる。パターン形状にもよるので状況により都度調整する。 As described in FIG. 5, when making the sides of the bottom surface of the lead portion 26 uneven, a mask is used so that the lead shape has a pattern to that effect in the exposure step. Cover with mask) and expose. In addition, the bottom surface 26d of the upper portion 26a at the location of the concave portion 27c of the uneven portion on each side may have a horizontal portion 26e. In this case, when developing the second resist layer 32 in the developing step, the developing time is longer than the tapered shape, whereby the bottom surface of the upper portion 26a which is the boundary between the upper portion 26a and the lower portion 26b corresponding to the recess 27c. It is possible to provide the horizontal part 26e in 26d. The length of the horizontal portion 26e can be adjusted by adjusting the development time. As it depends on the pattern shape, it is adjusted according to the situation.
図６（ｄ）は、めっき工程の一例を示した図である。めっき工程では、図６（ｂ）で形成したレジストマスク３５を用い、開口部３４が形成された導電性基板１０の露出部分にめっきを施して、めっき層２０を形成する。めっきは、第２のレジスト層３２の４／５程度の高さまで行う。これにより、めっき層２０は、第１にレジスト層３１と第２のレジスト層３２の形状に沿って形成されることになる。リード部２２の側面は、上段部２２ａと下段部２２ｂに分かれ、下段部２２ｂの側面２４ｂは垂直方向に直線部を有し、上段部２２ａの側面２４ａは、リード部２２の周縁に沿い上部が広がるテーパー形状を有する形状に形成することができる。 FIG. 6D is a view showing an example of the plating process. In the plating step, using the resist mask 35 formed in FIG. 6B, the exposed portion of the conductive substrate 10 in which the opening 34 is formed is plated to form a plating layer 20. The plating is performed to a height of about 4/5 of the second resist layer 32. As a result, the plating layer 20 is formed along the shapes of the resist layer 31 and the second resist layer 32 first. The side surface of the lead portion 22 is divided into an upper portion 22a and a lower portion 22b, the side surface 24b of the lower portion 22b has a straight portion in the vertical direction, and the side surface 24a of the upper portion 22a is along the periphery of the lead portion 22 It can be formed into a shape having an expanding taper shape.
めっきの種類は、特に限定は無い。例えば、導電性基板１０の表面上に、Ａｕめっき層、第２のＰｄめっき層、Ｎｉめっき層、Ｐｄめっきを順に層状に積み重ねる４層めっき、あるいは、更にＡｕめっきを行う５層めっき等を行う。ダイパッド部２１やリード部２２のめっき厚さも、特に限定は無いが、封止樹脂との密着性を考慮すれば、比較的硬度があり安価であるＮｉめっきを下段側から上段側をまたぐように厚さを設定することが好ましい。また、最表面には、ボンディング性の良いめっき層を必要最低限形成する。 The type of plating is not particularly limited. For example, on the surface of the conductive substrate 10, Au plating layer, second Pd plating layer, Ni plating layer, Pd plating are sequentially stacked in layers in a four-layer plating, or five-layer plating in which Au plating is further performed . The plating thickness of the die pad portion 21 and the lead portion 22 is not particularly limited, but considering the adhesion with the sealing resin, Ni plating is relatively hard and inexpensive so that it straddles the upper side from the lower side. It is preferable to set the thickness. In addition, on the outermost surface, a plated layer with good bondability is formed at the minimum necessary.
図６（ｅ）は、レジスト剥離工程の一例を示した図である。レジスト剥離工程では、硬化しているレジストマスク３５及びレジスト層３０を剥離する。これにより、めっき層２０からなるダイパッド部２１、リード部２２が形成される。 FIG. 6E is a view showing an example of the resist peeling step. In the resist peeling step, the hardened resist mask 35 and the resist layer 30 are peeled. Thereby, the die pad part 21 and the lead part 22 which consist of the plating layer 20 are formed.
ダイパッド部２１、リード部２２が形成された導電性基板１０を、必要に応じて所望の寸法に切断することにより、本発明の実施形態に係る半導体素子搭載用基板５０が得られる。 The semiconductor element mounting substrate 50 according to the embodiment of the present invention can be obtained by cutting the conductive substrate 10 on which the die pad portion 21 and the lead portion 22 are formed to a desired size, if necessary.
このように、上述の各工程を順に経ることにより、本発明の実施形態に係る半導体素子搭載用基板５０が作製される。 As described above, the semiconductor element mounting substrate 50 according to the embodiment of the present invention is manufactured by sequentially passing through the above-described steps.
［半導体装置の製造方法］
次に、図７を用いて、上述の製造方法によって作製された半導体素子搭載用基板５０を用いて半導体装置１００を製造する半導体装置１００の製造方法の一例について説明する。図７は、本発明の実施形態に係る半導体装置の製造方法の一例の一連の工程を示した図である。
[Method of Manufacturing Semiconductor Device]
Next, an example of a method of manufacturing the semiconductor device 100 for manufacturing the semiconductor device 100 using the semiconductor element mounting substrate 50 manufactured by the above-described manufacturing method will be described with reference to FIG. FIG. 7 is a diagram showing a series of steps in an example of the method of manufacturing a semiconductor device according to the embodiment of the present invention.
図７（ａ）は、半導体素子搭載工程の一例を示した図である。半導体素子搭載工程においては、半導体素子搭載用基板５０のダイパッド部２１上に半導体素子６０を搭載する。その際、半導体素子６０は、ダイパッド部２１上に、例えば、銀ペーストや接着剤等を用いて接着固定されてもよい。 FIG. 7A is a view showing an example of the semiconductor element mounting process. In the semiconductor element mounting step, the semiconductor element 60 is mounted on the die pad portion 21 of the semiconductor element mounting substrate 50. At that time, the semiconductor element 60 may be adhered and fixed onto the die pad portion 21 using, for example, silver paste, an adhesive, or the like.
図７（ｂ）は、ワイヤーボンディング工程の一例を示した図である。ワイヤーボンディング工程では、ワイヤーボンディングにより、ボンディングワイヤー７０を用いて半導体素子６０の電極６１とリード部２２とを電気的に接続して配線を形成する。 FIG. 7B is a view showing an example of a wire bonding process. In the wire bonding step, the electrodes 61 of the semiconductor element 60 and the lead portions 22 are electrically connected by wire bonding using the bonding wires 70 to form wirings.
図７（ｃ）は、樹脂封止工程の一例を示した図である。樹脂封止工程では、半導体素子搭載用基板５０の半導体素子６０を搭載した面全体を樹脂８０により封止する。 FIG.7 (c) is the figure which showed an example of the resin sealing process. In the resin sealing step, the entire surface of the semiconductor element mounting substrate 50 on which the semiconductor element 60 is mounted is sealed with a resin 80.
図７（ｄ）は、導電性基板除去工程の一例を示した図である。導電性基板除去工程では、樹脂封止部分から、導電性基板１０を除去する。導電性基板１０の除去方法は、溶解液を用いて、導電性基板１０を溶解除去する。あるいは、引き剥がし除去する方法もある。 FIG. 7D is a view showing an example of the conductive substrate removing step. In the conductive substrate removing step, the conductive substrate 10 is removed from the resin sealing portion. The method of removing the conductive substrate 10 dissolves and removes the conductive substrate 10 using a solution. Alternatively, there is also a method of peeling and removing.
図７（ｅ）は、切断工程の一例を示した図である。最後に、所定の半導体装置１００の寸法になるように切断し、半導体装置１００を完成させる。 FIG.7 (e) is the figure which showed an example of the cutting process. Finally, the semiconductor device 100 is cut to a predetermined size to complete the semiconductor device 100.
［光半導体素子搭載用基板および光半導体装置］
本発明は、半導体装置に限らず、光半導体装置にも適用することができる。以下、図８、図９も用いて説明する。
[Substrate for mounting optical semiconductor device and optical semiconductor device]
The present invention is applicable not only to semiconductor devices but also to optical semiconductor devices. Hereinafter, description will be made using FIGS. 8 and 9 as well.
図８は、本発明の実施形態に係る光半導体素子搭載用基板の一例を示す断面図である。光半導体素子搭載用基板５１は、半導体素子搭載用基板５０と構成は変わらない。図８に示されるように、導電性基板１０と、その表面１１上に配置された光半導体素子搭載用のダイパッド部２１と光半導体素子とワイヤボンディン等により接続するためのリード部２２とで構成されている。ダイパッド部２１とリード部２２は、対をなして形成され、それを一組として複数配置される。導電性基板１０は、表面１１上にめっき層２０が形成される基板であり、電気めっきによりめっき層２０を形成することが可能なように、導電性を有する材料から構成される。使用する導電性基板１０の材質は、導電性が得られれば特に限定はないが、一般的には金属材料が用いられ、例えば、ＣｕまたはＣｕ合金等が使用される。ダイパッド部２１やリード部２２は、導電性基板１０の片面（表面１１）にめっき加工により形成されためっき層２０である。ダイパッド部２１及びリード部２２の本発明の実施形態に係る光半導体素子搭載用基板５１の特徴については、半導体素子搭載用基板５０と同一である。 FIG. 8 is a cross-sectional view showing an example of the optical semiconductor element mounting substrate according to the embodiment of the present invention. The configuration of the optical semiconductor element mounting substrate 51 is the same as that of the semiconductor element mounting substrate 50. As shown in FIG. 8, a conductive substrate 10, a die pad portion 21 for mounting an optical semiconductor device disposed on the surface 11 thereof, and a lead portion 22 for connecting the optical semiconductor device by wire bonding or the like. It is configured. The die pad portion 21 and the lead portion 22 are formed in a pair, and a plurality of the die pad portion 21 and the lead portion 22 are disposed as one set. The conductive substrate 10 is a substrate on which the plating layer 20 is formed on the surface 11, and is made of a material having conductivity so that the plating layer 20 can be formed by electroplating. The material of the conductive substrate 10 to be used is not particularly limited as long as conductivity can be obtained, but generally, a metal material is used, and for example, Cu or a Cu alloy is used. The die pad portion 21 and the lead portion 22 are a plating layer 20 formed by plating on one surface (surface 11) of the conductive substrate 10. The features of the optical semiconductor element mounting substrate 51 according to the embodiment of the present invention of the die pad portion 21 and the lead portion 22 are the same as those of the semiconductor element mounting substrate 50.
次に、図９を用いて、光半導体装置について説明する。図９は、本発明の実施形態に係る光半導体装置１０１の一例の断面図である。 Next, an optical semiconductor device will be described with reference to FIG. FIG. 9 is a cross-sectional view of an example of the optical semiconductor device 101 according to the embodiment of the present invention.
図９に示すように、本発明の実施形態に係る光半導体装置１０１は、ダイパッド部２１に光半導体素子６２が搭載され、光半導体素子６２の電極６３とリード部２２とをボンディングワイヤー７０等を介して接続されている。また、光半導体素子６２及びボンディングワイヤー７０等の接続部を含む周辺部を取り囲む形で、ダイパッド部２１とリード部２２の上に外部樹脂８１が形成されている。また、ダイパッド部２１とリード部２２が対向する間の空間部分にも同時に外部樹脂８１が充填される。外部樹脂８１が取り囲んだ光半導体素子６２と電気的接続部周辺は、透明樹脂９０で充填されている。ダイパッド部２１及びリード部２２は、上面２３及び側面２４は外部樹脂８１及び透明樹脂９０により覆われているが、底面２５は露出している。また、図８で存在していた導電性基板１０は存在しない。導電性基板１０は、外部樹脂８１及び透明樹脂９０により封止が行われた後、除去されている。つまり、図８で示した光半導体素子搭載用基板５１は、まず、外部樹脂８１を封止後、ダイパッド部２１上に光半導体素子６２が搭載され、半導体素子６２の電極６３とリード部２２とがワイヤーボンディングによりボンディングワイヤー７０を介して接続された後、外部樹脂８１に開口された光半導体素子６２及びボンディングワイヤー７０等の接続部を含む周辺部を透明樹脂９０により封止が行われる。樹脂封止の後、導電性基板１０が除去されることにより、図９に示すような光半導体装置１０１が作製される。導電性基板１０の除去により露出したダイパッド部２１やリード部２２の底面２５は、外部機器とのはんだ接合するための外部端子となる。 As shown in FIG. 9, in the optical semiconductor device 101 according to the embodiment of the present invention, the optical semiconductor element 62 is mounted on the die pad portion 21, and the electrode 63 of the optical semiconductor element 62 and the lead portion 22 are bonded wire 70 etc. Connected through. In addition, an external resin 81 is formed on the die pad portion 21 and the lead portion 22 so as to surround the peripheral portion including the connection portion such as the optical semiconductor element 62 and the bonding wire 70. Also, the external resin 81 is simultaneously filled in the space between the die pad portion 21 and the lead portion 22 facing each other. The periphery of the optical semiconductor element 62 surrounded by the external resin 81 and the electrical connection portion is filled with a transparent resin 90. The upper surface 23 and the side surface 24 of the die pad portion 21 and the lead portion 22 are covered with the external resin 81 and the transparent resin 90, but the bottom surface 25 is exposed. Moreover, the conductive substrate 10 which existed in FIG. 8 does not exist. The conductive substrate 10 is removed after sealing with the external resin 81 and the transparent resin 90. That is, the optical semiconductor element mounting substrate 51 shown in FIG. 8 is first sealed with the external resin 81 and then the optical semiconductor element 62 is mounted on the die pad portion 21, and the electrode 63 of the semiconductor element 62 and the lead portion 22 Are connected through the bonding wire 70 by wire bonding, and then the peripheral portion including the connection portion such as the optical semiconductor element 62 and the bonding wire 70 opened in the external resin 81 is sealed with the transparent resin 90. After resin sealing, the conductive substrate 10 is removed, whereby an optical semiconductor device 101 as shown in FIG. 9 is manufactured. The bottom surface 25 of the die pad portion 21 and the lead portion 22 exposed by the removal of the conductive substrate 10 serves as an external terminal for soldering to an external device.
光半導体装置１０１は、ダイパッド部２１とリード部２２が対に配置されている。光半導体装置１０１の形状は小さいため、外部樹脂８１とダイパッド部２１及びリード部２２との密着性は重要である。本発明の実施形態に係る光半導体装置１０１のダイパッド部２１及びリード部２２のように、上側にテーパー形状を有することで外部樹脂８１との密着性を向上させることが可能である。 In the optical semiconductor device 101, a die pad portion 21 and a lead portion 22 are arranged in pairs. Since the shape of the optical semiconductor device 101 is small, the adhesion between the external resin 81 and the die pad portion 21 and the lead portion 22 is important. Similar to the die pad portion 21 and the lead portion 22 of the optical semiconductor device 101 according to the embodiment of the present invention, the adhesion with the external resin 81 can be improved by having a tapered shape on the upper side.
更に、図５で説明したように、リード部２２をリード部２６に置き換え、ダイパッド部２１とリード部２６の外形形状の各辺に凹凸を形成し、かつ、リード部２６の側面は、上段部２６ａと下段部２６ｂに分かれ、下段部２６ｂの側面２７ｂは垂直方向に直線部を有し、上段部２６ａの側面２７ａは、リード部周縁に沿い上部が広がるテーパー形状を有するとともに、その側面２７の一部には、上段部２６ａと下段部２６ｂの境界（上段部２６ａの底面２６ｄ）に水平部２６ｅを有してもよい。この上段部２６ａの底面２６ｄの一部に水平部２６ｅを有する箇所は、前述のリード部２６の下端部２６ｂの底面形状の各辺に凹凸形状を付加した凹部２７ｃに形成することができる。この凹部２７ｃに形成することで、凹部２７ｃの下面にも外部樹脂８１を充填することができ、より外部樹脂８１との密着性を向上させることができる。これにより、光半導体装置１０１は、より小型化、薄型化を図ることが可能となる。 Furthermore, as described in FIG. 5, the lead portion 22 is replaced with the lead portion 26 and irregularities are formed on each side of the outer shape of the die pad portion 21 and the lead portion 26, and the side surface of the lead portion 26 is the upper portion The side surface 27b of the lower portion 26b has a straight portion in the vertical direction, and the side surface 27a of the upper portion 26a has a tapered shape in which the upper part extends along the periphery of the lead portion. It may have a horizontal portion 26e at a boundary between the upper portion 26a and the lower portion 26b (the bottom surface 26d of the upper portion 26a). A portion having a horizontal portion 26e on a part of the bottom surface 26d of the upper portion 26a can be formed as a concave portion 27c in which a concavo-convex shape is added to each side of the bottom surface of the lower end portion 26b of the lead portion 26 described above. By forming the recess 27 c, the outer resin 81 can be filled also on the lower surface of the recess 27 c, and adhesion with the outer resin 81 can be further improved. As a result, the optical semiconductor device 101 can be further miniaturized and thinned.
［光半導体素子搭載用基板の製造方法および光半導体装置の製造方法］
次に、光半導体素子搭載用基板５１の製造方法および光半導体装置１０１の製造方法について説明する。光半導体素子搭載用基板５１の製造方法は、半導体素子搭載用基板５０の製造方法と同一である。なお、ダイパッド部２１及びリード部２２のめっき層２０のめっきの種類については、光半導体装置１０１の場合、発光素子（光半導体素子）からの光を効率的に反射させるため、反射率の高い貴金属めっきが最外層に施される。最外層のめっき層は、ＡｇまたはＡｇ合金めっきが光反射率の点から好適である。例えば、導電性基板１０の表面上に、Ａｕめっき層、Ｐｄめっき層、Ｎｉめっき層、Ａｕめっき層、Ａｇめっき層を順に層状に積み重ねる５層めっき等を行うことができる。
[Method of Manufacturing Substrate for Mounting Optical Semiconductor Device and Method of Manufacturing Optical Semiconductor Device]
Next, a method of manufacturing the optical semiconductor element mounting substrate 51 and a method of manufacturing the optical semiconductor device 101 will be described. The method of manufacturing the optical semiconductor element mounting substrate 51 is the same as the method of manufacturing the semiconductor element mounting substrate 50. The type of plating of the plating layer 20 of the die pad portion 21 and the lead portion 22 is, in the case of the optical semiconductor device 101, a noble metal having a high reflectance to efficiently reflect the light from the light emitting element (optical semiconductor element). Plating is applied to the outermost layer. The plating layer of the outermost layer is preferably Ag or Ag alloy plating from the viewpoint of light reflectance. For example, it is possible to perform five-layer plating or the like in which an Au plating layer, a Pd plating layer, an Ni plating layer, an Au plating layer, and an Ag plating layer are stacked in order on the surface of the conductive substrate 10.
光半導体装置１０１の製造方法については、上述した光半導体素子搭載用基板５１を使用し、外部樹脂８１を樹脂封止する。外部樹脂８１は、光半導体素子６２及びボンディングワイヤー７０等の接続部を含む周辺部を取り囲む形で、ダイパッド部２１とリード部２２の上に充填されている。また、ダイパッド部２１とリード部２２が対向する両者の間の空間部分にも同時に外部樹脂８１が充填される。その後、ダイパッド部２１上に光半導体素子６２が搭載され、光半導体素子６２の電極６３とリード部２２とがワイヤーボンディングによりボンディングワイヤー７０を介して接続される。次に、外部樹脂８１に開口された所定の中央領域に設けられた、光半導体素子６２及びボンディングワイヤー７０等の接続部を含む周辺部を、透明樹脂９０により封止する。樹脂封止の後、導電性基板１０が除去される。最後に所定の寸法になるように切断する。これにより光半導体装置１０１が作製される。 Regarding the method of manufacturing the optical semiconductor device 101, the external resin 81 is resin-sealed using the above-described optical semiconductor element mounting substrate 51. The external resin 81 is filled on the die pad portion 21 and the lead portion 22 so as to surround the peripheral portion including the connection portion such as the optical semiconductor element 62 and the bonding wire 70. Also, the external resin 81 is simultaneously filled in the space portion between the die pad portion 21 and the lead portion 22 facing each other. Thereafter, the optical semiconductor element 62 is mounted on the die pad portion 21, and the electrode 63 of the optical semiconductor element 62 and the lead portion 22 are connected to each other through the bonding wire 70 by wire bonding. Next, the peripheral portion including the connection portion such as the optical semiconductor element 62 and the bonding wire 70 provided in a predetermined central region opened in the external resin 81 is sealed with the transparent resin 90. After resin sealing, the conductive substrate 10 is removed. Finally, it is cut to a predetermined size. Thus, the optical semiconductor device 101 is manufactured.
以下、本発明の実施形態に係る半導体素子搭載用基板５０、５１及び半導体装置１００、１０１を作製して実施した実施例について説明する。なお、理解の容易のため、上述の実施形態の構成要素に対応する構成要素については、実施形態と同一の参照符号を付すこととする。 Hereinafter, an example in which the semiconductor element mounting substrates 50 and 51 and the semiconductor devices 100 and 101 according to the embodiment of the present invention are manufactured and implemented will be described. In addition, about the component corresponding to the component of the above-mentioned embodiment, suppose that the same referential mark as embodiment is attached for easy understanding.
［実施例１］
導電性基材１０として板厚０．２ｍｍのＳＵＳ板（ＳＵＳ４３０）を幅１４０ｍｍの長尺板状に加工し、次に導電性基板１０の表面に厚み０．０１５ｍｍ感光性ドライフィルムレジスト（旭化成イーマテリアルズ社製ＡＤＨ）を、ラミネートロールを用いて貼り付けた。引き続き、その上に、厚み０．０５ｍｍの感光性ドライフィルムレジスト（旭化成イーマテリアルズ社製ＡＱ）、厚み０．０２５ｍｍ感光性ドライフィルムレジスト（旭化成イーマテリアルズ社製ＡＤＨ）を順に貼り付けた。裏面には、厚み０．０４０ｍｍ感光性ドライフィルムレジスト（旭化成イーマテリアルズ社製ＡＱ）をラミネートロールで貼り付けた。
Example 1
A 0.2 mm thick SUS plate (SUS 430) is processed into a long plate shape having a width of 140 mm as the conductive substrate 10, and then a 0.015 mm thick photosensitive dry film resist (Asahi Kasei E.) is formed on the surface of the conductive substrate 10. Materials company ADH) was stuck using the lamination roll. Subsequently, a photosensitive dry film resist having a thickness of 0.05 mm (AQ manufactured by Asahi Kasei E-Materials, Inc.) and a photosensitive dry film resist having a thickness of 0.025 mm (ADH manufactured by Asahi Kasei E-Materials, Inc.) were sequentially adhered thereon. On the back surface, a 0.040 mm-thick photosensitive dry film resist (AQ manufactured by Asahi Kasei E-Materials Co., Ltd.) was attached with a laminating roll.
次に、表面側に半導体素子搭載用のダイパッド部２１と外部と接続するためのリード部２２の所望のパターン、裏面側には裏面全面を覆うパターンを形成すべく、パターンを形成したガラスマスクをドライフィルムレジストの上に被せ、紫外光で露光した。表面側の露光は、第１のレジスト層３１、第３のレジスト層３３が感光し、第２のレジスト層３２が感光しない波長で行った。このため、表面側の第２のレジスト層３２である厚み０．０５ｍｍのドライフィルムは未露光状態になった。裏面側の露光は裏面のレジストが感光する波長で行った。 Next, a glass mask on which a pattern is formed to form a desired pattern of the lead portion 22 for connecting the semiconductor chip mounting die pad portion 21 to the outside on the front side and a pattern covering the entire back side on the back side is used. The dry film resist was covered and exposed to ultraviolet light. The exposure on the surface side was performed at a wavelength at which the first resist layer 31 and the third resist layer 33 were exposed and the second resist layer 32 was not exposed. For this reason, the dry film with a thickness of 0.05 mm, which is the second resist layer 32 on the front surface side, is unexposed. The exposure on the back side was performed at a wavelength at which the resist on the back side was exposed.
なお、リード部２２及びダイパッド部２１の底面形状は矩形で、角部はＲ形状（丸め形状）とした。 The bottoms of the leads 22 and the die pad 21 are rectangular, and the corners are rounded (rounded).
その後、炭酸ナトリウム溶液を用いて、紫外光の照射が遮られて感光しなかった未硬化のドライフィルムレジストを溶かす現像処理を行った。現像時間、現像液の吐出圧力等適宜調整することで、第２のレジスト層３２のテーパーの角度が約４５°になるように設定した。その後、露光により第２のレジスト層を硬化処理した。 Thereafter, using a sodium carbonate solution, development treatment was performed to dissolve the uncured dry film resist which was not exposed due to the blocking of the irradiation of the ultraviolet light. The taper angle of the second resist layer 32 was set to be about 45 ° by appropriately adjusting the developing time, the discharge pressure of the developing solution, and the like. Thereafter, the second resist layer was cured by exposure.
次に、レジスト層が除去されて開口部３４が形成された導電性基材１０の露出部表面に、電気めっきを行った。ダイパッド部２１及びリード部２２を形成するため、Ａｕめっきを約０．０２μｍ、第Ｐｄめっきを０．０２μｍ、Ｎｉめっきを４０μｍ、Ｐｄめっきを０．０５μｍ順次施した。めっき層の厚さは、第２のレジスト層３２の２／３を目安に設定した。 Next, electroplating was performed on the surface of the exposed portion of the conductive substrate 10 in which the resist layer was removed and the opening 34 was formed. In order to form the die pad portion 21 and the lead portion 22, about 0.02 μm of Au plating, 0.02 μm of Pd plating, 40 μm of Ni plating, and 0.05 μm of Pd plating were sequentially applied. The thickness of the plating layer was set to 2/3 of the second resist layer 32 as a guide.
最後に、水酸化ナトリウム溶液でドライフィルムレジスト３０〜３３を剥離して、導電性基板上１０にダイパッド部２１及びリード部２２を形成した。 Finally, the dry film resists 30 to 33 were peeled off with a sodium hydroxide solution to form the die pad portion 21 and the lead portion 22 on the conductive substrate 10.
その後、所定寸法に切断することにより、本発明の実施例１に係る半導体素子搭載用基板５０を得た。 Thereafter, the substrate was cut into a predetermined size to obtain a semiconductor element mounting substrate 50 according to Example 1 of the present invention.
次いで、作製した半導体素子搭載用基板５０に半導体素子６０を搭載し、半導体素子６０とリード部２２をワイヤーボンディング７０で接続し、半導体素子６０が搭載されている面を樹脂８０で封止した後、樹脂封止部分から導電性基材１０を引き剥がし除去した。最後に、所定の半導体装置１００の寸法になるように切断し、実施例１に係る半導体装置１００を完成させた。 Next, the semiconductor element 60 is mounted on the manufactured semiconductor element mounting substrate 50, the semiconductor element 60 and the lead portion 22 are connected by the wire bonding 70, and the surface on which the semiconductor element 60 is mounted is sealed with the resin 80. Then, the conductive substrate 10 was peeled and removed from the resin-sealed portion. Finally, the semiconductor device 100 was cut to a predetermined size to complete the semiconductor device 100 according to the first embodiment.
［実施例２］
実施例２は、実施例１においてパターンをリード部２６及びダイパッド部２１の矩形の各辺にジグザグ（又は波型）の凹凸形状を付加した。また、ジグザグの各頂点はＲ形状とした。凹部２７ｃの長さは、０．０３ｍｍとした。また、現像工程では、現像時間、現像液の吐出圧力等適宜調整することで、凹部２７ｃに該当する上段部２６ａと下段部２６ｂの境界（上段部２６ａの底面）に水平部を設けるようにした。なお、現像時間は、実施例１より長くした。その他の条件は、実施例１と同様である。
Example 2
In the second embodiment, in the first embodiment, a zigzag (or corrugated) uneven shape is added to each side of the rectangles of the lead portion 26 and the die pad portion 21 in the pattern. In addition, each vertex of the zigzag has an R shape. The length of the recess 27c was 0.03 mm. In the development step, the horizontal portion is provided at the boundary between the upper portion 26a and the lower portion 26b (bottom surface of the upper portion 26a) corresponding to the recess 27c by appropriately adjusting the development time, the discharge pressure of the developer, and the like. . The developing time was longer than that of Example 1. The other conditions are the same as in Example 1.
図１０は、実施例２に係る半導体素子搭載用基板５１のリード部２６の上面からの拡大図で、リード部の側面の一部の拡大図である。図１０に示されるように、波型の側面を有する柱状の下段部２６ｂの上面上にやはり波型の側面を有する上段部２６ａが設けられ、上段部２６ａの側面が側方及び上方に張り出してテーパー状に形成されていることが分かる。かかる構成により、上段部２６ａの樹脂８０への引っ掛かりが良好となり、樹脂８０とリード部２６との密着性を向上させ、リード部２６の脱落及び剥離を防止することができる。 FIG. 10 is an enlarged view from the top surface of the lead portion 26 of the semiconductor element mounting substrate 51 according to the second embodiment, and is an enlarged view of a part of the side surface of the lead portion. As shown in FIG. 10, an upper portion 26a having a side surface is also provided on the upper surface of a columnar lower portion 26b having a side surface, and the side surface of the upper portion 26a protrudes laterally and upward. It can be seen that it is formed in a tapered shape. With this configuration, the upper end portion 26a can be easily caught on the resin 80, and the adhesion between the resin 80 and the lead portion 26 can be improved, and the detachment and peeling of the lead portion 26 can be prevented.
図１１は、実施例２に係る半導体素子搭載用基板５１のリード部２６の裏面からの拡大図で、リード部の裏面側における側面の一部の拡大図である。即ち、リード部２６を導電性基板１０から剥離し、リード部２６のみを裏面から示した図である。図１１に示されるように、柱状の下段部２６ｂの上面上（図１１では下方）に設けられた上段部２６ａの底面２６ｄが下段部２６ｂの上面を包含しており、波型の凹部において平坦面（水平面）２６ｅが形成されている。かかる平坦面２６ｅを上端部２６ａの底面２６ｄに設けることにより、樹脂８０の引っ掛かりが良好になり、樹脂８０とリード部２６との密着性が大幅に向上する。また、上段部２６ａの側面２７ａもテーパー状となっており、樹脂８０とリード部２６との密着性を向上させることができる。 FIG. 11 is an enlarged view from the back surface of the lead portion 26 of the semiconductor element mounting substrate 51 according to the second embodiment, and is an enlarged view of a part of the side surface on the back surface side of the lead portion. That is, it is the figure which peeled the lead part 26 from the conductive substrate 10, and showed only the lead part 26 from the back surface. As shown in FIG. 11, the bottom surface 26d of the upper portion 26a provided on the upper surface (lower in FIG. 11) of the columnar lower portion 26b includes the upper surface of the lower portion 26b, and is flat in the corrugated recess. A surface (horizontal surface) 26e is formed. By providing the flat surface 26e on the bottom surface 26d of the upper end portion 26a, the resin 80 can be easily caught and adhesion between the resin 80 and the lead portion 26 is significantly improved. Further, the side surface 27a of the upper portion 26a is also tapered, and the adhesion between the resin 80 and the lead 26 can be improved.
［実施例３］
実施例３は、光半導体素子搭載用基板５１を作製した例である。実施例３では、実施例１におけるパターンを光半導体装置１０１用のダイパッド部２１とリード部２２が対になった形状に設定した。めっき層２０は、実施例１のめっき層の最表層にＡｇめっき１μｍを追加した。その他は、実施例１と同じである。
[Example 3]
The third embodiment is an example in which the optical semiconductor element mounting substrate 51 is manufactured. In the third embodiment, the pattern in the first embodiment is set to a shape in which the die pad portion 21 and the lead portion 22 for the optical semiconductor device 101 are paired. In the plating layer 20, 1 μm of Ag plating was added to the outermost layer of the plating layer of Example 1. Others are the same as in the first embodiment.
実施例３の光半導体装置１０１を作製すべく、上で作製した光半導体素子搭載用基板５１を用いて、光半導体素子６２及びボンディングワイヤー７０等の接続部を含む周辺部を取り囲む形で、ダイパッド部２１とリード部２２の外側の表面上に外部樹脂８１を形成した。また、ダイパッド部２１とリード部２２とが対向する間隔をなす空間部分にも同時に外部樹脂８１を形成した。その後、ダイパッド部２１上に光半導体素子６２を搭載し、光半導体素子６２の電極６３とリード部２２とをワイヤーボンディングによりボンディングワイヤー７０を介して接続した。次に、外部樹脂８１に開口された光半導体素子６２及びボンディングワイヤー７０等の接続部を含む周辺部（所定の中央領域）を、透明樹脂９０により封止した。樹脂封止の後、導電性基板１０を除去した。最後に所定の寸法に切断した。これにより光半導体装置１０１を完成させた。 In order to manufacture the optical semiconductor device 101 according to the third embodiment, a die pad is formed so as to surround the peripheral portion including the connection portions such as the optical semiconductor element 62 and the bonding wire 70 using the optical semiconductor element mounting substrate 51 manufactured above. An external resin 81 was formed on the outer surface of the portion 21 and the lead portion 22. In addition, the external resin 81 was simultaneously formed in the space portion where the die pad portion 21 and the lead portion 22 face each other. Thereafter, the optical semiconductor element 62 is mounted on the die pad portion 21, and the electrode 63 of the optical semiconductor element 62 and the lead portion 22 are connected to each other through the bonding wire 70 by wire bonding. Next, the peripheral portion (predetermined central region) including the connection portions such as the optical semiconductor element 62 and the bonding wire 70 opened in the external resin 81 was sealed with the transparent resin 90. After resin sealing, the conductive substrate 10 was removed. Finally, it was cut to predetermined dimensions. Thus, the optical semiconductor device 101 was completed.
［比較例１］
比較例１では、レジスト被覆工程で、導電性基板の両面に厚み０．０２５ｍｍ感光性ドライフィルムレジスト（旭化成イーマテリアルズ社製ＡＱ−４０９６）をラミネートロール貼り付け、露光現像をおこなった。めっき工程では、レジスト層を超えてめっき層を形成した。その他条件は、実施例１と同様である。
Comparative Example 1
In Comparative Example 1, a photosensitive dry film resist (AQ-4096 manufactured by Asahi Kasei E-Materials Co., Ltd.) was laminated on both sides of a conductive substrate in a resist coating process, and exposure development was performed. In the plating step, a plating layer was formed beyond the resist layer. Other conditions are the same as in the first embodiment.
［比較例２］
比較例２では、レジスト被覆工程で導電性基板の表面に厚み０．０５ｍｍの感光性ドライフィルムレジスト（旭化成イーマテリアルズ社製ＡＱ−４０９６）を貼り付けた。裏面には、厚み０．０２５ｍｍ感光性ドライフィルムレジスト（旭化成イーマテリアルズ社製ＡＱ−４０９６）をラミネートロールで貼り付け、露光工程では散乱紫外光用いて露光を行った。その後、現像を行った。散乱紫外光で露光することで、レジスト層は半露光状態となり、テーパー形状のレジストが形成される。めっき工程では、形成されたテーパー形状のレジストマスクの開口部にめっきを行い、逆台形形状のリード部を作製した。その他の条件は実施例１と同じである。
Comparative Example 2
In Comparative Example 2, a photosensitive dry film resist (AQ-4096 manufactured by Asahi Kasei E-Materials Co., Ltd.) having a thickness of 0.05 mm was attached to the surface of the conductive substrate in the resist coating step. On the back surface, a 0.025 mm thick photosensitive dry film resist (AQ-4096 manufactured by Asahi Kasei E-materials Co., Ltd.) was attached by a laminating roll, and exposure was performed using scattered ultraviolet light in the exposure step. Thereafter, development was performed. By exposure to scattered ultraviolet light, the resist layer is in a semi-exposed state, and a tapered resist is formed. In the plating step, the opening portion of the formed resist mask having a tapered shape was plated to produce a lead portion having an inverted trapezoidal shape. The other conditions are the same as in Example 1.
［評価］
実施例１、実施例２、実施例３及び比較例１、比較例２については、以下の方法で評価を行った。
[Evaluation]
About Example 1, Example 2, Example 3, Comparative example 1, and Comparative example 2, evaluation was performed with the following method.
半導体素子搭載用基板において、リード部の底面形状寸法を各２０リード測定し、そのばらつきを確認した。 In the semiconductor element mounting substrate, the bottom shape and dimensions of the lead portions were measured for 20 leads each, and the variation was confirmed.
実施例１、比較例１においては、設定値±０．００３ｍｍ以内、実施例２及び実施例３は設定値±０．００４ｍｍと良好であったが、比較例２では、設定値±０．０１ｍｍとばらつきが大きかった。 In Example 1 and Comparative Example 1, the set value was ± 0.003 mm or less, and in Example 2 and Example 3, the set value was ± 0.004 mm, but in Comparative Example 2, the set value ± 0.01 mm. And the variation was large.
また、半導体素子搭載用基板の製作工程のレジスト剥離工程で、レジスト残り不具合があるか顕微鏡で１００枚観察した。その結果、実施例１及び実施例２、実施例３、比較例２に関してはレジスト残りの発生が無かったが、比較例１では、一部リード部に発生が見られた。 Further, in the resist peeling process in the manufacturing process of the substrate for mounting a semiconductor element, 100 sheets were observed with a microscope to see if there is a defect in the resist remaining. As a result, in Examples 1 and 2 and Example 3 and Comparative Example 2, no resist residue was generated, but in Comparative Example 1, generation was partially observed in the lead portion.
また、この半導体素子搭載用基板を使用して半導体素子を搭載し樹脂封止後、導電性基板を引き剥がし除去工程で、リード部が導電性基板に残る不具合があるか観察を行った。この結果、実施例１、実施例２、実施例３、比較例１、比較例２では封止樹脂と導電性基板との間でリード部が導電性基板に残る不具合はなく良好であった。実施例１、実施例２及び実施例３においても十分封止樹脂と密着性を確保していることが確認できた。 Moreover, after mounting a semiconductor element using this substrate for mounting a semiconductor element and resin-sealing, it was observed in the peeling removal process of the conductive substrate whether there is a defect that the lead portion remains on the conductive substrate. As a result, in Example 1, Example 2, Example 3, Comparative Example 1, and Comparative Example 2, there was no problem that the lead portion remained on the conductive substrate between the sealing resin and the conductive substrate, and it was good. Also in Example 1, Example 2, and Example 3, it has confirmed that sufficient sealing resin and adhesiveness were ensured.
以上、本発明の好ましい実施形態及び実施例について詳説したが、本発明は、上述した実施形態及び実施例に制限されることはなく、本発明の範囲を逸脱することなく、上述した実施形態及び実施例に種々の変形及び置換を加えることができる。 Although the preferred embodiments and examples of the present invention have been described above in detail, the present invention is not limited to the above-described embodiments and examples, and the above-described embodiments and examples are possible without departing from the scope of the present invention. Various modifications and substitutions may be made to the embodiments.
１０ 導電性基板
２０ めっき層
２１ ダイパッド部
２２、２６ リード部
２２ａ、２６ａ 上段部
２２ｂ、２６ｂ 下段部
２３ 上面
２４、２４ａ、２４ｂ、２７、２７ａ、２７ｂ 側面
２５ 裏面
２６ｃ 上段部の上面
２６ｄ 上段部の底面
２６ｅ 水平部
２７ｃ 凹部
３１ 第１のレジスト層
３２ 第２のレジスト層
３３ 第３のレジスト層
３４ 開口部
３５ めっき用レジストマスク
５０ 半導体素子搭載用基板
５１ 光半導体素子搭載用基板
６０ 半導体素子
６１、６３ 電極
６２ 光半導体素子
７０ ボンディングワイヤー
８０ 樹脂
８１ 外部樹脂
９０ 透明樹脂
１００ 半導体装置
１０１ 光半導体装置
DESCRIPTION OF SYMBOLS 10 Conductive substrate 20 plating layer 21 die pad part 22, 26 lead part 22a, 26a upper part 22b, 26b lower part 23 upper surface 24, 24a, 24b, 27, 27a, 27b side surface 25 back surface 26c upper surface of upper part 26d upper part Bottom surface 26e Horizontal portion 27c Recession 31 First resist layer 32 Second resist layer 33 Third resist layer 34 Opening 35 Plating resist mask 50 Semiconductor device mounting substrate 51 Photo semiconductor device mounting substrate 60 Semiconductor device 61, 63 electrode 62 optical semiconductor element 70 bonding wire 80 resin 81 external resin 90 transparent resin 100 semiconductor device 101 optical semiconductor device
Claims (16)
該導電性基板の表面上に設けられた半導体素子搭載領域と、
該半導体素子搭載領域の周囲の前記導電性基板の前記表面上の所定領域に設けられためっき層からなるリード部と、を有し、
該リード部は、前記導電性基板の前記表面と略垂直な側面を有して前記表面から柱状に上方に延びる下段部と、
該下段部の上面上に底面を有し、該底面からテーパー状に上方及び側方に広がる側面を有する上段部と、を有し、
前記リード部の前記下段部の前記側面は凹凸を有する平面形状を有し、
前記リード部の前記上段部の前記底面は、前記下段部の上面を包含する平面形状を有し、前記凹凸の凹部を覆う領域が露出した平坦面を有する半導体素子搭載用基板。 A conductive substrate that can be removed after the semiconductor element is mounted,
A semiconductor element mounting region provided on the surface of the conductive substrate;
And a lead portion comprising a plating layer provided on a predetermined area on the surface of the conductive substrate around the semiconductor element mounting area;
The lead portion has a side surface substantially perpendicular to the surface of the conductive substrate, and a lower portion extending upward from the surface in a columnar shape;
Has a bottom surface on the upper surface of the lower step portion, it has a, and upper portion having a side surface extending upwardly and laterally tapered from the bottom surface,
The side surface of the lower portion of the lead portion has a planar shape having unevenness,
The bottom surface of the upper portion of the lead portion, the have include planar shape an upper surface of the lower portion, a semiconductor device mounting board region covering the concave portion of the irregularities to have a flat surface that is exposed.
該半導体素子の周囲の所定領域に設けられ、形状の異なる上段部と下段部とを有するめっき層からなるリード部と、
前記半導体素子の電極と前記リード部の前記上段部の上面とを電気的に接続する接続手段と、
少なくとも前記リード部の前記下段部の底面が露出するように前記半導体素子、前記リード部及び前記接続手段を封止する樹脂と、を有し、
前記リード部の前記下段部は、前記底面から上方に垂直に延びる側面を有する柱状形状を有し、
前記リード部の前記上段部は、前記下段部の上面上に底面を有し、該底面からテーパー状に上方及び側方に側面が広がるテーパー形状を有し、
前記リード部の前記下段部の前記側面は波型の凹凸を有する平面形状を有し、
前記リード部の前記上段部の前記底面は、前記下段部の上面を包含する平面形状を有し、前記波型の凹部を覆う領域が露出した平坦面を有する半導体装置。 A semiconductor element,
A lead portion comprising a plated layer provided in a predetermined region around the semiconductor element and having an upper portion and a lower portion having different shapes;
Connection means for electrically connecting the electrode of the semiconductor element and the upper surface of the upper portion of the lead portion;
A resin sealing the semiconductor element, the lead portion, and the connection unit such that at least a bottom surface of the lower portion of the lead portion is exposed;
The lower portion of the lead portion has a columnar shape having side surfaces extending vertically upward from the bottom surface,
The upper portion of the lead portion has a bottom surface on an upper surface of the lower portion, it has a tapered shape in which side surfaces extending upwardly and laterally tapered from the bottom surface,
The side surface of the lower portion of the lead portion has a planar shape having a corrugated unevenness,
Said bottom surface of said upper portion of said lead portion has a planar shape including an upper surface of said lower portion, said wave-type semiconductor device region covering the recess to have a flat surface that is exposed.
該ダイパッド部は、前記リード部と同様の形状を有している請求項７乃至９のいずれか一項に記載の半導体装置。 The semiconductor element is mounted on a die pad portion made of a plating layer and provided.
The semiconductor device according to any one of claims 7 to 9 , wherein the die pad portion has the same shape as the lead portion.
前記ダイパッド部と対に設けられ、形状の異なる上段部と下段部とを有するめっき層からなるリード部と、
前記ダイパッド部に搭載された光半導体素子と、
該光半導体素子の電極と前記リード部の前記上段部の上面とを電気的に接続する接続手段と、
前記光半導体素子及び前記接続手段を含む前記ダイパッド部上及び前記リード部上の所定の中央領域を封止する透明樹脂と、
前記ダイパッド部及び前記リード部の底面が露出するように、前記ダイパッド部及び前記リード部の底面以外の前記ダイパッド部と前記リード部との間の領域と、前記ダイパッド部及び前記リード部の所定の外側領域とを封止する外部樹脂と、を有し、
前記リード部の前記下段部は、前記底面から上方に垂直に延びる側面を有する柱状形状を有し、
前記リード部の前記上段部は、前記下段部の上面上に底面を有し、該底面からテーパー状に上方及び側方に側面が広がるテーパー形状を有し、
前記リード部の前記下段部の前記側面は凹凸を有する平面形状を有し、
前記リード部の前記上段部の前記底面は、前記下段部の上面を包含する平面形状を有し、前記凹凸の凹部を覆う領域が露出した平坦面を有する光半導体装置。 A die pad portion having a region for mounting an optical semiconductor device;
A lead portion comprising a plated layer provided in pairs with the die pad portion and having an upper portion and a lower portion of different shapes;
An optical semiconductor element mounted on the die pad portion;
Connection means for electrically connecting the electrode of the optical semiconductor element and the upper surface of the upper portion of the lead portion;
A transparent resin for sealing a predetermined central region on the die pad portion including the optical semiconductor element and the connection means and on the lead portion;
A region between the die pad portion and the lead portion other than the die pad portion and the bottom surface of the lead portion so that the bottom surface of the die pad portion and the lead portion is exposed, and a predetermined portion of the die pad portion and the lead portion And an outer resin sealing the outer region,
The lower portion of the lead portion has a columnar shape having side surfaces extending vertically upward from the bottom surface,
The upper portion of the lead portion has a bottom surface on an upper surface of the lower portion, it has a tapered shape in which side surfaces extending upwardly and laterally tapered from the bottom surface,
The side surface of the lower portion of the lead portion has a planar shape having unevenness,
It said bottom surface of said upper portion of said lead portion has a planar shape including upper surface of the lower portion, the optical semiconductor device region covering to have a flat surface which is exposed to the recess of the uneven.
第１の露光により、前記第１及び第３のレジスト層を硬化させるとともに、前記第２のレジスト層を硬化させていない状態で現像を行い、前記第２のレジスト層の上部が前記第１及び第３のレジスト層よりも内側に削れ、テーパー状の形状を有するパターンを形成する工程と、
第２の露光により、第２のレジスト層を硬化させる工程と、
前記第１乃至第３のレジスト層からなるパターンをめっきマスクとしてめっきを行い、前記第１のレジスト層により形成された部分が柱状形状を有し、前記第２のレジスト層により形成された部分がテーパー形状を有するめっき層を形成する工程と、
前記めっきマスクを除去する工程と、を有する半導体素子搭載用基板の製造方法。 A first resist layer coated with a first resist having a first photosensitive wavelength on the surface of a conductive substrate, and a second resist coated with a second photosensitive wavelength on the first resist layer Forming a second resist layer, a third resist layer coated with the first resist on the second resist layer in sequence;
While the first and third resist layers are cured by the first exposure, development is performed in a state where the second resist layer is not cured, and the upper portion of the second resist layer is the first and second resist layers. Forming a pattern having a tapered shape by being scraped inward of the third resist layer;
Curing the second resist layer by the second exposure;
Plating is performed using the pattern formed of the first to third resist layers as a plating mask, the portion formed of the first resist layer has a columnar shape, and the portion formed of the second resist layer is Forming a plating layer having a tapered shape;
And removing the plating mask.
該半導体素子の電極と前記めっき層の上面とを接続手段により電気的に接続する工程と、
前記めっき層の底面及び前記半導体素子の前記電極が設けられていない面のみが露出するように、前記半導体素子、前記めっき層及び前記接続手段を樹脂で封止する工程と、を有する半導体装置の製造方法。 A step of mounting a semiconductor element on a predetermined semiconductor element mounting region of a semiconductor element mounting substrate manufactured by the method of manufacturing a semiconductor element mounting substrate according to claim 13 .
Electrically connecting the electrode of the semiconductor element and the upper surface of the plating layer by connection means;
Sealing the semiconductor element, the plating layer, and the connection means with a resin such that only the bottom surface of the plating layer and the surface of the semiconductor element on which the electrode is not provided are exposed Production method.
ダイパッド部に、半導体素子を搭載する工程と、
該半導体素子の電極と前記リード部の上面とを接続手段により電気的に接続する工程と、
前記リード部及び前記ダイパッド部の底面のみが露出するように、前記半導体素子、前記リード部及び前記接続手段を樹脂で封止する工程と、を有する半導体装置の製造方法。 The plated layer of the semiconductor element mounting substrate manufactured by the method of manufacturing a semiconductor element mounting substrate according to claim 13 is a die pad portion and a lead portion,
Mounting a semiconductor element on the die pad portion;
Electrically connecting the electrode of the semiconductor element and the upper surface of the lead portion by connection means;
Sealing the semiconductor element, the lead portion and the connection means with a resin such that only the bottom surface of the lead portion and the bottom surface of the die pad portion are exposed.
ダイパッド部に、光半導体素子を搭載する工程と、
該光半導体素子の電極と前記リード部の上面とを接続手段により電気的に接続する工程と、
前記リード部及び前記ダイパッド部の底面のみが露出するように、前記光半導体素子及び前記接続手段が設けられた所定の中央領域よりも外側の領域及び前記リード部と前記ダイパッド部との間の領域を外部樹脂で封止する工程と、
前記所定の中央領域を透明樹脂で封止する工程と、を有する光半導体装置の製造方法。 The plated layer of the semiconductor element mounting substrate manufactured by the method of manufacturing a semiconductor element mounting substrate according to claim 13 is a die pad portion and a lead portion,
Mounting an optical semiconductor element on the die pad portion;
Electrically connecting the electrode of the optical semiconductor element and the upper surface of the lead portion by connection means;
A region outside the predetermined central region provided with the optical semiconductor element and the connection means such that only the bottom surfaces of the lead portion and the die pad portion are exposed, and a region between the lead portion and the die pad portion Sealing with external resin,
And sealing the predetermined central region with a transparent resin.
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| JP4052915B2 (en) * | 2002-09-26 | 2008-02-27 | 三洋電機株式会社 | Circuit device manufacturing method |
| JP4508064B2 (en) * | 2005-09-30 | 2010-07-21 | 住友金属鉱山株式会社 | Manufacturing method of wiring board for semiconductor device |
| TWI387080B (en) * | 2007-04-13 | 2013-02-21 | Chipmos Technologies Inc | Qfn package structure and method |
| KR101088910B1 (en) * | 2008-05-29 | 2011-12-07 | 삼성엘이디 주식회사 | LED package and method of manufacturing the same |
| JP4811520B2 (en) * | 2009-02-20 | 2011-11-09 | 住友金属鉱山株式会社 | Semiconductor device substrate manufacturing method, semiconductor device manufacturing method, semiconductor device substrate, and semiconductor device |
| JP5544583B2 (en) * | 2009-10-16 | 2014-07-09 | アピックヤマダ株式会社 | Lead frame, electronic component board and electronic component |
| JP5500130B2 (en) * | 2011-07-20 | 2014-05-21 | 大日本印刷株式会社 | Resin-sealed semiconductor device and circuit member for semiconductor device |
| CN103907185B (en) * | 2011-08-11 | 2016-10-19 | 联达科技控股有限公司 | There is the leaded carriers of the package member that the printing of many materials is formed |
| CN102324412B (en) * | 2011-09-13 | 2013-03-06 | 江苏长电科技股份有限公司 | Island-free lead frame structure prefilled with plastic encapsulating material, plated firstly and etched later and production method thereof |
| US9301391B2 (en) * | 2011-11-29 | 2016-03-29 | Advanpack Solutions Pte Ltd. | Substrate structure, semiconductor package device, and manufacturing method of substrate structure |
| US9324584B2 (en) * | 2012-12-14 | 2016-04-26 | Stats Chippac Ltd. | Integrated circuit packaging system with transferable trace lead frame |
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2016
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| Publication number | Publication date |
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| CN108701658B (en) | 2021-07-27 |
| TWI636541B (en) | 2018-09-21 |
| CN108701658A (en) | 2018-10-23 |
| JP2017152588A (en) | 2017-08-31 |
| TW201742218A (en) | 2017-12-01 |
| MY188860A (en) | 2022-01-10 |
| WO2017145923A1 (en) | 2017-08-31 |
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