JP4288277B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP4288277B2
JP4288277B2 JP2006285159A JP2006285159A JP4288277B2 JP 4288277 B2 JP4288277 B2 JP 4288277B2 JP 2006285159 A JP2006285159 A JP 2006285159A JP 2006285159 A JP2006285159 A JP 2006285159A JP 4288277 B2 JP4288277 B2 JP 4288277B2
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semiconductor device
semiconductor element
external electrode
semiconductor
corners
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JP2008103550A (en
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大輔 高尾
正博 富家
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Aoi Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

本発明は、半導体素子の端子と外部電極とをワイヤまたはリードで接続した半導体装置に関する。   The present invention relates to a semiconductor device in which terminals of a semiconductor element and external electrodes are connected by wires or leads.

半導体素子上の端子と外部電極とをワイヤで接続した半導体装置が従来技術として知られている（たとえば、特許文献１）。この半導体装置では、矩形形状の半導体装置の辺と矩形形状の半導体素子の辺とが平行になるように半導体素子を配置する。そして、半導体装置の対向する２辺と、半導体素子の対向する２辺との各々の間に外部電極を設ける。
特開２００２−１６１８１号公報 A semiconductor device in which a terminal on a semiconductor element and an external electrode are connected by a wire is known as a prior art (for example, Patent Document 1). In this semiconductor device, the semiconductor elements are arranged so that the sides of the rectangular semiconductor device and the sides of the rectangular semiconductor element are parallel to each other. An external electrode is provided between each of two opposing sides of the semiconductor device and two opposing sides of the semiconductor element.
Japanese Patent Laid-Open No. 2002-16181

上記特許文献１に記載されているような従来の半導体装置では、半導体装置の辺と半導体素子の辺との間に無駄なスペースが発生してしまう。このため、半導体素子のチップサイズを小さくすることなく半導体装置を小型化することが難しかった。   In the conventional semiconductor device as described in Patent Document 1, a useless space is generated between the side of the semiconductor device and the side of the semiconductor element. For this reason, it has been difficult to reduce the size of the semiconductor device without reducing the chip size of the semiconductor element.

（１）請求項１の発明は、略矩形形状の半導体素子を有し、回路基板に接合するための外部電極を底面に形成した略矩形形状の半導体装置において、外部電極は、回路基板と接合する面の反対側の面で、半導体素子の端子とワイヤで接続され、外部電極は、半導体装置の４隅の少なくとも３箇所に形成され、半導体素子は、半導体装置の辺に対して傾けて配置され、半導体装置の４隅のうちの少なくとも３隅に形成された外部電極における隣接する隅に形成された外部電極間の少なくとも２つのスペースに、半導体素子の隅の部分がそれぞれ含まれることを特徴とする。
（２）請求項２の発明は、請求項１に記載の半導体装置において、半導体素子は、半導体素子の辺と半導体装置の辺とのなす角が３０°以上、６０°以下になるように配置されることを特徴とする。
（３）請求項３の発明は、請求項２に記載の半導体装置において、半導体素子は、半導体素子の辺と半導体装置の辺とのなす角が４５°になるように配置されることを特徴とする。
（４）請求項４の発明は、請求項１乃至３のいずれか１項に記載の半導体装置において、半導体素子の端子数は３以上、８以下であることを特徴とする。
（５）請求項５の発明は、請求項４に記載の半導体装置において、半導体素子の端子数は４であることを特徴とする。
（６）請求項６の発明は、請求項５に記載の半導体装置において、外部電極は半導体装置の４隅にそれぞれ１つずつ設けられていることを特徴とする。
（７）請求項７の発明は、請求項１乃至６のいずれか１項に記載の半導体装置において、外部電極の形状は略三角形であることを特徴とする。
（８）請求項８の発明は、請求項１乃至７のいずれか１項に記載の半導体装置において、外部電極は電鋳から成ることを特徴とする。 (1) The invention of claim 1 is a substantially rectangular semiconductor device having a substantially rectangular semiconductor element and having an external electrode for bonding to the circuit board formed on the bottom surface . The external electrode is bonded to the circuit board. The surface of the semiconductor device is connected to the terminal of the semiconductor element by a wire on the surface opposite to the surface to be processed, and the external electrodes are formed in at least three corners of the four corners of the semiconductor device. is, at least two spaces between the external electrodes formed on corners adjacent in at least 3 corners formed an external electrode of the four corners of the semiconductor device, the Rukoto includes corner portions of the semiconductor elements, respectively Features.
(2) The invention of claim 2 is the semiconductor device according to claim 1, wherein the semiconductor element is arranged such that an angle formed between the side of the semiconductor element and the side of the semiconductor device is 30 ° or more and 60 ° or less. It is characterized by being.
(3) The invention of claim 3 is the semiconductor device according to claim 2, wherein the semiconductor element is arranged such that an angle formed between the side of the semiconductor element and the side of the semiconductor device is 45 °. And
(4) The invention of claim 4 is the semiconductor device according to any one of claims 1 to 3, wherein the number of terminals of the semiconductor element is 3 or more and 8 or less.
(5) The invention of claim 5 is the semiconductor device according to claim 4, wherein the number of terminals of the semiconductor element is four.
(6) The invention of claim 6 is the semiconductor device according to claim 5, wherein one external electrode is provided at each of the four corners of the semiconductor device.
(7) The invention according to claim 7 is the semiconductor device according to any one of claims 1 to 6 , wherein the external electrode has a substantially triangular shape.
(8) The invention according to claim 8 is the semiconductor device according to any one of claims 1 to 7 , wherein the external electrode is made of electroforming.

本発明によれば、略矩形形状の半導体素子の端子とワイヤで接続する外部電極を略矩形形状の半導体装置の４隅の少なくとも２箇所に設け、半導体装置の辺に対して半導体素子を傾けて配置した。したがって、半導体装置を小型化することができる。   According to the present invention, the external electrodes connected to the terminals of the substantially rectangular semiconductor element by the wires are provided at at least two positions of the four corners of the substantially rectangular semiconductor device, and the semiconductor element is inclined with respect to the side of the semiconductor device. Arranged. Therefore, the semiconductor device can be reduced in size.

本発明の実施形態の半導体装置について図１を参照して説明する。図１（ａ）は半導体装置１の裏面図であり、図１（ｂ）は図１（ａ）のＡ−Ａ線断面図、図１（ｃ）は図１（ａ）のＢ−Ｂ線断面図である。   A semiconductor device according to an embodiment of the present invention will be described with reference to FIG. 1A is a back view of the semiconductor device 1, FIG. 1B is a cross-sectional view taken along line AA of FIG. 1A, and FIG. 1C is a line BB of FIG. 1A. It is sectional drawing.

図１において、符号１は平面視略矩形形状の半導体装置を示し、２は平面視略矩形形状の半導体素子を示す。この半導体素子２は、不図示のダイボンディング材によりダイパッド４ｂの上面に実装されている。半導体素子２には４つの端子２ｂが設けられている。図１（ａ）に示すように、半導体装置１の辺１ａと半導体素子の辺２ａとのなす角θが４５°になるように、半導体装置１上に半導体素子２が配置されている。半導体素子２と同様に、平面視略矩形形状のダイパッド４ｂの辺も半導体装置１の辺と４５°の角度をなす。半導体装置１の４隅には外部電極３ｂが配設されている。外部電極３ｂの各々の形状は、半導体装置１の４隅の領域を有効に利用できるようにするため、略三角形とする。   In FIG. 1, reference numeral 1 denotes a semiconductor device having a substantially rectangular shape in plan view, and 2 denotes a semiconductor element having a substantially rectangular shape in plan view. The semiconductor element 2 is mounted on the upper surface of the die pad 4b by a die bonding material (not shown). The semiconductor element 2 is provided with four terminals 2b. As shown in FIG. 1A, the semiconductor element 2 is arranged on the semiconductor device 1 so that the angle θ formed by the side 1a of the semiconductor device 1 and the side 2a of the semiconductor element is 45 °. Similar to the semiconductor element 2, the side of the die pad 4 b having a substantially rectangular shape in plan view forms an angle of 45 ° with the side of the semiconductor device 1. External electrodes 3 b are disposed at the four corners of the semiconductor device 1. Each of the external electrodes 3b has a substantially triangular shape so that the four corner regions of the semiconductor device 1 can be used effectively.

外部電極３ｂおよびダイパッド４ｂの各上面にはＡｇ層３ａ，４ａが形成されている。外部電極３ｂおよびダイパッド４ｂの各下面にはＡｕ層３ｃ，４ｃが形成されている。図１（ａ）には、外部電極３ｂおよびダイパッド４ｂに形成された全てのＡｕ層３ｃ，４ｃが示されている。以下、本発明の実施形態による半導体装置１を詳細に説明する。   Ag layers 3a and 4a are formed on the upper surfaces of the external electrode 3b and the die pad 4b. Au layers 3c and 4c are formed on the lower surfaces of the external electrode 3b and the die pad 4b. FIG. 1A shows all the Au layers 3c and 4c formed on the external electrode 3b and the die pad 4b. Hereinafter, a semiconductor device 1 according to an embodiment of the present invention will be described in detail.

外部電極３ｂおよびダイパッド４ｂはニッケル電鋳（Ｎｉ電鋳）から成り、半導体装置１の底面に設けられている。したがって、この半導体装置１はいわゆるリードフレームレスタイプである。ここで、外部電極３ｂとは、半導体素子２の電極２ｂと、半導体装置１を実装する回路基板との間で電気的接続をとるための電極である。ダイパッド４ｂは半導体素子２を搭載するための電極である。外部電極３ｂおよびダイパッド４ｂの上面側には、Ａｇ層３ａ，４ａが形成される。外部電極３ｂの上面側のＡｇ層３ａはワイヤボインディングの接続性改善のために設けられる。ダイパッド４ｂの上面側のＡｇ層４ａは、外部電極３ｂの上面側にＡｇ層３ａを形成する際に一緒に設けられるものである。一方、外部電極３ｂおよびダイパッド４ｂの下面側には、Ａｕ層３ｃ，４ｃが形成される。Ａｕ層３ｃ，４ｃは半田濡れ性改善のために設けられる。   The external electrode 3 b and the die pad 4 b are made of nickel electroforming (Ni electroforming), and are provided on the bottom surface of the semiconductor device 1. Therefore, the semiconductor device 1 is a so-called lead frameless type. Here, the external electrode 3 b is an electrode for establishing electrical connection between the electrode 2 b of the semiconductor element 2 and the circuit board on which the semiconductor device 1 is mounted. The die pad 4 b is an electrode for mounting the semiconductor element 2. Ag layers 3a and 4a are formed on the upper surfaces of the external electrode 3b and the die pad 4b. The Ag layer 3a on the upper surface side of the external electrode 3b is provided for improving the connectivity of wire bonding. The Ag layer 4a on the upper surface side of the die pad 4b is provided together when the Ag layer 3a is formed on the upper surface side of the external electrode 3b. On the other hand, Au layers 3c and 4c are formed on the lower surfaces of the external electrode 3b and the die pad 4b. The Au layers 3c and 4c are provided for improving solder wettability.

図１（ｃ）に示すように、半導体素子２と外部電極３ｂとはＡｕのワイヤ５によって電気的に接続している。半導体素子２、ワイヤ５、外部電極３ｂおよびダイパッド４ｂは、エポキシ樹脂などからなる樹脂６によって封止される。このような半導体装置１は、その底面を半田ペーストが塗布された回路基板上に配設し、リフロー炉で熱処理することにより、回路基板上に接合して実装される。   As shown in FIG. 1C, the semiconductor element 2 and the external electrode 3 b are electrically connected by an Au wire 5. The semiconductor element 2, the wire 5, the external electrode 3b, and the die pad 4b are sealed with a resin 6 made of an epoxy resin or the like. Such a semiconductor device 1 is mounted on a circuit board by arranging the bottom surface on a circuit board coated with a solder paste and performing heat treatment in a reflow furnace.

次に、上述した半導体装置１の製造方法について、図２〜図４を参照して説明する。この製造方法は、金属層形成工程と、半導体素子実装工程と、樹脂封止工程と、金属板剥離工程と、分割工程とを含み、１つの金属板上に複数の半導体装置１を縦横並列配置し、同時に作製する。以下、各工程を工程順に説明する。   Next, a method for manufacturing the semiconductor device 1 described above will be described with reference to FIGS. This manufacturing method includes a metal layer forming step, a semiconductor element mounting step, a resin sealing step, a metal plate peeling step, and a dividing step, and a plurality of semiconductor devices 1 are arranged in parallel in the vertical and horizontal directions on one metal plate. At the same time. Hereinafter, each process will be described in the order of processes.

（イ）金属層形成工程
金属層形成工程について、図２（ａ）〜（ｄ）を参照して説明する。図２は、図１のＡ−Ａ線断面図である。
図２（ａ）に示すように、可撓性を有する金属板２１の両面にレジスト２２を塗布またはラミネートする。金属板２１は、厚さ約０．１ｍｍの平板状のＪＩＳ規格のＳＵＳステンレス鋼板またはＣｕ板などの金属薄板からなる。次に、アクリルフィルムベースのパターンマスクフィルムを密着させ、紫外線により露光する。そして、現像し、図２（ｂ）に示すように、外部電極３ｂおよびダイパッド４ｂを形成する部分のレジスト２２Ｒを除去する。金属板２１の一方の面（図２（ａ）の下面）には金属層を形成しないので、レジスト２２によって全面が覆われる。 (I) Metal layer formation process
The metal layer forming step will be described with reference to FIGS. 2 is a cross-sectional view taken along line AA in FIG.
As shown in FIG. 2A, a resist 22 is applied or laminated on both surfaces of a flexible metal plate 21. The metal plate 21 is made of a thin metal plate such as a flat JIS standard SUS stainless steel plate or Cu plate having a thickness of about 0.1 mm. Next, an acrylic film-based pattern mask film is brought into intimate contact and exposed to ultraviolet rays. Then, development is performed, and as shown in FIG. 2B, a portion of the resist 22R that forms the external electrode 3b and the die pad 4b is removed. Since the metal layer is not formed on one surface of the metal plate 21 (the lower surface in FIG. 2A), the entire surface is covered with the resist 22.

次に、金属板２１をＡｕメッキ溶液に浸漬して金属板２１に電力を供給して電鋳を行い、金属板２１上にＡｕ層２３を形成する。次にＡｕ層２３を形成した金属板２１をＮｉめっき溶液に浸漬して電鋳を行い、Ｎｉ層２４を形成する。さらに、Ａｇめっき溶液に金属板２１を浸漬して金属板２１に電力を供給することにより、Ｎｉ層２４の上にＡｇ層２５を形成する。このようにして、図２（ｃ）に示すように、金属板２１に金属層として、パターニングされたＡｕ層２３とＮｉ層２４とＡｇ層２５とを形成する。金属層を形成後、図２（ｄ）に示すように、レジスト２２を金属板２１から剥離する。   Next, the metal plate 21 is immersed in an Au plating solution, electric power is supplied to the metal plate 21 and electroforming is performed, and the Au layer 23 is formed on the metal plate 21. Next, the metal plate 21 on which the Au layer 23 is formed is immersed in a Ni plating solution and electroformed to form the Ni layer 24. Furthermore, the Ag layer 25 is formed on the Ni layer 24 by immersing the metal plate 21 in the Ag plating solution and supplying power to the metal plate 21. In this way, as shown in FIG. 2C, the patterned Au layer 23, Ni layer 24, and Ag layer 25 are formed on the metal plate 21 as metal layers. After forming the metal layer, the resist 22 is peeled from the metal plate 21 as shown in FIG.

（ロ）半導体素子実装工程
半導体素子実装工程について、図２（ｅ）を参照して説明する。
ダイパッド４ｂのＡｇ層４ａに相当するＡｇ層２５に不図示のダイボンディング材を塗布し、図２（ｅ）に示すように半導体素子２をＡｇ層２５上に搭載して固着する。ワイヤボンディングによって、半導体素子２の端子２ｂと、外部電極３ｂのＡｇ層３ａに相当するＡｇ層２５とをワイヤ５によって接続する。 (B) Semiconductor Element Mounting Process The semiconductor element mounting process will be described with reference to FIG.
A die bonding material (not shown) is applied to the Ag layer 25 corresponding to the Ag layer 4a of the die pad 4b, and the semiconductor element 2 is mounted and fixed on the Ag layer 25 as shown in FIG. The wire 2 connects the terminal 2b of the semiconductor element 2 and the Ag layer 25 corresponding to the Ag layer 3a of the external electrode 3b by wire bonding.

（ハ）樹脂封止工程
樹脂封止工程について、図３（ａ）を参照して説明する。
樹脂封止工程では、図３（ａ）に示すように半導体素子２、ワイヤ５、Ａｕ層２３、Ｎｉ層２４およびＡｇ層２５を樹脂６によって封止する。 (C) Resin sealing process The resin sealing process is demonstrated with reference to Fig.3 (a).
In the resin sealing step, the semiconductor element 2, the wire 5, the Au layer 23, the Ni layer 24, and the Ag layer 25 are sealed with the resin 6 as shown in FIG.

（ニ）金属板剥離工程
金属板剥離工程について、図３（ｂ）を参照して説明する。
樹脂６による封止が完了した後は、図３（ｂ）に示すように、Ｎｉ層２４や樹脂６から金属板２１を剥離する。金属板２１は可撓性を有するので、容易に剥離することができる。この金属板２１を剥離したものを以下、樹脂封止体３０と呼ぶ。図４に示すように、樹脂封止体３０には、半導体装置１が複数配置されている。 (D) Metal plate peeling process A metal plate peeling process is demonstrated with reference to FIG.3 (b).
After the sealing with the resin 6 is completed, the metal plate 21 is peeled from the Ni layer 24 and the resin 6 as shown in FIG. Since the metal plate 21 has flexibility, it can be easily peeled off. Hereinafter, the metal plate 21 peeled off is referred to as a resin sealing body 30. As shown in FIG. 4, a plurality of semiconductor devices 1 are arranged in the resin sealing body 30.

（ホ）分割工程
分割工程について、図３（ｂ），（ｃ）および図４を参照して説明する。
図３（ｂ）および図４の一点鎖線３１に沿って、ダイヤモンドブレード・ダイシング法で樹脂封止体３０をダイシングする。そして、図３（ｃ）に示すように、一つの樹脂封止体３０が分割され、半導体装置１が完成する。 (E) Division Step The division step will be described with reference to FIGS. 3 (b), 3 (c) and FIG.
The resin encapsulant 30 is diced by the diamond blade dicing method along the alternate long and short dash line 31 in FIGS. And as shown in FIG.3 (c), the one resin sealing body 30 is divided | segmented and the semiconductor device 1 is completed.

以上の本発明の実施形態による半導体装置１は次のような作用効果を奏する。
（１）略矩形形状の半導体素子２の端子２ｂとワイヤ５で接続する外部電極３ｂを略矩形形状の半導体装置１の隅に設けた。そして、半導体装置１の辺に対して半導体素子２を傾けて配置した。したがって、半導体装置１を小型化することができる。図５（ａ）に従来の、半導体装置１Ａの辺に対して傾けないで半導体素子２を配置した半導体装置１Ａを示す。従来の半導体装置１Ａでは、半導体装置１Ａの辺１ａと半導体素子２の辺２ａとの間にスペース４１ａ，４１ｂが生じる。また、外部電極３ｂ間にもスペース４１ｃ，４１ｄが生じる。一方、本発明の実施形態の半導体装置１では、図５（ｂ）に示すように、それらのスペースが生じないので、半導体装置１を小型化することができる。本発明の実施形態の半導体装置１では、従来の半導体装置１Ａに比べてパッケージサイズを７７％の大きさに縮小することができた。 The semiconductor device 1 according to the above embodiment of the present invention has the following operational effects.
(1) External electrodes 3b connected to the terminals 2b of the substantially rectangular semiconductor element 2 by wires 5 are provided at the corners of the substantially rectangular semiconductor device 1. Then, the semiconductor element 2 is disposed so as to be inclined with respect to the side of the semiconductor device 1. Therefore, the semiconductor device 1 can be reduced in size. FIG. 5A shows a conventional semiconductor device 1A in which the semiconductor element 2 is arranged without being inclined with respect to the side of the semiconductor device 1A. In the conventional semiconductor device 1 </ b> A, spaces 41 a and 41 b are generated between the side 1 a of the semiconductor device 1 </ b> A and the side 2 a of the semiconductor element 2. Also, spaces 41c and 41d are generated between the external electrodes 3b. On the other hand, in the semiconductor device 1 according to the embodiment of the present invention, as shown in FIG. 5B, such a space does not occur, so that the semiconductor device 1 can be downsized. In the semiconductor device 1 of the embodiment of the present invention, the package size could be reduced to 77% as compared with the conventional semiconductor device 1A.

（２）半導体装置１の辺１ａに対して半導体素子２の辺２ａとのなす角度が４５°になるように半導体素子２を傾けて配置した。したがって、半導体装置１を小型化しても、略矩形形状の半導体装置１の隅に設けた外部電極３ｂを大きくすることができる。 (2) The semiconductor element 2 is arranged so as to be inclined so that the angle between the side 1a of the semiconductor device 1 and the side 2a of the semiconductor element 2 is 45 °. Therefore, even if the semiconductor device 1 is downsized, the external electrode 3b provided at the corner of the substantially rectangular semiconductor device 1 can be enlarged.

（３）半導体装置１の隅に配設されている外部電極３ｂの形状を略三角形とした。したがって、半導体装置１の隅を有効に利用でき、外部電極３ｂの面積を大きくすることができる。 (3) The shape of the external electrode 3b disposed at the corner of the semiconductor device 1 is substantially triangular. Therefore, the corners of the semiconductor device 1 can be used effectively, and the area of the external electrode 3b can be increased.

（４）外部電極を電鋳により形成することにより、半導体装置を小型化することができるが、本発明により、さらに小型化が可能となる。 (4) Although the semiconductor device can be miniaturized by forming the external electrode by electroforming, the present invention can be further miniaturized.

以上の実施の形態の半導体装置１を次のように変形することができる。
（１）半導体装置１の辺１ａと半導体素子２の辺２ａとのなす角度を４５°とするのが最も好ましい。しかし、半導体装置１の辺１ａと半導体素子２の辺２ａとのなす角度は３０°以上、６０°以下の範囲内であれば特に４５°に限定されない。この範囲内であれば、半導体装置１の隅に外部電極３ｂを設けることによって、半導体装置１を小型化することができる。一方、半導体装置１の辺１ａと半導体素子２の辺２ａとのなす角度が上記範囲から外れると、以下のような問題が生じる。つまり、図６に示すように、半導体装置１の隅に形成する外部電極３ｂの形状が細長くなったり、外部電極３ｂの面積が小さくなったりし、ワイヤボンディングが難しくなる。ここで、図６の半導体装置１の辺１ａと半導体素子２の辺２ａとのなす角度は２０°である。 The semiconductor device 1 of the above embodiment can be modified as follows.
(1) The angle formed between the side 1a of the semiconductor device 1 and the side 2a of the semiconductor element 2 is most preferably 45 °. However, the angle formed between the side 1a of the semiconductor device 1 and the side 2a of the semiconductor element 2 is not particularly limited to 45 ° as long as it is within a range of 30 ° or more and 60 ° or less. Within this range, the semiconductor device 1 can be miniaturized by providing the external electrodes 3 b at the corners of the semiconductor device 1. On the other hand, when the angle formed between the side 1a of the semiconductor device 1 and the side 2a of the semiconductor element 2 is out of the above range, the following problem occurs. That is, as shown in FIG. 6, the shape of the external electrode 3b formed at the corner of the semiconductor device 1 is elongated, the area of the external electrode 3b is reduced, and wire bonding becomes difficult. Here, the angle formed between the side 1a of the semiconductor device 1 of FIG. 6 and the side 2a of the semiconductor element 2 is 20 °.

（２）半導体素子２の端子２ｂの数は、半導体装置１の隅の数が４であるので４つであることが最も好ましい。しかし、半導体素子２の端子数は、３以上、８以下の範囲内であれば限定されない。たとえば、図７に示すように６つでもよい。半導体素子２の電極の数が２以下になると、半導体装置１の隅の無駄なスペースが大きくなり、９以上になると、コーナに外部電極３ｂを設けるのが困難となる。 (2) The number of terminals 2b of the semiconductor element 2 is most preferably four because the number of corners of the semiconductor device 1 is four. However, the number of terminals of the semiconductor element 2 is not limited as long as it is within the range of 3 or more and 8 or less. For example, as shown in FIG. When the number of electrodes of the semiconductor element 2 is 2 or less, a useless space at the corner of the semiconductor device 1 is increased, and when it is 9 or more, it is difficult to provide the external electrode 3b at the corner.

（３）半導体装置１の４隅全てに外部電極３ｂを設けているが、図８に示すように、半導体装置１の４隅のうちの２隅に外部電極３ｂを設けるようにしてもよい。また、３隅に外部電極３ｂを設けるようにしてもよい。半導体装置１の４隅のうちの１隅または２隅に外部電極３ｂが形成されていないスペースが生ずるものの、それでも半導体装置１の小型化が可能となる。 (3) Although the external electrodes 3b are provided at all four corners of the semiconductor device 1, the external electrodes 3b may be provided at two of the four corners of the semiconductor device 1 as shown in FIG. In addition, external electrodes 3b may be provided at three corners. Although there is a space where the external electrode 3b is not formed at one or two of the four corners of the semiconductor device 1, the semiconductor device 1 can still be downsized.

（４）半導体素子２の形状は特に限定されないが、半導体装置１の形状が略正方形の場合は、半導体素子２の形状は略正方形であることが好ましい。半導体装置１を小型化しても略直角二等辺三角形で、面積の大きい外部電極を形成することができ、ワイヤボンディングが行いやすい。 (4) The shape of the semiconductor element 2 is not particularly limited, but when the shape of the semiconductor device 1 is approximately square, the shape of the semiconductor element 2 is preferably approximately square. Even if the semiconductor device 1 is miniaturized, an external electrode having a substantially right isosceles triangle and a large area can be formed, and wire bonding is easily performed.

（５）本発明は、ワイヤによって半導体素子の端子と外部電極とを接続する半導体装置のほかに、リードによって半導体素子の端子と外部電極とを接続する半導体装置に適用できる。この場合も、半導体装置を小型化することができる。 (5) The present invention can be applied not only to a semiconductor device that connects a terminal of a semiconductor element and an external electrode by a wire, but also to a semiconductor device that connects the terminal of a semiconductor element and an external electrode by a lead. Also in this case, the semiconductor device can be reduced in size.

（６）本発明は、ワイヤまたはリードによって半導体素子の端子と外部電極とを接続するものであれば実施例に限定されない。たとえば、基板に半導体素子を搭載した半導体装置や、リードフレームに半導体素子を搭載した半導体装置にも適用できる。また、小タブ構造の半導体装置やチップ・オン・リード（ＣＯＬ）構造の半導体装置にも適用できる。これらの半導体装置についても小型化することができる。 (6) The present invention is not limited to the embodiment as long as the terminal of the semiconductor element and the external electrode are connected by a wire or a lead. For example, the present invention can be applied to a semiconductor device in which a semiconductor element is mounted on a substrate and a semiconductor device in which a semiconductor element is mounted on a lead frame. Further, the present invention can be applied to a semiconductor device having a small tab structure and a semiconductor device having a chip-on-lead (COL) structure. These semiconductor devices can also be reduced in size.

本発明は、その特徴的構成を有していれば、以上説明した実施の形態になんら限定されない。   The present invention is not limited to the embodiment described above as long as it has the characteristic configuration.

本発明の一実施形態における半導体装置の構造を示す図である。It is a figure which shows the structure of the semiconductor device in one Embodiment of this invention. 本発明の一実施形態における半導体装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of the semiconductor device in one Embodiment of this invention. 本発明の一実施形態における半導体装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of the semiconductor device in one Embodiment of this invention. 樹脂封止体を説明するための図である。It is a figure for demonstrating a resin sealing body. 本発明の一実施形態における半導体装置の効果を説明するための図である。It is a figure for demonstrating the effect of the semiconductor device in one Embodiment of this invention. 半導体素子を傾ける角度を２０°としたときの半導体装置を説明するための図である。It is a figure for demonstrating a semiconductor device when the angle which inclines a semiconductor element is 20 degrees. 半導体素子の端子数が６の場合の本発明の一実施形態における半導体装置を説明するための図である。It is a figure for demonstrating the semiconductor device in one Embodiment of this invention in case the number of terminals of a semiconductor element is six. ４隅のうちの一部の隅に外部電極を設けた半導体装置を説明するための図である。It is a figure for demonstrating the semiconductor device which provided the external electrode in the corner of some of four corners.

符号の説明Explanation of symbols

１、１Ａ 半導体装置
１ａ，２ａ 辺
２ 半導体素子
２ｂ 端子
３ａ，４ａ，２５ Ａｇ層
３ｂ 外部電極
３ｃ，４ｃ，２３ Ａｕ層
４ｂ ダイパッド
５ ワイヤ
６ 樹脂
２１ 金属板
２２ レジスト
２４ Ｎｉ層
３０ 樹脂封止体 DESCRIPTION OF SYMBOLS 1, 1A Semiconductor device 1a, 2a Side 2 Semiconductor element 2b Terminal 3a, 4a, 25 Ag layer 3b External electrode 3c, 4c, 23 Au layer 4b Die pad 5 Wire 6 Resin 21 Metal plate 22 Resist 24 Ni layer 30 Resin sealing body

Claims (8)

略矩形形状の半導体素子を有し、回路基板に接合するための外部電極を底面に形成した略矩形形状の半導体装置において、
前記外部電極は、回路基板と接合する面の反対側の面で、前記半導体素子の端子とワイヤで接続され、
前記外部電極は、前記半導体装置の４隅の少なくとも３箇所に形成され、
前記半導体素子は、前記半導体装置の辺に対して傾けて配置され、
前記半導体装置の４隅のうちの少なくとも３隅に形成された外部電極における隣接する隅に形成された外部電極間の少なくとも２つのスペースに、前記半導体素子の隅の部分がそれぞれ含まれることを特徴とする半導体装置。 In a substantially rectangular semiconductor device having a substantially rectangular semiconductor element and forming an external electrode on the bottom surface for bonding to a circuit board ,
The external electrode is connected to the terminal of the semiconductor element by a wire on the surface opposite to the surface to be bonded to the circuit board,
The external electrodes are formed in at least three locations of the four corners of the semiconductor device,
The semiconductor element is disposed to be inclined with respect to a side of the semiconductor device ,
At least two spaces between the external electrodes formed on corners adjacent in at least 3 corners formed an external electrode of the four corners of the semiconductor device, the Rukoto corner portions of the semiconductor device is contained respectively A featured semiconductor device. 請求項１に記載の半導体装置において、
前記半導体素子は、前記半導体素子の辺と前記半導体装置の辺とのなす角が３０°以上、６０°以下になるように配置されることを特徴とする半導体装置。 The semiconductor device according to claim 1,
The semiconductor device is arranged such that an angle formed between a side of the semiconductor element and a side of the semiconductor device is 30 ° or more and 60 ° or less. 請求項２に記載の半導体装置において、
前記半導体素子は、前記半導体素子の辺と前記半導体装置の辺とのなす角が４５°になるように配置されることを特徴とする半導体装置。 The semiconductor device according to claim 2,
The semiconductor device is arranged such that an angle formed between a side of the semiconductor element and a side of the semiconductor device is 45 °. 請求項１乃至３のいずれか１項に記載の半導体装置において、
前記半導体素子の端子数は３以上、８以下であることを特徴とする半導体装置。 The semiconductor device according to any one of claims 1 to 3,
The number of terminals of the semiconductor element is 3 or more and 8 or less. 請求項４に記載の半導体装置において、
前記半導体素子の端子数は４であることを特徴とする半導体装置。 The semiconductor device according to claim 4,
The semiconductor device according to claim 1, wherein the number of terminals of the semiconductor element is four. 請求項５に記載の半導体装置において、
前記外部電極は前記半導体装置の４隅にそれぞれ１つずつ設けられていることを特徴とする半導体装置。 The semiconductor device according to claim 5,
One external electrode is provided at each of the four corners of the semiconductor device. 請求項１乃至６のいずれか１項に記載の半導体装置において、
前記外部電極の形状は略三角形であることを特徴とする半導体装置。 The semiconductor device according to any one of claims 1 to 6 ,
The semiconductor device according to claim 1, wherein the external electrode has a substantially triangular shape . 請求項１乃至７のいずれか１項に記載の半導体装置において、
前記外部電極は電鋳から成ることを特徴とする半導体装置。
The semiconductor device according to any one of claims 1 to 7,
The semiconductor device according to claim 1, wherein the external electrode is made of electroforming .
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