JP6523999B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP6523999B2 JP6523999B2 JP2016050171A JP2016050171A JP6523999B2 JP 6523999 B2 JP6523999 B2 JP 6523999B2 JP 2016050171 A JP2016050171 A JP 2016050171A JP 2016050171 A JP2016050171 A JP 2016050171A JP 6523999 B2 JP6523999 B2 JP 6523999B2
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- semiconductor chip
- semiconductor
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- chip
- recess
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- 239000004065 semiconductor Substances 0.000 title claims description 153
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 229920005989 resin Polymers 0.000 claims description 60
- 239000011347 resin Substances 0.000 claims description 60
- 238000000034 method Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 16
- 239000000853 adhesive Substances 0.000 claims description 9
- 230000001070 adhesive effect Effects 0.000 claims description 9
- 238000007789 sealing Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 2
- 238000012986 modification Methods 0.000 description 10
- 230000004048 modification Effects 0.000 description 10
- 230000000052 comparative effect Effects 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 238000003475 lamination Methods 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Dicing (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
上記のような構造では、制御チップの厚みに起因して樹脂部材が凸状に変形しやすく、この変形によって半導体メモリチップは凸状に反りやすくなる。そのため、半導体メモリチップを封止するモールド樹脂の凸状部分では、厚さが他の部分よりも薄く形成される可能性がある。モールド樹脂が薄いと、例えば、そのモールド樹脂にレーザで製品名等をマークするときに、モールド樹脂の下の半導体メモリチップがダメージを受けやすくなる。
変形例について説明する。本変形例は、第2半導体チップ41の凹部41aの形成方法が上述した実施形態と異なる。以下、図8を参照して、この形成方法について説明する。
Claims (7)
- 基板の上方に接着剤を介して設けられた第1半導体チップと、
前記第1半導体チップを覆う第1樹脂部材と、
前記第1樹脂部材の上に設けられ、前記第1樹脂部材を介して前記第1半導体チップと対向する部分に前記第1半導体チップの体積と前記接着剤の体積の合計体積よりも小さい体積の凹部を有する第2半導体チップと、
前記第2半導体チップを封止する第2樹脂部材と、
を備える半導体装置。 - 前記凹部の開口端が、前記第1半導体チップの外側に位置し、かつ前記凹部の深さが、前記基板からの前記第1半導体チップの前記第2半導体チップと対向する面までの高さよりも浅い、請求項1に記載の半導体装置。
- 前記第2半導体チップの上に積層され、前記第2樹脂部材で封止された複数の第3半導体チップをさらに備える、請求項1または2に記載の半導体装置。
- 前記第2半導体チップと前記複数の第3半導体チップが、半導体メモリチップであり、
前記半導体装置に入力されるデータおよび前記半導体装置から出力されるデータは、前記第1半導体チップを介して、前記半導体メモリチップに入力および前記半導体メモリチップから出力される、請求項3に記載の半導体装置。 - 基板の上方に接着剤を介して第1半導体チップを設け、
第2半導体チップに前記第1半導体チップの体積と前記接着剤の体積の合計体積よりも小さい体積の凹部を形成し、
前記第1半導体チップを、前記第2半導体チップの前記凹部に沿って接着された第1樹脂部材で覆い、
前記第2半導体チップを第2樹脂部材で覆う、半導体装置の製造方法。 - 前記凹部を、レーザ光の照射にて形成する、請求項5に記載の半導体装置の製造方法。
- 前記凹部を、エッチングにて形成する、請求項5に記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016050171A JP6523999B2 (ja) | 2016-03-14 | 2016-03-14 | 半導体装置およびその製造方法 |
TW106104844A TWI677960B (zh) | 2016-03-14 | 2017-02-15 | 半導體裝置及其製造方法 |
CN201710140999.3A CN107195621B (zh) | 2016-03-14 | 2017-03-10 | 半导体装置及其制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016050171A JP6523999B2 (ja) | 2016-03-14 | 2016-03-14 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2017168533A JP2017168533A (ja) | 2017-09-21 |
JP6523999B2 true JP6523999B2 (ja) | 2019-06-05 |
Family
ID=59871578
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016050171A Active JP6523999B2 (ja) | 2016-03-14 | 2016-03-14 | 半導体装置およびその製造方法 |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP6523999B2 (ja) |
CN (1) | CN107195621B (ja) |
TW (1) | TWI677960B (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6523999B2 (ja) * | 2016-03-14 | 2019-06-05 | 東芝メモリ株式会社 | 半導体装置およびその製造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06268151A (ja) * | 1993-03-12 | 1994-09-22 | Rohm Co Ltd | 半導体装置 |
US6649445B1 (en) * | 2002-09-11 | 2003-11-18 | Motorola, Inc. | Wafer coating and singulation method |
TWI278947B (en) * | 2004-01-13 | 2007-04-11 | Samsung Electronics Co Ltd | A multi-chip package, a semiconductor device used therein and manufacturing method thereof |
JP2006210402A (ja) * | 2005-01-25 | 2006-08-10 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2010118554A (ja) * | 2008-11-13 | 2010-05-27 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP5918664B2 (ja) * | 2012-09-10 | 2016-05-18 | 株式会社東芝 | 積層型半導体装置の製造方法 |
JP6054188B2 (ja) * | 2013-01-30 | 2016-12-27 | 株式会社東芝 | 半導体パッケージおよびその製造方法 |
JP5847749B2 (ja) * | 2013-03-21 | 2016-01-27 | 株式会社東芝 | 積層型半導体装置の製造方法 |
JP2015176906A (ja) * | 2014-03-13 | 2015-10-05 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
JP6523999B2 (ja) * | 2016-03-14 | 2019-06-05 | 東芝メモリ株式会社 | 半導体装置およびその製造方法 |
-
2016
- 2016-03-14 JP JP2016050171A patent/JP6523999B2/ja active Active
-
2017
- 2017-02-15 TW TW106104844A patent/TWI677960B/zh active
- 2017-03-10 CN CN201710140999.3A patent/CN107195621B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
CN107195621A (zh) | 2017-09-22 |
TWI677960B (zh) | 2019-11-21 |
TW201810605A (zh) | 2018-03-16 |
JP2017168533A (ja) | 2017-09-21 |
CN107195621B (zh) | 2019-08-16 |
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