JP6520233B2 - 電子デバイスの製造方法、および、電子デバイス - Google Patents
電子デバイスの製造方法、および、電子デバイス Download PDFInfo
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Description
本発明の電子デバイスの製造方法は、上記目的を達成するために提案されたものであり、撓み変形が許容される駆動領域に当該駆動領域を変形させる駆動素子が設けられた第1の基板と、前記駆動素子とその他の構造体とを間に介在させた状態で前記第1の基板に対して間隔を開けて配置された第2の基板と、が熱硬化性を有する接着剤により接合された電子デバイスの製造方法であって、
前記第1の基板又は前記第2の基板のうち、各々の接合面に形成された構造体を覆う状態で前記接着剤を接合面に塗布したときに、前記構造体を覆う前記接着剤の頂部からスロープを経て前記接着剤の表面が平坦となるまでの距離が短い側の基板に前記接着剤を塗布する工程と、
前記第1基板と前記第2基板との間に前記構造体及び前記接着剤を挟んだ状態で、前記第1基板と前記第2基板とを接合する工程と、
を含むことを特徴とする。
また、上記手段1の方法に関し、パターニングする工程において、前記接着剤は、前記第1基板と前記第2基板との間において高低差が最も大きい構造体が配置される領域を挟んで、当該領域の両側に配置されることが望ましい。
そして、本発明の電子デバイスは、上記手段1または手段2の製造方法により製造されたことを特徴とする。
さらに、上記目的を達成するために提案される本発明は、以下の構成を備えたものであってもよい。
すなわち、撓み変形が許容される駆動領域に当該駆動領域を変形させる駆動素子が設けられた第1の基板と、前記駆動素子とその他の構造体とを間に介在させた状態で前記第1の基板に対して間隔を開けて配置された第2の基板と、が熱硬化性を有する接着剤により接合された電子デバイスの製造方法であって、
前記第1の基板又は前記第2の基板のうち、各々の接合面に形成された構造体を覆う状態で前記接着剤を接合面に塗布したときに、前記構造体を覆う前記接着剤の頂部からスロープを経て前記接着剤の表面が平坦となるまでの距離が短い側の基板に、前記構造体のうちの最も高いものの高さよりも厚く前記接着剤を塗布する工程と、
前記第1基板と前記第2基板との間において高低差が最も大きい構造体が配置される領域を挟んで、当該領域の両側に対応する位置に前記接着剤をパターニングする工程と、
前記第1基板と前記第2基板との間に前記構造体及び前記接着剤を挟んだ状態で、前記第1基板と前記第2基板とを接合する工程と、
を含み、
高低差が最も大きい前記構造体は、内部樹脂と、当該内部樹脂の表面に形成された導電膜と、を有するバンプ電極であることを特徴とする。
本発明によれば、基板に塗布された感光性接着剤の表面にスロープが生じることが抑制される。このため、構造体に対して接着剤をできるだけ近づけて配置することができるため、設計自由度が向上し、構造体や接着剤が高密度に配置されるレイアウトを採用することができる。これにより、電子デバイスの小型化に寄与することができる。また、例えば、シリコン単結晶基板から複数の電子デバイスに対応するチップを切り分ける場合においてチップ1つあたりの面積が小さくなり、シリコン単結晶基板内のチップの取り数を増加させることが可能となる。その結果、電子デバイスの1つあたりのコストを削減することが可能となる。さらに、接着剤の接着信頼性が向上するので、電子デバイスをより安定して製造することができ、歩留まりの向上が期待できる。
また、高低差が最も大きい構造体の配置予定領域においても接着剤の表面にスロープが生じにくいので、当該構造体の配置予定位置にできるだけ近い位置に接着剤を配置することができ、さらなる設計自由度の向上、小型化が期待できる。
また、本発明の電子デバイスは、上記手段1または手段2の製造方法により製造されたことを特徴とする。
本発明によれば、より小型で信頼性の高い電子デバイスを提供することが可能となる。
Claims (2)
- 撓み変形が許容される駆動領域に当該駆動領域を変形させる駆動素子が設けられた第1の基板と、前記駆動素子とその他の構造体とを間に介在させた状態で前記第1の基板に対して間隔を開けて配置された第2の基板と、が熱硬化性を有する接着剤により接合された電子デバイスの製造方法であって、
前記第1の基板又は前記第2の基板のうち、各々の接合面に形成された構造体を覆う状態で前記接着剤を接合面に塗布したときに、前記構造体を覆う前記接着剤の頂部からスロープを経て前記接着剤の表面が平坦となるまでの距離が短い側の基板に、前記構造体のうちの最も高いものの高さよりも厚く前記接着剤を塗布する工程と、
前記第1基板と前記第2基板との間において高低差が最も大きい構造体が配置される領域を挟んで、当該領域の両側に対応する位置に前記接着剤をパターニングする工程と、
前記第1基板と前記第2基板との間に前記構造体及び前記接着剤を挟んだ状態で、前記第1基板と前記第2基板とを接合する工程と、
を含み、
高低差が最も大きい前記構造体は、内部樹脂と、当該内部樹脂の表面に形成された導電膜と、を有するバンプ電極であることを特徴とする電子デバイスの製造方法。 - 請求項1に記載の電子デバイスの製造方法により製造されたことを特徴とする電子デバイス。
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Application Number | Priority Date | Filing Date | Title |
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JP2015044207A JP6520233B2 (ja) | 2015-03-06 | 2015-03-06 | 電子デバイスの製造方法、および、電子デバイス |
US15/003,612 US9889629B2 (en) | 2015-03-06 | 2016-01-21 | Electronic device manufacturing method and electronic device |
CN201610121176.1A CN105936184B (zh) | 2015-03-06 | 2016-03-03 | 电子装置的制造方法以及电子装置 |
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JP2016163937A JP2016163937A (ja) | 2016-09-08 |
JP6520233B2 true JP6520233B2 (ja) | 2019-05-29 |
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