JP6493042B2 - 半導体装置及び半導体装置の制御方法 - Google Patents
半導体装置及び半導体装置の制御方法 Download PDFInfo
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Description
本発明の第1の実施形態について説明する。
図1は、第1の実施形態における半導体装置の構成例を示す図である。図1において、データを送信する側の回路が形成されたダイA10は、データバッファメモリ11、ギャップデータ生成回路12、データ出力ドライバ13、データ反転制御回路14、バリッド信号生成回路15、データ転送制御回路16、及び出力制御回路17を有する。また、データを受信する側の回路が形成されたダイB30は、データ受信バッファ31を有する。なお、図1においては、半導体基板を貫通する貫通電極(TSV)20を1つの領域として示しているが、信号線毎に貫通電極(TSV)20がそれぞれ設けられている。
次に、本発明の第2の実施形態について説明する。
図2は、第2の実施形態における半導体装置の構成例を示す図である。図2において、図1に示した構成要素と同一の機能を有する構成要素には同一の符号を付し、重複する説明は省略する。第2の実施形態において、ダイA10に形成されるデータを送信する側の構成は、第1の実施形態と同様である。第2の実施形態において、データを受信する側の回路が形成されたダイB30は、データ受信バッファ31に加え、クロックデータリカバリ(CDR:Clock Data Recovery)回路32を有する。
次に、本発明の第3の実施形態について説明する。
図3は、第3の実施形態における半導体装置の構成例を示す図である。図3において、図1に示した構成要素と同一の機能を有する構成要素には同一の符号を付し、重複する説明は省略する。第3の実施形態において、ダイA10に形成されるデータを送信する側の構成は、第1の実施形態と同様である。第3の実施形態において、データを受信する側の回路が形成されたダイB30は、データ受信バッファ31に加え、データパターン検出回路33及びクロック位相調整回路34を有する。また、クロック位相調整回路34は、図4に示すように、位相比較器41及び可変遅延回路42を有する。
11 データバッファメモリ
12 ギャップデータ生成回路
13 データ出力ドライバ
14 データ反転制御回路
15 バリッド信号生成回路
16 データ転送制御回路
17 出力制御回路
20 貫通電極
31 データ受信バッファ
32 クロックデータリカバリ回路
33 データパターン検出回路
34 クロック位相調整回路
Claims (7)
- 伝送する第1のデータを保持する保持回路と、
前記第1のデータと同じ伝送路で伝送される第2のデータを生成するデータ生成回路と、
データ信号の周波数が所定の周波数以上になるよう前記第1のデータ及び前記第2のデータの伝送を制御する制御回路と、
前記制御回路による制御に応じて、前記保持回路が保持する前記第1のデータ又は前記データ生成回路が生成する前記第2のデータを選択し前記データ信号として出力する出力回路と、
前記出力回路が前記第1のデータを出力しているとき、データが有効であることを示すバリッド信号を出力するバリッド信号生成回路と、
前記保持回路と前記データ生成回路と前記制御回路と前記出力回路と前記バリッド信号生成回路とを有する第1のダイとは異なる第2のダイに形成され、貫通電極を含む前記伝送路を介して前記第1のダイより伝送された前記データ信号及び前記バリッド信号を受けて、前記バリッド信号を基に前記データ信号により入力されるデータが有効であるか否かを判定し、有効なデータである場合には前記データ信号より前記第1のデータとして取得する受信回路とを有することを特徴とする半導体装置。 - 前記データ信号によって伝送されるデータが反転されたデータであるか否かを示す反転制御信号を出力する反転制御回路を前記第1のダイに有し、
前記出力回路は、前記データ信号として出力するデータを、前記反転制御回路からの指示に応じて非反転又は反転させて出力し、
前記受信回路は、前記第1のダイより伝送された前記反転制御信号が反転されたデータであることを示す場合、取得した前記データを反転させることを特徴とする請求項1記載の半導体装置。 - 前記第1のダイより伝送された前記反転制御信号を基に、前記受信回路での前記第1のデータの取得に用いるクロック信号を生成するクロック生成回路を前記第2のダイに有することを特徴とする請求項2記載の半導体装置。
- 前記第1のダイより伝送されたデータ信号の変化頻度に応じて、前記データ信号とともに前記第1のダイより伝送されたクロック信号の位相を調整し、前記受信回路での前記第1のデータの取得に用いるクロック信号を生成するクロック生成回路を前記第2のダイに有することを特徴とする請求項2記載の半導体装置。
- 前記クロック生成回路は、データが有効ではないことを前記バリッド信号が示している期間は動作を停止することを特徴とする請求項3又は4記載の半導体装置。
- 伝送する第1のデータを保持する保持回路、前記第1のデータと同じ伝送路で伝送される第2のデータを生成するデータ生成回路、制御回路、出力回路、及びバリッド信号生成回路とを有する第1のダイと、受信回路を有する第2のダイとが、貫通電極を含む伝送路により接続された半導体装置の制御方法であって、
前記制御回路が、データ信号の周波数が所定の周波数以上になるよう前記第1のデータ及び前記第2のデータの伝送を制御し、
前記出力回路が、前記制御回路による制御に応じて、前記保持回路が保持する前記第1のデータ又は前記データ生成回路が生成する前記第2のデータを選択し前記データ信号として出力し、
前記バリッド信号生成回路が、前記データ信号として前記第1のデータを出力しているとき、データが有効であることを示すバリッド信号を出力し、
前記受信回路が、前記伝送路を介して前記第1のダイより伝送された前記データ信号及び前記バリッド信号を受けて、前記バリッド信号を基に前記データ信号により入力されるデータが有効であるか否かを判定し、有効なデータである場合には前記データ信号より前記第1のデータとして取得することを特徴とする半導体装置の制御方法。 - 前記第1のダイが有する反転制御回路が、前記データ信号によって伝送されるデータが反転されたデータであるか否かを示す反転制御信号を出力し、
前記出力回路が、前記データ信号として出力するデータを、前記反転制御回路からの指示に応じて非反転又は反転させて出力し、
前記受信回路が、前記第1のダイより伝送された前記反転制御信号が反転されたデータであることを示す場合、取得した前記データを反転させることを特徴とする請求項6記載の半導体装置の制御方法。
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US20200251159A1 (en) * | 2020-04-21 | 2020-08-06 | Intel Corporation | Stacked memory device with end to end data bus inversion |
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JP4423453B2 (ja) * | 2005-05-25 | 2010-03-03 | エルピーダメモリ株式会社 | 半導体記憶装置 |
US7847608B2 (en) * | 2006-03-13 | 2010-12-07 | Nxp B.V. | Double data rate interface |
JP2007325018A (ja) * | 2006-06-01 | 2007-12-13 | Hitachi Communication Technologies Ltd | 半導体集積回路 |
JP2008072164A (ja) * | 2006-09-12 | 2008-03-27 | Nec Corp | 送信デバイス及び電気回路並びに消費電流安定化方法 |
JP5595708B2 (ja) | 2009-10-09 | 2014-09-24 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及びその調整方法並びにデータ処理システム |
TW201403782A (zh) | 2012-07-04 | 2014-01-16 | Ind Tech Res Inst | 基底穿孔的製造方法、矽穿孔結構及其電容控制方法 |
US20140054742A1 (en) | 2012-08-27 | 2014-02-27 | Agency For Science, Technology And Research | Semiconductor Structure |
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