JP6454443B2 - フラットゲート転流型サイリスタ - Google Patents
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Description
本発明は、請求項1のプリアンブルに記載のターンオフパワー半導体デバイス、および、このようなターンオフパワー半導体デバイスの製造方法に関する。
DE2625917A1から知られている半導体デバイスは、P導電型とN導電型を交互にした4つの層を有する半導体本体を含み、これらの層はサイリスタを構成し、その最外層は隣接する層とともにエミッタ接合を形成する。この半導体本体はまた、サイリスタのエミッタ接合のうちの1つを橋絡するための集積電界効果トランジスタ部分を含む。この電界効果トランジスタのソースおよびドレインは、同一導電型の領域を含み、これらの領域のうちの一方は、橋絡されたエミッタ接合に隣接するエミッタ層を形成し、他方は、エミッタ層に隣接しかつエミッタ層と同一導電型の層にオーミック接続された領域を含む。電界効果トランジスタは制御電極を有し、電界効果トランジスタの制御電極と半導体本体との間の電圧を制限するために保護ダイオードが半導体本体に設けられている。サイリスタは光学的点弧のために配置される。サイリスタの点弧のためのゲート電極とP型ベース層との間に好適なオーミック接触を設けるために、高濃度ドープP+型ウェル領域が電極の下方に設けられる。
例示的な実施形態において、ゲートウェル領域の深さは少なくともカソード領域の深さである。典型的に、ゲートウェル領域の深さは、少なくとも5μmであり、より典型的には少なくとも10μmである。
図5〜図7に示されているのは、ターンオフパワー半導体デバイスの比較例である。そのため、この比較例は請求項の範囲に含まれない。しかしながら、この比較例は本発明をより良く理解するのに役立つ。図5はターンオフパワー半導体デバイスの平面図を示し、図6は図5の線AA’に沿う断面図を示し、図7は図6に示される断面図の一部を拡大したものである部分断面図を示す。
Claims (12)
- ターンオフパワー半導体デバイスであって、
第1主面(530)と前記第1主面(530)の反対側の第2主面(531)とを有する半導体ウェハ(51)と、
複数のサイリスタセル(52)とを備え、前記複数のサイリスタセル(52)は各々、前記第1主面(530)から前記第2主面(531)に向けて順に、
(a)第1導電型のカソード領域(54a,54b,54c)、
(b)前記第1導電型と異なるベース層(55)であって、前記カソード領域(54a,54b,54c)が前記ベース層(55)内のウェルとして形成されることにより前記ベース層(55)と前記カソード領域(54a,54b,54c)との間の第1pn接合を形成する第2導電型の前記ベース層(55)、
(c)前記ベース層(55)との間に第2pn接合を形成する前記第1導電型のドリフト層(56)、および
(d)前記ドリフト層(56)によって前記ベース層(55)から分離された前記第2導電型のアノード層(58)を含み、
各サイリスタセル(52)はさらに、
前記カソード領域(54a,54b,54c)の側方に配置され前記ベース層(55)との間にオーミック接触を形成するゲート電極(510)と、
前記第1主面(530)上に配置され前記カソード領域(54a,54b,54c)との間にオーミック接触を形成するカソード電極(53a,53b,53c)と、
前記第2主面(531)上に配置され前記アノード層(58)との間にオーミック接触を形成するアノード電極(59)とを含み、
前記複数のサイリスタセル(52)において、前記カソード領域(54a,54b,54c)と前記カソード電極(53a,53b,53c)との間の界面および前記ベース層(55)と前記ゲート電極(510)との間の界面は、平坦でありかつ同一面にあり、
前記ベース層(55)は、前記ゲート電極(510)との接触から、前記カソード領域(54a,54b,54c)の深さ(dC)の少なくとも2分の1の深さ(dW)まで延在するゲートウェル領域(522)を含み、
任意の深さにおいて、この深さにおける前記ゲートウェル領域(522)の最小ドープ濃度は、この深さおよび側方位置における前記カソード領域(54a,54b,54c)と前記ゲートウェル領域(522)との間の前記ベース層(55)のドープ濃度よりも50%高く、前記側方位置は、前記第1主面(530)に平行な面に直交射影したときの前記カソード領域(54a,54b,54c)からの距離が2μmの位置であり、
前記ベース層(55)は前記第2導電型の補償領域(524)を含み、前記補償領域は、前記第1主面(530)に直に隣接し前記カソード領域(54a,54b,54c)と前記ゲートウェル領域(522)との間に位置するように配置され、前記補償領域における正味ドープ濃度に対する第1導電型不純物の密度は少なくとも0.4であることを特徴とする、ターンオフパワー半導体デバイス。 - 前記ゲートウェル領域(522)の深さ(dW)は、少なくとも前記カソード領域(54a,54b,54c)の深さ(dC)である、請求項1に記載のターンオフパワー半導体デバイス。
- 前記ゲートウェル領域(522)の深さ(dW)は、少なくとも5μmまたは少なくとも10μmである、請求項1または2に記載のターンオフパワー半導体デバイス。
- 前記カソード領域(54a,54b,54c)の前記深さ(dC)は、少なくとも10μmまたは少なくとも15μmである、請求項1〜3のいずれか1項に記載のターンオフパワー半導体デバイス。
- 前記第1主面(530)に直に隣接するように配置されかつ前記カソード領域(54a,54b,54c)と前記ゲートウェル領域(522)との間に配置されている前記ベース層(55)の部分のドープ濃度は、前記第1主面(530)からの距離の増加に伴って増大する、請求項1〜4のいずれか1項に記載のターンオフパワー半導体デバイス。
- 前記補償領域(524)は、前記第1主面(530)から、少なくとも前記カソード領域(54a,54b,54c)の前記深さ(dC)である深さ(dHC)まで延在する、請求項1〜5のいずれか1項に記載のターンオフパワー半導体デバイス。
- 前記補償領域(524)は、前記第1主面(530)から、少なくとも10μmまたは少なくとも15μmの深さ(dHC)まで延在する、請求項1〜6のいずれか1項に記載のターンオフパワー半導体デバイス。
- 前記カソード電極(53a,53b,53c)は、少なくとも10μmの厚さまたは少なくとも15μmの厚さを有する、請求項1〜7のいずれか1項に記載のターンオフパワー半導体デバイス。
- 隣り合うカソード電極(53a,53b,53c)間の空間が絶縁層(528)で埋められており、連続するカソード接触層(532)が、前記カソード電極(53a,53b,53c)および前記絶縁層(528)の上に、前記カソード電極(53a,53b,53c)および前記絶縁層(528)と直に接触するように配置されている、請求項1〜8のいずれか1項に記載のターンオフパワー半導体デバイス。
- 請求項1〜9のいずれか1項に記載のターンオフパワー半導体デバイスの製造方法であって、前記方法は、
前記第1主面(530)に対応する第3主面(530’)と前記第2主面(531)に対応する第4主面とを有する半導体ウェハ(51’)を与えるステップを含み、前記半導体ウェハ(51’)は、前記第3主面(530’)から前記第4主面に向けて順に、
(a)最終的な前記ターンオフパワー半導体デバイスにおける前記ベース層(55)を形成する前記第2導電型の第1半導体層(55’)と、
(b)前記最終的なターンオフパワー半導体デバイスにおける前記ドリフト層(56)を形成する前記第1導電型の第2半導体層(56’)とを備え、
第1導電型第1ドーパント(542)を前記半導体ウェハ(51’)の前記第3主面(530’)から前記第1半導体層(55’)内に選択的に与えることにより、前記第1導電型の複数の半導体領域(54a’,54b’)を前記第1半導体層(55’)内に形成するステップを含み、前記複数の半導体領域(54a’,54b’)は、前記最終的なターンオフパワー半導体デバイスにおける前記複数のサイリスタセル(52)の前記カソード領域(54a,54b)を形成し、
前記第1半導体層(55’)内の複数のウェル領域(522’)におけるドープ濃度を、第2導電型第2ドーパント(549)を前記半導体ウェハ(51’)の第3主面(530’)から前記第1半導体層(51’)内に選択的に与えることによって増大させるステップを含み、前記ウェル領域(522’)は前記複数の半導体領域(54a’,54b’)から分離され、前記ウェル領域(522’)は前記最終的なターンオフパワー半導体デバイスにおける前記ゲートウェル領域(522)を形成し、
第1メタライゼーション層を選択的に形成することにより、前記複数のサイリスタセル(52)の前記カソード電極(53a,53b,53c)を形成するステップと、
第2メタライゼーション層を選択的に形成することにより、前記複数のサイリスタセル(52)の前記ゲート電極(510)を形成するステップと、
第1導電型第3ドーパント(551)を前記第3主面(530’)に隣接する領域に与えることにより、少なくとも、前記最終的なターンオフパワー半導体デバイスにおける前記複数のサイリスタセル(52)の前記カソード領域(54a,54b,54c)と前記ゲートウェル領域(522)との間に位置する領域において、前記第1半導体層(55’)の前記第2導電型のドーピングを部分的に補償するステップとを含む、方法。 - 前記第1導電型第3ドーパント(551)を与えるステップにおいて、前記第1導電型第3ドーパント(551)は前記第3主面(530’)に対して均一に与えられる、請求項10に記載のパワー半導体デバイスの製造方法。
- 前記カソード電極(53a,53b,53c)の厚みを選択的プレーティングによって増大させるステップをさらに含む、請求項9〜11のいずれか1項に記載のパワー半導体デバイスの製造方法。
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