JP6445480B2 - Soi基板の製造方法 - Google Patents
Soi基板の製造方法 Download PDFInfo
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- JP6445480B2 JP6445480B2 JP2016059090A JP2016059090A JP6445480B2 JP 6445480 B2 JP6445480 B2 JP 6445480B2 JP 2016059090 A JP2016059090 A JP 2016059090A JP 2016059090 A JP2016059090 A JP 2016059090A JP 6445480 B2 JP6445480 B2 JP 6445480B2
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- 239000000758 substrate Substances 0.000 title claims description 46
- 238000004519 manufacturing process Methods 0.000 title claims description 31
- 239000004065 semiconductor Substances 0.000 claims description 173
- 239000012535 impurity Substances 0.000 claims description 101
- 238000010438 heat treatment Methods 0.000 claims description 19
- 238000002513 implantation Methods 0.000 claims description 14
- 230000007423 decrease Effects 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 202
- 238000000034 method Methods 0.000 description 17
- 230000015556 catabolic process Effects 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 230000004913 activation Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- -1 and in other cases Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
本明細書または図面に説明した技術要素は、単独あるいは各種の組み合わせによって技術有用性を発揮するものであり、出願時請求項記載の組み合わせに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成するものであり、そのうちの1つの目的を達成すること自体で技術有用性を持つものである。
12 :裏面側半導体層
14 :ボックス層
16 :表面側半導体層
30 :高濃度領域
40 :追加半導体層
Claims (5)
- 高濃度領域を有するSOI基板の製造方法であって、
裏面側半導体層と、前記裏面側半導体層の表面に接している絶縁層と、前記絶縁層の表面に接している表面側半導体層を有するSOI予備基板を準備する工程と、
前記表面側半導体層に不純物を注入することで、前記表面側半導体層に不純物濃度を上昇させた高濃度領域を形成する工程と、
前記高濃度領域を形成した前記SOI予備基板を熱処理する工程と、
熱処理後の前記SOI予備基板の前記表面側半導体層の表面に、前記高濃度領域よりも不純物濃度が低い追加半導体層をエピタキシャル成長させる工程、
を有し、
前記高濃度領域を形成する前記工程では、前記表面側半導体層への不純物注入範囲を変更しながら不純物注入を繰り返し行うことで、前記表面側半導体層の横方向に配列されているとともに不純物濃度が互いに異なる複数の領域を有する前記高濃度領域を形成する、
製造方法。 - 前記追加半導体層に不純物を注入することで、前記追加半導体層の一部にp型領域とn型領域を形成する工程をさらに有し、
前記高濃度領域がn型であり、
前記追加半導体層がn型であり、
前記追加半導体層に不純物を注入する前記工程において、元の前記追加半導体層の不純物濃度を維持している領域が中間領域であり、
前記中間領域が、前記p型領域と前記n型領域の間に配置され、
前記高濃度領域が、前記中間領域と前記絶縁層の間に配置される、
請求項1の製造方法。 - 前記高濃度領域内の前記複数の領域が、前記n型領域から前記p型領域に向かうにしたがってn型不純物濃度が低下するように配列されている、請求項2の製造方法。
- 前記p型領域がダイオードのアノード領域であり、
前記n型領域がダイオードのカソード領域である、
請求項2または3の製造方法。 - 前記p型領域が、MOSFETのドレイン領域であり、
前記n型領域が、MOSFETのソース領域に隣接している、
請求項2または3の製造方法。
Priority Applications (2)
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JP2016059090A JP6445480B2 (ja) | 2016-03-23 | 2016-03-23 | Soi基板の製造方法 |
US15/459,404 US10312133B2 (en) | 2016-03-23 | 2017-03-15 | Method of manufacturing silicon on insulator substrate |
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JP2016059090A JP6445480B2 (ja) | 2016-03-23 | 2016-03-23 | Soi基板の製造方法 |
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JP6445480B2 true JP6445480B2 (ja) | 2018-12-26 |
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Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2703280B2 (ja) * | 1988-09-05 | 1998-01-26 | 株式会社東芝 | 半導体装置の製造方法 |
JPH07263539A (ja) * | 1993-12-09 | 1995-10-13 | Hitachi Ltd | 半導体集積回路装置及びその製造方法 |
JPH098310A (ja) * | 1995-06-16 | 1997-01-10 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH11274312A (ja) * | 1998-03-20 | 1999-10-08 | Sony Corp | 半導体装置及びその製造方法 |
US6579359B1 (en) * | 1999-06-02 | 2003-06-17 | Technologies And Devices International, Inc. | Method of crystal growth and resulted structures |
JP3708057B2 (ja) * | 2001-07-17 | 2005-10-19 | 株式会社東芝 | 高耐圧半導体装置 |
DE102005006290A1 (de) * | 2005-02-11 | 2006-08-24 | Bayerische Motoren Werke Ag | Verfahren und Vorrichtung zur Sichtbarmachung der Umgebung eines Fahrzeugs durch Fusion eines Infrarot- und eines Visuell-Abbilds |
US7435504B2 (en) * | 2005-08-25 | 2008-10-14 | Honda Motor Co., Ltd. | Platinum, tungsten, and nickel or zirconium containing electrocatalysts |
JP5090638B2 (ja) | 2005-11-18 | 2012-12-05 | 株式会社Sumco | Soi基板を製造する方法 |
JP4483775B2 (ja) | 2005-12-14 | 2010-06-16 | 株式会社デンソー | 半導体装置の製造方法 |
JP4713327B2 (ja) | 2005-12-21 | 2011-06-29 | トヨタ自動車株式会社 | 半導体装置とその製造方法 |
US7910455B2 (en) | 2006-04-27 | 2011-03-22 | Shin-Etsu Handotai Co., Ltd. | Method for producing SOI wafer |
JP4564510B2 (ja) * | 2007-04-05 | 2010-10-20 | 株式会社東芝 | 電力用半導体素子 |
JP2009224495A (ja) * | 2008-03-14 | 2009-10-01 | Sanyo Electric Co Ltd | 絶縁ゲート型半導体装置およびその製造方法 |
DE102008040338B3 (de) * | 2008-07-10 | 2010-04-15 | Visteon Global Technologies, Inc., Van Buren Township | Fahrzeugklimaanlage |
JP2010062452A (ja) * | 2008-09-05 | 2010-03-18 | Sumco Corp | 半導体基板の製造方法 |
JP2011253906A (ja) * | 2010-06-01 | 2011-12-15 | Shin Etsu Handotai Co Ltd | 貼り合わせウェーハの製造方法 |
JP2016063190A (ja) * | 2014-09-22 | 2016-04-25 | 住友電気工業株式会社 | 炭化珪素エピタキシャル基板の製造方法、炭化珪素エピタキシャル基板および炭化珪素半導体装置 |
JP2016100566A (ja) | 2014-11-26 | 2016-05-30 | トヨタ自動車株式会社 | Soiウエハの製造方法及びsoiウエハ |
DE102015122828A1 (de) * | 2015-12-23 | 2017-06-29 | Infineon Technologies Austria Ag | Verfahren zum Herstellen einer Halbleitervorrichtung mit epitaktischen Schichten und einer Ausrichtungsmarkierung |
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US20170278741A1 (en) | 2017-09-28 |
US10312133B2 (en) | 2019-06-04 |
JP2017174963A (ja) | 2017-09-28 |
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