JP6410281B2 - データ送受信装置及び表示装置 - Google Patents
データ送受信装置及び表示装置 Download PDFInfo
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- JP6410281B2 JP6410281B2 JP2017536138A JP2017536138A JP6410281B2 JP 6410281 B2 JP6410281 B2 JP 6410281B2 JP 2017536138 A JP2017536138 A JP 2017536138A JP 2017536138 A JP2017536138 A JP 2017536138A JP 6410281 B2 JP6410281 B2 JP 6410281B2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/32—Circuits or arrangements for control or supervision between transmitter and receiver or between image input and image output device, e.g. between a still-image camera and its memory or between a still-image camera and a printer device
- H04N1/36—Circuits or arrangements for control or supervision between transmitter and receiver or between image input and image output device, e.g. between a still-image camera and its memory or between a still-image camera and a printer device for synchronising or phasing transmitter and receiver
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/12—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
- H04N5/126—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising whereby the synchronisation signal indirectly commands a frequency generator
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/033—Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor
- G06F3/038—Control and interface arrangements therefor, e.g. drivers or device-embedded control circuitry
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Signal Processing (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Multimedia (AREA)
- Computer Networks & Wireless Communication (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
(実施の形態1)
図1は、実施の形態1に係る表示装置の電気的機能構成を示すブロック図である。図1中、100は表示装置であり、表示装置100は、テレビジョン受信機又はパーソナルコンピュータ等に用いられ、画像を表示する。
なお、ソースドライバ3は、位相誤差情報に係るアナログ電圧をアナログ電流に変換して位相調整部52に送信してもよい。位相誤差情報を電流伝送することにより、ソースドライバ3からタイミングコントローラ5へのアナログ信号伝送時における電界ノイズによる位相誤差情報のオフセット、ノイズによる影響を抑制することができる。
図5は、実施の形態2に係る表示装置100が備える位相誤差検出部32の構成を示す回路図である。実施の形態2に係る表示装置100の構成について、実施の形態1と同様な構成については、同一の符号を付してその詳細な説明を省略する。
なお、ソースドライバ3は、位相誤差情報に係るアナログ電圧をアナログ電流に変換して位相調整部52に送信してもよい。位相誤差情報を電流伝送することにより、ソースドライバ3からタイミングコントローラ5へのアナログ信号伝送時における電界ノイズによる位相誤差情報のオフセット及びノイズの影響を抑制することができる。
図6は、実施の形態3に係る表示装置100が備える位相誤差検出部32の構成を示す回路図である。実施の形態3においては、一つのクロック信号CLKに対して複数のデータ信号Sxが存在する場合の構成について説明する。実施の形態3に係る表示装置100の構成について、実施の形態1と同様な構成については、同一の符号を付してその詳細な説明を省略する。
例えば、データ信号S1とデータ信号S2との間にスキューがある場合、データ信号S1とクロック信号CLKとの位相を最適に調整すると、データ信号S2とクロック信号CLKとの位相が最適からずれてしまうことがあるが、上記の構成によればデータ信号S1とクロック信号CLKとの位相、及びデータ信号S2とクロック信号CLKとの位相が満遍なく最適となるように調整することができる。
図7は、実施の形態4に係る表示装置100が備える位相誤差検出部32の構成を示す回路図である。実施の形態4においては、実施の形態3と同様に、一つのクロック信号CLKに対して複数のデータ信号Sxが存在する場合の構成について説明する。実施の形態4に係る表示装置100の構成について、実施の形態1から実施の形態3までと同様な構成については、同一の符号を付してその詳細な説明を省略する。
3 ソースドライバ(データ受信部)
32 位相誤差検出部
52 位相調整部
5 タイミングコントローラ(データ送信部)
CLK クロック信号
S1、S2、Sx データ信号
100 表示装置
Claims (5)
- クロック信号及び該クロック信号に同期した複数のデータ信号を送信するデータ送信部と、
前記クロック信号及び前記複数のデータ信号を受信するデータ受信部と
を備え、
前記データ受信部は、前記複数のデータ信号と前記クロック信号との間の複数の位相誤差の平均値に係る位相誤差情報を出力する位相誤差検出部を有し、
前記データ送信部は、前記位相誤差情報に基づいて、前記クロック信号及び前記複数のデータ信号の内の少なくともいずれか一方の位相を調整する位相調整部を有し、
前記位相誤差検出部は、それぞれが、前記複数の位相誤差のそれぞれに対応する電圧を出力する、複数のチャージポンプ回路を有し、
前記複数のチャージポンプ回路の出力は、バッファ回路に接続された共通のコンデンサに接続されており、
前記バッファ回路は、前記位相誤差情報として、前記複数の位相誤差の平均値に対応する前記コンデンサの電圧を出力する、データ送受信装置。 - クロック信号及び該クロック信号に同期した複数のデータ信号を送信するデータ送信部と、
前記クロック信号及び前記複数のデータ信号を受信するデータ受信部と
を備え、
前記データ受信部は、前記複数のデータ信号と前記クロック信号との間の複数の位相誤差の和に係る位相誤差情報を出力する位相誤差検出部を有し、
前記データ送信部は、前記位相誤差情報に基づいて、前記クロック信号及び前記複数のデータ信号の内の少なくともいずれか一方の位相を調整する位相調整部を有し、
前記位相誤差検出部は、それぞれが、前記複数の位相誤差のそれぞれを求める、複数の引き算回路と、前記複数の位相誤差の前記和を求める加算回路とを有し、
前記加算回路は、前記位相誤差情報として、前記複数の位相誤差の前記和を出力する、データ送受信装置。 - 前記位相誤差検出部は、検出した前記複数の位相誤差に係る位相誤差情報を前記データ送信部にフィードバックするように構成されている、請求項1または2に記載のデータ送受信装置。
- 前記データ送信部は、前記位相調整部が調整した前記クロック信号及び前記複数のデータ信号を前記データ受信部に送信するように構成されており、
前記データ受信部は、前記位相調整部が調整した前記クロック信号及び前記複数のデータ信号を同期化するデータ同期部を有する、請求項1から3のいずれかに記載のデータ送受信装置。 - 請求項1から4のいずれかに記載のデータ送受信装置と、
画素電極を含む複数の表示画素を有する液晶パネルと
を備え、
前記データ送信部は、画像データから前記複数のデータ信号を生成し、前記データ受信部は、前記複数のデータ信号を前記画素電極に書き込むように構成されている、表示装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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PCT/JP2015/074087 WO2017033318A1 (ja) | 2015-08-26 | 2015-08-26 | データ送受信装置及び表示装置 |
Publications (2)
Publication Number | Publication Date |
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JPWO2017033318A1 JPWO2017033318A1 (ja) | 2018-06-14 |
JP6410281B2 true JP6410281B2 (ja) | 2018-10-24 |
Family
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Application Number | Title | Priority Date | Filing Date |
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JP2017536138A Expired - Fee Related JP6410281B2 (ja) | 2015-08-26 | 2015-08-26 | データ送受信装置及び表示装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20180183975A1 (ja) |
JP (1) | JP6410281B2 (ja) |
CN (1) | CN107925558B (ja) |
WO (1) | WO2017033318A1 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
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CN107506121A (zh) * | 2017-08-17 | 2017-12-22 | 惠州Tcl移动通信有限公司 | 一种按键控制方法、存储介质及智能终端 |
JP2020030346A (ja) * | 2018-08-23 | 2020-02-27 | 堺ディスプレイプロダクト株式会社 | 表示装置及び表示装置におけるデータ伝送方法 |
CN109215561B (zh) * | 2018-10-30 | 2021-04-23 | 惠科股份有限公司 | 延时调整电路及方法、显示装置 |
CN109493782A (zh) * | 2018-12-19 | 2019-03-19 | 惠科股份有限公司 | 信号校正控制器、信号校正控制方法及显示装置 |
CN109857189B (zh) * | 2018-12-27 | 2023-04-11 | 惠科股份有限公司 | 一种防止集成电路误动作***及方法 |
CN109933300B (zh) * | 2019-03-20 | 2022-07-15 | 合肥鑫晟光电科技有限公司 | 显示处理方法、显示面板和显示装置 |
TWI723669B (zh) * | 2019-12-06 | 2021-04-01 | 新唐科技股份有限公司 | 背光裝置及驅動方法 |
DE112021000274T5 (de) * | 2020-01-08 | 2023-03-02 | Fanuc Corporation | Kommunikationseinrichtung, Industriemaschine und Verfahren zur Bestimmung der Qualität der Kommunikation |
CN113724639B (zh) * | 2021-09-06 | 2023-09-22 | Tcl华星光电技术有限公司 | 显示装置 |
CN117524029A (zh) * | 2024-01-05 | 2024-02-06 | 武汉精立电子技术有限公司 | 一种测试信号生成***和面板检测设备 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH07105818B2 (ja) * | 1986-05-19 | 1995-11-13 | 株式会社日立製作所 | 並列伝送方式 |
US5805233A (en) * | 1996-03-13 | 1998-09-08 | In Focus Systems, Inc. | Method and apparatus for automatic pixel clock phase and frequency correction in analog to digital video signal conversion |
US6483447B1 (en) * | 1999-07-07 | 2002-11-19 | Genesis Microchip (Delaware) Inc. | Digital display unit which adjusts the sampling phase dynamically for accurate recovery of pixel data encoded in an analog display signal |
JP2003218847A (ja) * | 2002-01-28 | 2003-07-31 | Nec Corp | データ受信方式 |
WO2007023620A1 (ja) * | 2005-08-25 | 2007-03-01 | Matsushita Electric Industrial Co., Ltd. | データ受信装置及びデータ送受信システム |
JP2007124130A (ja) * | 2005-10-26 | 2007-05-17 | Fuji Xerox Co Ltd | 送信装置、受信装置、及び送受信装置 |
WO2010146741A1 (ja) * | 2009-06-17 | 2010-12-23 | シャープ株式会社 | 表示駆動回路、表示装置及び表示駆動方法 |
US8629700B2 (en) * | 2012-01-19 | 2014-01-14 | Qualcomm Incorporated | Capacitive multiplication in a phase locked loop |
US20150194083A1 (en) * | 2014-01-03 | 2015-07-09 | Pixtronix, Inc. | Adaptive power-efficient high-speed data link between display controller and component on glass driver ics |
-
2015
- 2015-08-26 WO PCT/JP2015/074087 patent/WO2017033318A1/ja active Application Filing
- 2015-08-26 CN CN201580082575.5A patent/CN107925558B/zh active Active
- 2015-08-26 JP JP2017536138A patent/JP6410281B2/ja not_active Expired - Fee Related
-
2018
- 2018-02-23 US US15/903,223 patent/US20180183975A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
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WO2017033318A1 (ja) | 2017-03-02 |
US20180183975A1 (en) | 2018-06-28 |
CN107925558A (zh) | 2018-04-17 |
JPWO2017033318A1 (ja) | 2018-06-14 |
CN107925558B (zh) | 2020-10-16 |
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