JP6352693B2 - 貫通電極を有する半導体パッケージ及びその製造方法 - Google Patents
貫通電極を有する半導体パッケージ及びその製造方法 Download PDFInfo
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- JP6352693B2 JP6352693B2 JP2014125071A JP2014125071A JP6352693B2 JP 6352693 B2 JP6352693 B2 JP 6352693B2 JP 2014125071 A JP2014125071 A JP 2014125071A JP 2014125071 A JP2014125071 A JP 2014125071A JP 6352693 B2 JP6352693 B2 JP 6352693B2
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- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
3 積層パッケージ
4 パッケージスタック
5 半導体パッケージ
80 パッケージ基板
83 外部モールド膜
85 ソルダボール
90 グラインダ
95 ブレード
100 第1半導体チップ
101 第1半導体基板
111a 半導体基板
120 垂直ホール
121a 貫通電極
123a 連結電極
125 外部電極
601、602、603 モールド膜
Claims (22)
- 第1半導体パッケージ上に第2半導体パッケージを積層することを含む半導体パッケージの製造方法において、
前記第1半導体パッケージを形成する段階が、第1チップ及び第2チップを提供することを含み、
前記第1及び第2チップを提供することが、
第1チップの第1基板が有する前面上に第1活性膜を提供し、
第2チップの第2基板が有する前面上に第2活性膜を提供し、
前記第1及び第2チップを積層して前記第1チップの第1活性膜が前記第2チップの第2活性膜に対向するようにし、
前記第1チップ上及び前記第2チップの第2基板が有する前面上にポリマー物質を含むモールド膜を形成して前記半導体パッケージに剛性を提供し、
前記モールド膜を有する前記第2基板の後面を薄型化し、
前記第2基板の薄型化された後面上に、前記第2基板内の第2貫通電極と電気的に連結される後面電極を形成することを含み、
前記第2半導体パッケージを積層することが、
前記第1半導体パッケージを裏返しにして前記第2チップの薄型化された後面が上に向かうようにし、
前記裏返した第1半導体パッケージ上に前記第2半導体パッケージを積層して、前記第2半導体パッケージの後面が前記第1半導体パッケージの第2チップの薄型化された後面に向かうようにすることを含み、
前記第2半導体パッケージが第3チップと前記第3チップ上の第4チップとを含み、前記第3チップの後面が前記第2チップの薄型化された後面に向かい、
前記第2チップの幅が前記第3チップの幅に比べて大きく、
前記第4チップの幅が前記第3チップの幅に比べて小さい、半導体パッケージの製造方法。 - 前記第2基板の後面を薄型化することが、
機械的工程を使用して前記後面を薄型化することを含む、請求項1に記載の半導体パッケージの製造方法。 - 前記第2基板の後面を薄型化することが、
前記第2基板内の前記第2貫通電極を露出させることを含み、
前記第2貫通電極が前記第2活性膜と電気的に連結された、請求項2に記載の半導体パッケージの製造方法。 - 前記後面電極を形成する前に、
前記薄型化された第2基板内に前記第2貫通電極を形成することをさらに含む、請求項1に記載の半導体パッケージの製造方法。 - 前記第1チップと前記第2チップとの間に第1連結電極を形成して前記第1活性膜と前記第2活性膜とを電気的に連結することをさらに含む、請求項1に記載の半導体パッケージの製造方法。
- 前記第1半導体パッケージ上に前記第2半導体パッケージを積層することが、
前記第1半導体パッケージを含むウエハーレベルパッケージを調製する段階と、
前記第2半導体パッケージを含むチップレベルパッケージを調製する段階と、
前記ウエハーレベルパッケージ上に前記チップレベルパッケージを積層する段階と、を含む、請求項1に記載の半導体パッケージの製造方法。 - 前記第1半導体パッケージに含まれた前記第1基板の第1チップの後面を薄型化することをさらに含む、請求項6に記載の半導体パッケージの製造方法。
- 前記第1基板の薄型化された後面上に第1後面電極を形成することをさらに含み、
前記第1後面電極が前記第1基板内の複数個の第1貫通電極と電気的に連結され、前記複数個の第1貫通電極が前記第1活性膜と電気的に連結された、請求項7に記載の半導体パッケージの製造方法。 - 前記第1半導体パッケージに含まれた前記第1基板の第1チップの後面を薄型化することが、
前記第1基板内の複数個の第1貫通電極を露出させることを含む、請求項8に記載の半導体パッケージの製造方法。 - 前記第1後面電極を形成する前に、
前記第1基板の薄型化された後面内に第1貫通電極を形成することをさらに含む、請求項8に記載の半導体パッケージの製造方法。 - 前記第1及び第2チップを提供することが、
前記モールド膜がキャリヤーとしての役割を提供することを包含する、請求項1に記載の半導体パッケージの製造方法。 - 前記第1活性膜が第1トランジスターを含み、前記第2活性膜が第2トランジスターを含む、請求項1に記載の半導体パッケージの製造方法。
- 前記第2チップの基板が有する熱膨張係数(CTE)と前記モールド膜が有する熱膨張係数(CTE)とが同じ大きさの程度の範囲にある、請求項1に記載の半導体パッケージの製造方法。
- 前記第2チップの基板が有する熱膨張係数(CTE)と前記モールド膜が有する熱膨張係数(CTE)との比が1乃至3である、請求項1に記載の半導体パッケージの製造方法。
- 第1半導体パッケージと第2半導体パッケージとを含み、
前記第1半導体パッケージが、
第1前面に第1活性膜を有する第1チップと、
第2前面に第2活性膜を有し、前記第2活性膜が前記第1活性膜に向かうように前記第1チップ上に積層された第2チップと、
前記第1チップと前記第2チップとの間に配置されたモールド膜と、を含み、
前記第2半導体パッケージが、
第3前面に第3活性膜を有する第3チップと、
第4前面に第4活性膜を有し、前記第4活性膜が前記第3活性膜に向かうように前記第3チップ上に積層された第4チップと、を含み、
前記第3チップの第3後面が前記第2チップの第2後面に向かい、
前記第2チップの幅が前記第3チップの幅に比べて大きく、
前記第4チップの幅が前記第3チップの幅に比べて小さい、半導体パッケージ。 - 前記第1チップが第1貫通電極をさらに含み、
前記第2チップが第2貫通電極をさらに含み、
前記第3チップが第3貫通電極をさらに含み、
前記第4チップが第4貫通電極をさらに含む、請求項15に記載の半導体パッケージ。 - 前記第2貫通電極と前記第3貫通電極とを連結する複数個の電極をさらに含む、請求項16に記載の半導体パッケージ。
- 前記第2チップの幅が前記第1チップの幅に比べて大きい、請求項17に記載の半導体パッケージ。
- 前記第2チップの基板が有する熱膨張係数(CTE)と前記モールド膜が有する熱膨張係数(CTE)とが同じ大きさの程度の範囲にある、請求項15に記載の半導体パッケージ。
- 前記第2チップの基板が有する熱膨張係数(CTE)と前記モールド膜が有する熱膨張係数(CTE)との比が1乃至3である、請求項15に記載の半導体パッケージ。
- 前記第1及び第2活性膜を電気的に連結する第1連結電極をさらに含む、請求項15に記載の半導体パッケージ。
- 第1半導体パッケージと第2半導体パッケージとを含み、
前記第1半導体パッケージが、
第1前面に第1活性膜を有する第1チップと、
第2前面に第2活性膜を有し、前記第1チップ上に積層された第2チップと、
前記第1チップと前記第2チップとの間に配置されたモールド膜と、を含み、
前記第2半導体パッケージが、
第3前面に第3活性膜を有する第3チップと、
第4前面に第4活性膜を有し、前記第3チップ上に積層された第4チップと、を含み、
前記第3チップの第3後面が前記第2チップの第2後面に向かい、
前記第1チップが第1幅を有し、前記第2チップが前記第1幅に比べて大きい第2幅を有し、
前記第3チップが前記第2幅に比べて小さい第3幅を有し、
前記第4チップが前記第3幅に比べて小さい第4幅を有する、半導体パッケージ。
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Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101394203B1 (ko) * | 2011-12-29 | 2014-05-14 | 주식회사 네패스 | 적층형 반도체 패키지 및 그 제조 방법 |
US9147663B2 (en) | 2013-05-28 | 2015-09-29 | Intel Corporation | Bridge interconnection with layered interconnect structures |
US9601410B2 (en) * | 2015-01-07 | 2017-03-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
KR102327142B1 (ko) * | 2015-06-11 | 2021-11-16 | 삼성전자주식회사 | 웨이퍼 레벨 패키지 |
US20170062240A1 (en) * | 2015-08-25 | 2017-03-02 | Inotera Memories, Inc. | Method for manufacturing a wafer level package |
KR102455398B1 (ko) | 2015-11-24 | 2022-10-17 | 에스케이하이닉스 주식회사 | 신축성을 갖는 반도체 패키지 및 이를 이용한 반도체 장치 |
JP6337873B2 (ja) | 2015-11-30 | 2018-06-06 | 日亜化学工業株式会社 | パッケージ、パッケージ中間体、発光装置及びそれらの製造方法 |
KR102667851B1 (ko) * | 2016-02-22 | 2024-05-23 | 삼성디스플레이 주식회사 | 디스플레이 장치 |
JP6443362B2 (ja) * | 2016-03-03 | 2018-12-26 | 株式会社デンソー | 半導体装置 |
CN105810590A (zh) * | 2016-03-18 | 2016-07-27 | 中国电子科技集团公司第二十六研究所 | 声表面波滤波器晶圆键合封装工艺 |
US10186499B2 (en) * | 2016-06-30 | 2019-01-22 | Intel IP Corporation | Integrated circuit package assemblies including a chip recess |
KR102570582B1 (ko) * | 2016-06-30 | 2023-08-24 | 삼성전자 주식회사 | 반도체 패키지 및 그 제조 방법 |
EP3267484B1 (en) | 2016-07-04 | 2021-09-01 | ams International AG | Sensor chip stack and method of producing a sensor chip stack |
KR102508526B1 (ko) | 2016-08-24 | 2023-03-09 | 삼성전자주식회사 | 반도체 패키지 제조 방법 |
JP6981800B2 (ja) * | 2017-07-28 | 2021-12-17 | 浜松ホトニクス株式会社 | 積層型素子の製造方法 |
US11562935B2 (en) * | 2017-11-07 | 2023-01-24 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure |
KR20190057559A (ko) * | 2017-11-20 | 2019-05-29 | 삼성전자주식회사 | 반도체 장치 |
US11211355B2 (en) * | 2018-01-19 | 2021-12-28 | Mitsubishi Electric Corporation | Semiconductor device, method for manufacturing semiconductor device, and power conversion device |
US10319696B1 (en) * | 2018-05-10 | 2019-06-11 | Micron Technology, Inc. | Methods for fabricating 3D semiconductor device packages, resulting packages and systems incorporating such packages |
CN112385036A (zh) * | 2018-07-06 | 2021-02-19 | 伊文萨思粘合技术公司 | 模制的直接键合和互连的堆叠 |
US10978424B2 (en) * | 2018-08-03 | 2021-04-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and manufacturing method thereof |
US10985134B2 (en) * | 2018-11-09 | 2021-04-20 | Nanya Technology Corporation | Method and system of manufacturing stacked wafers |
CN111952268A (zh) | 2019-05-15 | 2020-11-17 | 西部数据技术公司 | 多模块集成内插器和由此形成的半导体器件 |
CN113826200A (zh) * | 2019-05-20 | 2021-12-21 | 华为技术有限公司 | 芯片封装结构及芯片封装方法 |
JP2020194936A (ja) * | 2019-05-30 | 2020-12-03 | 株式会社ディスコ | ウェーハの製造方法及び積層デバイスチップの製造方法 |
US11164819B2 (en) * | 2019-05-30 | 2021-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and manufacturing method thereof |
DE102019128274A1 (de) * | 2019-05-30 | 2020-12-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package-in-Package-gebildetes System |
KR20210013429A (ko) | 2019-07-25 | 2021-02-04 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조 방법 |
KR20220017022A (ko) * | 2020-08-03 | 2022-02-11 | 삼성전자주식회사 | 반도체 패키지 |
US11855006B2 (en) * | 2021-07-29 | 2023-12-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory device, package structure and fabricating method thereof |
US11854928B2 (en) * | 2021-08-27 | 2023-12-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and manufacturing method thereof |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100394808B1 (ko) * | 2001-07-19 | 2003-08-14 | 삼성전자주식회사 | 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법 |
US6867501B2 (en) * | 2001-11-01 | 2005-03-15 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing same |
US6642081B1 (en) | 2002-04-11 | 2003-11-04 | Robert Patti | Interlocking conductor method for bonding wafers to produce stacked integrated circuits |
JP2004128063A (ja) | 2002-09-30 | 2004-04-22 | Toshiba Corp | 半導体装置及びその製造方法 |
JP4575205B2 (ja) * | 2005-03-30 | 2010-11-04 | Okiセミコンダクタ株式会社 | 積層構造体の形成方法及びその方法を使用した半導体装置の製造方法 |
JP2007227555A (ja) * | 2006-02-22 | 2007-09-06 | Renesas Technology Corp | 半導体装置の製造方法 |
KR100743648B1 (ko) * | 2006-03-17 | 2007-07-27 | 주식회사 하이닉스반도체 | 웨이퍼 레벨 시스템 인 패키지의 제조방법 |
JP2008130704A (ja) * | 2006-11-20 | 2008-06-05 | Sony Corp | 半導体装置の製造方法 |
US7781235B2 (en) | 2006-12-21 | 2010-08-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip-probing and bumping solutions for stacked dies having through-silicon vias |
JP2008192853A (ja) * | 2007-02-05 | 2008-08-21 | Sharp Corp | 複数の半導体素子を備える半導体装置、および半導体装置の製造方法 |
KR100945504B1 (ko) * | 2007-06-26 | 2010-03-09 | 주식회사 하이닉스반도체 | 스택 패키지 및 그의 제조 방법 |
US8384224B2 (en) * | 2008-08-08 | 2013-02-26 | International Business Machines Corporation | Through wafer vias and method of making same |
KR20100046760A (ko) * | 2008-10-28 | 2010-05-07 | 삼성전자주식회사 | 반도체 패키지 |
KR20110016017A (ko) | 2009-08-10 | 2011-02-17 | 주식회사 하이닉스반도체 | 반도체 칩 모듈 및 이를 포함하는 반도체 패키지 |
US8159060B2 (en) | 2009-10-29 | 2012-04-17 | International Business Machines Corporation | Hybrid bonding interface for 3-dimensional chip integration |
KR101099578B1 (ko) | 2009-11-03 | 2011-12-28 | 앰코 테크놀로지 코리아 주식회사 | 재배선 및 tsv를 이용한 적층 칩 패키지 |
US20110186960A1 (en) * | 2010-02-03 | 2011-08-04 | Albert Wu | Techniques and configurations for recessed semiconductor substrates |
KR101179268B1 (ko) | 2010-08-05 | 2012-09-03 | 에스케이하이닉스 주식회사 | 관통 비아들을 통한 칩선택이 가능한 반도체 패키지 |
KR101099587B1 (ko) | 2011-04-20 | 2011-12-28 | 앰코 테크놀로지 코리아 주식회사 | Tsv를 이용한 적층 칩 반도체 패키지 |
KR101056750B1 (ko) | 2011-04-20 | 2011-08-16 | 앰코 테크놀로지 코리아 주식회사 | Tsv를 이용한 적층 칩 패키지 |
KR20120126365A (ko) | 2011-05-11 | 2012-11-21 | 에스케이하이닉스 주식회사 | 유닛 패키지 및 이를 갖는 스택 패키지 |
KR20130016682A (ko) * | 2011-08-08 | 2013-02-18 | 에스케이하이닉스 주식회사 | 듀얼 레이어 구조의 반도체칩과 듀얼 레이어 구조의 반도체칩을 갖는 패키지들 및 그 제조방법 |
CN202394958U (zh) * | 2011-12-20 | 2012-08-22 | 日月光半导体制造股份有限公司 | 晶圆级半导体封装构造 |
CN202523706U (zh) * | 2012-02-28 | 2012-11-07 | 刘胜 | 扇出晶圆级半导体芯片三维堆叠封装结构 |
US8703539B2 (en) * | 2012-06-29 | 2014-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple die packaging interposer structure and method |
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