JP6347330B2 - Epitaxial wafer manufacturing method - Google Patents
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- JP6347330B2 JP6347330B2 JP2015095717A JP2015095717A JP6347330B2 JP 6347330 B2 JP6347330 B2 JP 6347330B2 JP 2015095717 A JP2015095717 A JP 2015095717A JP 2015095717 A JP2015095717 A JP 2015095717A JP 6347330 B2 JP6347330 B2 JP 6347330B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 29
- 229910052710 silicon Inorganic materials 0.000 claims description 29
- 239000010703 silicon Substances 0.000 claims description 29
- 238000010438 heat treatment Methods 0.000 claims description 27
- 238000001947 vapour-phase growth Methods 0.000 claims description 16
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 15
- 239000013078 crystal Substances 0.000 claims description 15
- 239000001257 hydrogen Substances 0.000 claims description 12
- 229910052739 hydrogen Inorganic materials 0.000 claims description 12
- 239000012298 atmosphere Substances 0.000 claims description 9
- 239000012808 vapor phase Substances 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 description 30
- 230000007547 defect Effects 0.000 description 16
- 238000006243 chemical reaction Methods 0.000 description 10
- 230000000052 comparative effect Effects 0.000 description 6
- 239000007789 gas Substances 0.000 description 5
- 239000012159 carrier gas Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000002542 deteriorative effect Effects 0.000 description 3
- 239000012071 phase Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- 238000001816 cooling Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 2
- 239000005052 trichlorosilane Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000005033 Fourier transform infrared spectroscopy Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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Description
本発明は、エピタキシャルウェーハの製造方法に関する。 The present invention relates to an epitaxial wafer manufacturing method.
気相成長法により、シリコン単結晶基板の表面にエピタキシャル層を形成したシリコンエピタキシャルウェーハは、電子デバイスに広く使用されている。近年、電子デバイスの微細化によって、エピタキシャルウェーハの品質改善が重要な課題となっている。 A silicon epitaxial wafer in which an epitaxial layer is formed on the surface of a silicon single crystal substrate by a vapor deposition method is widely used for electronic devices. In recent years, with the miniaturization of electronic devices, quality improvement of epitaxial wafers has become an important issue.
エピタキシャル層には、成膜条件によって積層欠陥をはじめとする結晶欠陥が発生することがあり、エピタキシャル層成膜により発生した欠陥を総じてエピ欠陥と呼んでいる。このエピ欠陥の発生は、成膜の温度と深く関係しており、より低温ではエピ欠陥が発生しやすく、成膜条件を変更した際にエピ欠陥レベルが悪化する要因の一つとなっている。また、膜厚均一性も成膜条件の影響を受けやすく、低温で膜厚均一性は悪化する傾向がある。 Crystal defects such as stacking faults may occur in the epitaxial layer depending on the film forming conditions, and defects generated by the epitaxial layer film formation are generally called epi defects. The occurrence of epi defects is deeply related to the temperature of film formation. Epi defects tend to occur at lower temperatures, and this is one of the factors that deteriorate the epi defect level when the film formation conditions are changed. Also, the film thickness uniformity is easily affected by the film forming conditions, and the film thickness uniformity tends to deteriorate at low temperatures.
一方で、エピタキシャル層の表面粗さに関しても成膜条件、特に温度と深く関係している。この際の表面粗さとはパーティクルカウンタで算出されるヘイズレベルを表しており、低温でヘイズレベルは低減する傾向となり、エピ欠陥や膜厚均一性とは逆の相関となっており、ヘイズを低減するためにはエピ欠陥レベル、及び膜厚均一性が悪化してしまうという課題があった。 On the other hand, the surface roughness of the epitaxial layer is also closely related to the film forming conditions, particularly the temperature. The surface roughness at this time represents the haze level calculated by the particle counter, and the haze level tends to decrease at low temperatures, which is inversely correlated with epi defects and film thickness uniformity, reducing haze. In order to do so, there is a problem that the epi defect level and the film thickness uniformity deteriorate.
従来のエピタキシャルウェーハ反応工程においては、エピタキシャル成長の反応温度は1050℃〜1170℃の範囲で行われるのが一般的であり、上記反応温度より低温ではEP欠陥の増加や膜厚均一性の悪化、高温ではスリップの発生が起こり、製造条件としては相応しくない。上記反応温度の範囲内においては、前述したように、エピ欠陥レベル、膜厚均一性と表面粗さの一つの指標であるヘイズレベルは逆の相関となっており、ヘイズレベルを低減するとエピ欠陥レベル、膜厚均一性が悪化する傾向があった。 In the conventional epitaxial wafer reaction process, the reaction temperature for epitaxial growth is generally performed in the range of 1050 ° C to 1170 ° C. Below the above reaction temperature, EP defects increase and film thickness uniformity deteriorates. Then, slip occurs and is not suitable as a manufacturing condition. Within the above reaction temperature range, as described above, the epi-defect level, the haze level that is one index of film thickness uniformity and surface roughness have an inverse correlation. There was a tendency for the level and film thickness uniformity to deteriorate.
特許文献１では、主表面が(110)のウェーハを用いエピタキシャル層を成膜したのち、水素雰囲気で熱処理を行うことでヘイズレベルが改善しているが、ヘイズが発生しやすい主表面が(110)のシリコンウェーハに関するものであり、水素雰囲気での熱処理を行うことで、主表面が(100)のシリコンウェーハのヘイズレベルと同等まで低減するというものである。したがって、主表面が(100)のシリコンウェーハ自体のヘイズレベルを低減できる技術ではない。
In
本発明は、上記した従来技術の問題点に鑑みなされたもので、主表面が(100)のシリコンウェーハの表面にシリコン単結晶エピタキシャル層を気相成長させるエピタキシャルウェーハの製造方法において、エピ欠陥レベル、膜厚均一性を悪化させることなく、ヘイズレベルを低減できるエピタキシャルウェーハの製造方法を提供することを目的とする。 The present invention has been made in view of the above-described problems of the prior art, and in an epitaxial wafer manufacturing method in which a silicon single crystal epitaxial layer is vapor-grown on the surface of a silicon wafer having a main surface of (100), an epitaxial defect level is provided. An object of the present invention is to provide an epitaxial wafer manufacturing method capable of reducing the haze level without deteriorating film thickness uniformity.
上記課題を解決するために、本発明のシリコンエピタキシャルウェーハの製造方法は、主表面が(100)のシリコンウェーハの表面にシリコン単結晶エピタキシャル層を気相成長させるエピタキシャルウェーハの製造方法であり、主表面が(100)のシリコンウェーハの表面にシリコン単結晶エピタキシャル層を気相成長させる気相成長工程と、前記気相成長工程後に、連続して水素雰囲気で熱処理を行う成長後熱処理工程と、を有し、前記成長後熱処理工程の熱処理温度が、前記気相成長工程の成長温度より低温でありかつ800℃〜1120℃の範囲であることを特徴とする。 In order to solve the above problems, a method for producing a silicon epitaxial wafer of the present invention is a method for producing an epitaxial wafer in which a silicon single crystal epitaxial layer is vapor-phase grown on the surface of a silicon wafer having a main surface of (100). A vapor phase growth step in which a silicon single crystal epitaxial layer is vapor-phase grown on the surface of a silicon wafer having a surface of (100), and a post-growth heat treatment step in which heat treatment is continuously performed in a hydrogen atmosphere after the vapor phase growth step. a heat treatment temperature of the growth after the heat treatment step, wherein the range der Rukoto cold der Li Kui 800 ℃ ~1120 ℃ than the growth temperature of the vapor phase growth step.
前記成長後熱処理工程の熱処理温度が、前記成長温度より、50℃以上低温であるのが好ましい。 The heat treatment temperature in the post-growth heat treatment step is preferably lower than the growth temperature by 50 ° C. or more.
前記成長温度が1050℃〜1170℃の範囲であることが好ましい。 The growth temperature is preferably in the range of 1050 ° C to 1170 ° C.
前記成長後熱処理工程の熱処理温度が、800℃〜1120℃の範囲であることが好ましい。 The heat treatment temperature in the post-growth heat treatment step is preferably in the range of 800 ° C to 1120 ° C.
本発明によれば、主表面が(100)のシリコンウェーハの表面にシリコン単結晶エピタキシャル層を気相成長させるエピタキシャルウェーハの製造方法において、エピ欠陥レベル、膜厚均一性を悪化させることなく、ヘイズレベルを低減できるエピタキシャルウェーハの製造方法を提供することができるという著大な効果を有する。 According to the present invention, in a method for producing an epitaxial wafer in which a silicon single crystal epitaxial layer is vapor-grown on the surface of a silicon wafer having a main surface of (100), the haze can be obtained without deteriorating the epi defect level and film thickness uniformity. It has a remarkable effect that an epitaxial wafer manufacturing method capable of reducing the level can be provided.
図１を参照して、本発明のシリコンエピタキシャルウェーハの一つの実施の形態に係る製造方法を説明する。 With reference to FIG. 1, the manufacturing method which concerns on one embodiment of the silicon epitaxial wafer of this invention is demonstrated.
先ず、搬送装置を用いて、気相成長装置の反応容器内に備えられたサセプタに主表面の結晶方位(100)のシリコン単結晶基板を載置する（仕込み工程、図１のステップ１０）。
First, a silicon single crystal substrate having a crystal orientation (100) of the main surface is placed on a susceptor provided in a reaction vessel of a vapor phase growth apparatus using a transfer device (preparation process,
次いで、反応容器内に水素ガスを流した状態で、シリコン単結晶エピタキシャル層を気相成長するための成長温度まで反応容器内の温度を昇温する（昇温工程、図１のステップ１２）。この成長温度は基板表面の自然酸化膜を水素で除去できる1000℃以上に設定する。 Next, with the hydrogen gas flowing in the reaction vessel, the temperature in the reaction vessel is raised to a growth temperature for vapor phase growth of the silicon single crystal epitaxial layer (temperature raising step, step 12 in FIG. 1). This growth temperature is set to 1000 ° C. or higher at which the natural oxide film on the substrate surface can be removed with hydrogen.
次に成長温度を保持したままで水素ガスのみを反応容器内に導入しウェーハ表面の自然酸化膜を除去する（ベーク工程、図１のステップ１４）。 Next, while maintaining the growth temperature, only hydrogen gas is introduced into the reaction vessel to remove the natural oxide film on the wafer surface (baking step, step 14 in FIG. 1).
次いで、反応容器内を成長温度に保持したままで、水素ガスとともに原料ガスをそれぞれ所定流量で供給し、所定膜厚となるまでエピタキシャル層を成長させる（気相成長工程、図１のステップ１６）。
Next, while keeping the inside of the reaction vessel at the growth temperature, the source gas is supplied at a predetermined flow rate together with the hydrogen gas, and the epitaxial layer is grown until a predetermined film thickness is obtained (vapor phase growth step,
さらに、前記気相成長工程後に、連続して水素雰囲気で成長後熱処理工程を行う（成長後熱処理工程、図１のステップ１８）。前記成長後熱処理工程の熱処理温度は、前記気相成長工程の成長温度より低温であることが好ましく、前記成長後熱処理工程の熱処理温度が、前記成長温度より、50℃以上低温であることがより好ましい。
Further, after the vapor phase growth step, a post-growth heat treatment step is continuously performed in a hydrogen atmosphere (post-growth heat treatment step,
反応容器内の温度を下降させて取り出し温度までエピタキシャルウェーハを冷却する（冷却工程、図１のステップ２０）。この冷却工程では、800℃から400℃程度の間で、水素雰囲気から窒素雰囲気へと切換えられる。そして、窒素雰囲気のままで取り出し温度に至ったら気相成長装置からエピタキシャルウェーハを取り出す（取り出し工程、図１のステップ２２）。
The temperature in the reaction vessel is lowered to cool the epitaxial wafer to the removal temperature (cooling step,
その後、エピタキシャルウェーハを洗浄し、不良ウェーハを選別し、シリコンエピタキシャルウェーハを得ることができる。 Thereafter, the epitaxial wafer can be cleaned, and the defective wafer can be selected to obtain a silicon epitaxial wafer.
以下に、本発明の実施例をあげてさらに具体的に説明するが、本発明はこれらの実施例に限定されるものではなく、本発明の技術思想から逸脱しない限り様々の変形が可能であることは勿論である。 Hereinafter, the present invention will be described in more detail with reference to examples. However, the present invention is not limited to these examples, and various modifications can be made without departing from the technical idea of the present invention. Of course.
枚葉式エピタキシャル成長装置において、直径300mm、主表面の面方位(100)のP型シリコン単結晶ウェーハを用いて、原料ガスとしてトリクロロシランを、キャリアガスとして水素を用い、シリコン単結晶エピタキシャル層を気相成長させた。原料ガスの供給量は10slm、キャリアガスの供給量は80slmを選択した。気相成長のみのもの（比較例）及び気相成長後に水素雰囲気での熱処理を行ったもの（実施例）で得られたエピタキシャルウェーハに対して、ヘイズレベル、エピ欠陥レベル、膜厚均一性を評価した。ヘイズレベルはパーティクルカウンタSP2のDW(Darkfield Wide)モードにて、エピ欠陥はSP2のDCO（Darkfield Composite Oblique）モード46nmupにて、膜厚均一性はFT-IRによりエピタキシャル層の膜厚を測定し、得られたエピタキシャル層膜厚の分布から最大値をTmax、最小値をTminとした場合、(Tmax - Tmin)/(Tmax + Tmin)にて算出し評価した。 In a single-wafer epitaxial growth apparatus, using a P-type silicon single crystal wafer having a diameter of 300 mm and a main surface orientation (100), using trichlorosilane as a source gas and hydrogen as a carrier gas, the silicon single crystal epitaxial layer is gasified. Phase growth. The supply amount of source gas was selected to be 10 slm, and the supply amount of carrier gas was selected to be 80 slm. Haze level, epi defect level, and film thickness uniformity for epitaxial wafers obtained by vapor phase growth only (comparative example) and heat treatment in hydrogen atmosphere after vapor phase growth (example) evaluated. The haze level is measured in the DW (Darkfield Wide) mode of the particle counter SP2, the epi defect is measured in the DCO (Darkfield Composite Oblique) mode 46nmup of the SP2, and the film thickness uniformity is measured by FT-IR. When the maximum value was Tmax and the minimum value was Tmin from the distribution of the obtained epitaxial layer thickness, the evaluation was performed by (Tmax−Tmin) / (Tmax + Tmin).
（比較例）
成膜条件を成長温度1170℃とし、気相成長のみ行ったエピタキシャルウェーハのエピ欠陥レベル、膜厚均一性、ヘイズレベルはそれぞれ3.0個/Wf、±0.82%、0.81ppmであった。比較例のエピタキシャル層の積層時の温度プロファイルを図２に示す。
(Comparative example)
The epitaxial defect level, film thickness uniformity, and haze level of the epitaxial wafer subjected only to vapor phase growth at the growth temperature of 1170 ° C. were 3.0 / Wf, ± 0.82%, and 0.81 ppm, respectively. FIG. 2 shows a temperature profile when the epitaxial layer of the comparative example is stacked.
（実施例）
実施例として、比較例と同様にして、成膜条件を成長温度1170℃とし、気相成長を行った後、連続して1000℃の水素雰囲気にて成長後熱処理を行ったエピタキシャルウェーハの、エピ欠陥レベル、膜厚均一性、ヘイズレベルはそれぞれ3.1個/Wf、±0.81%、0.53ppmであった。比較例と実施例の結果を表１に示すが、ヘイズレベルが実施例において低減しているのがわかる。また、実施例のエピタキシャル層の積層時及び成長後熱処理時の温度プロファイルを図３に示す。
(Example)
As an example, in the same manner as in the comparative example, after the vapor deposition was performed at the growth temperature of 1170 ° C., the epitaxial wafer was epitaxially grown after the post-growth heat treatment in a hydrogen atmosphere at 1000 ° C. The defect level, film thickness uniformity, and haze level were 3.1 / Wf, ± 0.81%, and 0.53 ppm, respectively. The results of the comparative example and the example are shown in Table 1, and it can be seen that the haze level is reduced in the example. Moreover, the temperature profile at the time of lamination | stacking of the epitaxial layer of an Example and the heat processing after a growth is shown in FIG.
（実験例）
枚葉式エピタキシャル成長装置において、直径300mm、主表面の面方位(100)のP型シリコン単結晶ウェーハを用いて、原料ガスとしてトリクロロシランを、キャリアガスとして水素を用い、シリコン単結晶エピタキシャル層を気相成長させた。原料ガスの供給量は10slm、キャリアガスの供給量は80slmを選択した。成膜条件を成長温度1050〜1170℃とし、気相成長のみを行った場合と、前記温度にてエピタキシャル層の積層後、水素雰囲気での成長後熱処理を700℃〜1170℃にて行った場合のヘイズレベルの結果を表２に示す。
(Experimental example)
In a single-wafer epitaxial growth apparatus, using a P-type silicon single crystal wafer having a diameter of 300 mm and a main surface orientation (100), using trichlorosilane as a source gas and hydrogen as a carrier gas, the silicon single crystal epitaxial layer is gasified. Phase growth. The supply amount of source gas was selected to be 10 slm, and the supply amount of carrier gas was selected to be 80 slm. When film-forming conditions are growth temperatures of 1050 to 1170 ° C. and only vapor phase growth is performed, and after growth of an epitaxial layer at the above temperature, post-growth heat treatment in a hydrogen atmosphere is performed at 700 to 1170 ° C. Table 2 shows the results of haze levels.
表２からわかるように、成長温度が1050℃〜1170℃の温度域においては、成長後熱処理工程の熱処理温度が800℃以上1120℃以下、かつ成長温度より50℃以上低い場合にヘイズレベルが気相成長のみを行った場合に比較して低減しており、本発明の実施形態を用いることで、エピ欠陥レベル、膜厚均一性を悪化させることなくヘイズレベルの低減が可能である。 As can be seen from Table 2, in the temperature range of 1050 ° C to 1170 ° C, the haze level is significant when the heat treatment temperature in the post-growth heat treatment step is 800 ° C or higher and 1120 ° C or lower and 50 ° C or lower than the growth temperature. Compared with the case where only the phase growth is performed, by using the embodiment of the present invention, it is possible to reduce the haze level without deteriorating the epi defect level and the film thickness uniformity.
Claims (3)
主表面が(100)のシリコンウェーハの表面にシリコン単結晶エピタキシャル層を気相成長させる気相成長工程と、
前記気相成長工程後に、連続して水素雰囲気で熱処理を行う成長後熱処理工程と、
を有し、
前記成長後熱処理工程の熱処理温度が、前記気相成長工程の成長温度より低温でありかつ800℃〜1120℃の範囲であることを特徴とするシリコンエピタキシャルウェーハの製造方法。 An epitaxial wafer manufacturing method in which a silicon single crystal epitaxial layer is vapor-phase grown on the surface of a silicon wafer having a main surface of (100),
A vapor phase growth step in which a silicon single crystal epitaxial layer is vapor-phase grown on the surface of a (100) silicon wafer,
A post-growth heat treatment step of continuously performing heat treatment in a hydrogen atmosphere after the vapor phase growth step;
Have
The heat treatment temperature of the growth after the heat treatment step, method for producing a silicon epitaxial wafer, comprising range der Rukoto cold der Li Kui 800 ℃ ~1120 ℃ than the growth temperature of the vapor phase growth step.
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