JP6331695B2 - 半導体素子の製造方法 - Google Patents
半導体素子の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000000758 substrate Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 18
- 239000013078 crystal Substances 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000003746 surface roughness Effects 0.000 description 9
- 239000002019 doping agent Substances 0.000 description 6
- 229910002704 AlGaN Inorganic materials 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- KTWOOEGAPBSYNW-UHFFFAOYSA-N ferrocene Chemical compound [Fe+2].C=1C=C[CH-]C=1.C=1C=C[CH-]C=1 KTWOOEGAPBSYNW-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
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- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Description
本願の発明に係る他の半導体装置の製造方法は、基板上にAlN層をエピタキシャル成長する第1工程と、該AlN層の上に、Feを添加せずに、xが0より大きく1より小さいAlxGa1−xNをエピタキシャル成長してひずみ緩和層を形成する工程と、該ひずみ緩和層の上に、x+y+zが1でありyが0でないAlxGayInzNをエピタキシャル成長してバッファ層を形成する第2工程と、該バッファ層の上に、Feを添加しつつx+y+zが1でありyが0でないAlxGayInzNをエピタキシャル成長して抵抗層を形成する第3工程と、該抵抗層の上にチャネル層をエピタキシャル成長する工程と、該チャネル層の上方に電子供給層をエピタキシャル成長する工程と、該電子供給層の上方に電極を形成する工程と、を備え、該ひずみ緩和層の格子定数は該AlN層の格子定数と該バッファ層の格子定数の間の値であり、該ひずみ緩和層の厚さと該バッファ層の厚さの合計を150nm以下としたことを特徴とする。
図1は、本発明の実施の形態1に係る半導体素子の製造方法で製造された半導体素子10の断面図である。半導体素子10はGaN系のHEMT(High Electron Mobility Transistor)を構成している。半導体素子10は単結晶SiCで形成された基板12を備えている。基板12はサファイア又はSiで形成してもよい。基板12の上にはAlN層14が形成されている。
実施の形態2に係る半導体素子の製造方法は、実施の形態1との共通点が多いので、実施の形態1との相違点を中心に説明する。第2工程では、AlN層14の上に、Feを添加しつつバッファ層16をエピタキシャル成長する。バッファ層16は、x+y+zが1でありyが0でないAlxGayInzNである。
Claims (7)
- 基板上にAlN層をエピタキシャル成長する第1工程と、
前記AlN層の上に、Feを添加せずに、x+y+zが1でありyが0でないAlxGayInzNをエピタキシャル成長してバッファ層を形成する第2工程と、
前記バッファ層の上に、Feを添加しつつx+y+zが1でありyが0でないAlxGayInzNをエピタキシャル成長して抵抗層を形成する第3工程と、
前記抵抗層の上にチャネル層をエピタキシャル成長する工程と、
前記チャネル層の上方に電子供給層をエピタキシャル成長する工程と、
前記電子供給層の上方に電極を形成する工程と、を備え、
前記第3工程で前記抵抗層に添加された前記Feの一部は、前記電極形成までに前記バッファ層へ熱拡散し、前記バッファ層と前記AlN層の界面のFe濃度を1×1017cm−3以上に高めることを特徴とする半導体素子の製造方法。 - 前記抵抗層の厚さは200nm〜400nmであり、
前記第3工程では、前記抵抗層のFeの濃度が1×10 17 cm −3 〜1×10 20 cm −3 の範囲となるように、Feを添加することを特徴とする請求項1に記載の半導体素子の製造方法。 - 前記バッファ層の厚さは150nm以下であることを特徴とする請求項1又は2に記載の半導体素子の製造方法。
- 前記基板は単結晶SiCであることを特徴とする請求項1〜3のいずれか1項に記載の半導体素子の製造方法。
- 前記AlN層は、裏面より表面の凹凸が大きいことを特徴とする請求項1〜4のいずれか1項に記載の半導体素子の製造方法。
- 基板上にAlN層をエピタキシャル成長する第1工程と、
前記AlN層の上に、Feを添加せずに、xが0より大きく1より小さいAl x Ga 1−x Nをエピタキシャル成長してひずみ緩和層を形成する工程と、
前記ひずみ緩和層の上に、x+y+zが1でありyが0でないAl x Ga y In z Nをエピタキシャル成長してバッファ層を形成する第2工程と、
前記バッファ層の上に、Feを添加しつつx+y+zが1でありyが0でないAl x Ga y In z Nをエピタキシャル成長して抵抗層を形成する第3工程と、
前記抵抗層の上にチャネル層をエピタキシャル成長する工程と、
前記チャネル層の上方に電子供給層をエピタキシャル成長する工程と、
前記電子供給層の上方に電極を形成する工程と、を備え、
前記ひずみ緩和層の格子定数は前記AlN層の格子定数と前記バッファ層の格子定数の間の値であり、
前記第3工程で前記抵抗層に添加された前記Feの一部は、前記電極形成までに前記バッファ層及び前記ひずみ緩和層へ熱拡散し、前記ひずみ緩和層と前記AlN層の界面でのFe濃度を1×10 17 cm −3 以上とすることを特徴とする半導体素子の製造方法。 - 基板上にAlN層をエピタキシャル成長する第1工程と、
前記AlN層の上に、Feを添加せずに、xが0より大きく1より小さいAl x Ga 1−x Nをエピタキシャル成長してひずみ緩和層を形成する工程と、
前記ひずみ緩和層の上に、x+y+zが1でありyが0でないAl x Ga y In z Nをエピタキシャル成長してバッファ層を形成する第2工程と、
前記バッファ層の上に、Feを添加しつつx+y+zが1でありyが0でないAl x Ga y In z Nをエピタキシャル成長して抵抗層を形成する第3工程と、
前記抵抗層の上にチャネル層をエピタキシャル成長する工程と、
前記チャネル層の上方に電子供給層をエピタキシャル成長する工程と、
前記電子供給層の上方に電極を形成する工程と、を備え、
前記ひずみ緩和層の格子定数は前記AlN層の格子定数と前記バッファ層の格子定数の間の値であり、
前記ひずみ緩和層の厚さと前記バッファ層の厚さの合計を150nm以下としたことを特徴とする半導体素子の製造方法。
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US10483354B2 (en) * | 2018-01-30 | 2019-11-19 | Kabushiki Kaisha Toshiba | Nitride semiconductor device |
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TWI730494B (zh) | 2019-11-06 | 2021-06-11 | 錼創顯示科技股份有限公司 | 半導體結構 |
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