JP6302184B2 - 信頼性のある表面実装集積型パワーモジュール - Google Patents
信頼性のある表面実装集積型パワーモジュール Download PDFInfo
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- JP6302184B2 JP6302184B2 JP2013148095A JP2013148095A JP6302184B2 JP 6302184 B2 JP6302184 B2 JP 6302184B2 JP 2013148095 A JP2013148095 A JP 2013148095A JP 2013148095 A JP2013148095 A JP 2013148095A JP 6302184 B2 JP6302184 B2 JP 6302184B2
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Classifications
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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Description
12 半導体デバイス
14 POLサブモジュール
16 第2のレベルの入力/出力(I/O)接続部
17 はんだバンプ
18 基板構造
20 セラミック基板
22 ダイ側ダイレクトボンド銅(DBC)層
24 非ダイ側DBC層
26 アンダーフィル
30 誘電体層
32 フレーム構造
34 接着剤層
36 ビア
37 銅シム
38 金属インターコネクト
39 上部表面
40 はんだマスク
44 厚さ
46 面積カバレッジ
50 POL構造
52 セラミック/誘電体シート
54 切欠き部
56 成形コンパウンド
58 ギャップ
Claims (21)
- サブモジュールであって、
柔軟な誘電体層と、
複数の半導体デバイスの各々が半導体材料からなる基板を含む状態で、前記誘電体層に取り付けられた複数の半導体デバイスと、
前記複数の半導体デバイスに電気的に結合された第1のレベルの金属インターコネクト構造であり、前記金属インターコネクト構造が前記複数の半導体デバイスに接続されるように前記誘電体層を貫通して形成されたビアを通って延伸する、第1のレベルの金属インターコネクト構造と、
前記第1のレベルの金属インターコネクト構造に電気的に結合され、かつ前記複数の半導体デバイスとは反対側の前記誘電体層上に形成された第2のレベルの入力/出力(I/O)接続部であり、前記第2のレベルのI/O接続部が外部回路に前記サブモジュールを接続するように構成される、第2のレベルのI/O接続部と
を備えた、サブモジュールと、
第1の表面および第2の表面を有する多層基板構造であって、前記サブモジュールの前記複数の半導体デバイスが前記多層基板の前記第1の表面に取り付けられる、多層基板構造と、
前記誘電体層と前記多層基板構造の前記第1の表面との間でかつ前記サブモジュールの前記複数の半導体デバイスのまわりに少なくとも一部が配置された1つまたは複数の誘電体材料であって、前記1つまたは複数の誘電体材料が前記表面実装型構造内のギャップ内を埋め、かつ前記表面実装型構造にさらなる構造的完全性を与えるように構成される、1つまたは複数の誘電体材料と
を備え、
前記第1のレベルの金属インターコネクト構造が、金属膜を備え、
前記第1のレベルの金属インターコネクト構造と前記第2のレベルのI/O接続部とが各々の半導体デバイスにおいて独立して形成される、表面実装型構造。 - 前記多層基板構造が、
セラミック絶縁性層と、
前記多層基板構造の前記第1の表面を形成するように前記絶縁性層の一方の側の上に配置された第1の金属層と、
前記多層基板構造の前記第2の表面を形成するように前記絶縁性層のもう一方の側の上に配置された第2の金属層と
を備えた、請求項1記載の表面実装型構造。 - 前記第1の金属層および前記第2の金属層が、第1のダイレクトボンド銅(DBC)層および第2のDBC層を備える、請求項2記載の表面実装型構造。
- 前記第1のDBC層がパターニングされたDBC層を含み、前記第2のDBC層がパターニングされたまたはパターニングされていないDBC層を含む、請求項3記載の表面実装型構造。
- 前記第2のDBC層の前記体積が、前記第1のDBC層の前記体積の等倍から2.5倍までの間である、請求項3記載の表面実装型構造。
- 前記第2のDBC層の厚さまたは面積、および対応する体積が、前記1つまたは複数の誘電体材料の厚さおよび材料特性、前記複数の半導体デバイスの密度、厚さ、および間隔、ならびに前記セラミック絶縁性層の厚さおよび材料特性のうちの少なくとも1つに基づいて制御される、請求項5記載の表面実装型構造。
- 前記1つまたは複数の誘電体材料および前記セラミック絶縁性層の前記材料特性が、弾性係数、熱膨張係数(CTE)、ならびに破壊応力および靱性のうちの少なくとも1つを含む、請求項6記載の表面実装型構造。
- 前記1つまたは複数の誘電体材料が、前記誘電体層と前記多層基板構造の前記第1の表面との間に配置されたアンダーフィル材料、封入剤、シリコーンまたは成形コンパウンドを含む、請求項1乃至7のいずれかに記載の表面実装型構造。
- 1つまたは複数の誘電体材料が、
前記誘電体層と前記多層基板構造の前記第1の表面との間に配置されたセラミックまたは誘電体シートであって、前記セラミックまたは誘電体シートが前記複数の半導体デバイスを受けるために前記シート内に形成された切欠きを有する、セラミックまたは誘電体シートと、
前記セラミックまたは誘電体シートと前記多層基板構造との間のギャップを埋めるために、前記セラミックまたは誘電体シートと前記多層基板構造の前記第1の表面との間に配置された誘電体フィラー材料と
を備えた、請求項1乃至8のいずれかに記載の表面実装型構造。 - 前記第2のレベルのI/O接続部が、ランドグリッドアレイ(LGA)はんだバンプおよびボールグリッドアレイ(BGA)はんだバンプのうちの一方を備える、請求項1乃至9のいずれかに記載の表面実装型構造。
- 前記多層基板構造に前記サブモジュールをしっかりと固定するために前記多層基板構造と前記サブモジュールとの間に配置されたはんだ材料、導電性接着剤、または焼結した金属接合部のうちの1つをさらに備えた、請求項10記載の表面実装型構造。
- 前記サブモジュールが、パワーオーバーレイ(POL)サブモジュールを含む、請求項1乃至11のいずれかに記載の表面実装型構造。
- 表面実装型パッケージングおよびインターコネクト構造を製造する方法であって、
複数の半導体デバイスおよびその周りに形成されたパッケージング構造を含
むサブモジュールを構築するステップであり、
柔軟な誘電体層に前記複数の半導体デバイスを取り付けるサブステップと、
前記誘電体層の上方に金属膜を備える第1のレベルの金属インターコネクト構造を形成するサブステップであり、前記第1のレベルの金属インターコネクト構造が前記複数の半導体デバイスに電気的に接続するために前記誘電体層内のビアを通って延伸する、第1のレベルの金属インターコネクト構造を形成するサブステップと、
前記複数の半導体デバイスとは反対側の前記誘電体層上に第2のレベルの入力/出力(I/O)接続部を形成するサブステップであり、前記第2のレベルのI/O接続部が外部回路に前記サブモジュールを接続するように構成される、第2のレベルのI/O接続部を形成するサブステップと
を含み、
前記第1のレベルの金属インターコネクト構造と前記第2のレベルのI/O接続部とが各々の半導体デバイスにおいて独立して形成される、サブモジュールを構築するステップと、
第1の金属層および第2の金属層が基板構造のそれぞれ第1の表面および第2の表面を形成するように、中央基板層ならびに前記中央基板層の反対側に前記第1の金属層および前記第2の金属層を含む基板構造を形成するステップと、
前記基板構造の前記第1の表面に前記サブモジュールを取り付けるステップと、
前記誘電体層と前記基板構造の前記第1の表面との間に誘電体フィラー材料を設けるステップであり、前記誘電体フィラー材料が前記サブモジュールの前記複数の半導体デバイスを少なくとも部分的に封入する、誘電体フィラー材料を設けるステップとを含む方法。 - 前記基板構造を形成するステップが、
前記第1の金属層に対する前記第2の金属層の所望の体積比率を決定するサブステップと、
前記第1の金属層に対する前記第2の金属層の前記所望の体積比率を与える厚さおよび面積を有するように前記第2の金属層を形成するサブステップと
をさらに含み、
前記第1の金属層に対する前記第2の金属層の前記所望の体積比率を決定するサブステップが、前記誘電体フィラー材料の厚さおよび材料特性、前記複数の半導体デバイスの密度、厚さ、および間隔、ならびに前記中央基板層の厚さおよび材料特性のうちの少なくとも1つに基づき、
前記誘電体フィラー材料および前記中央基板層の前記材料特性が、弾性係数、熱膨張係数(CTE)、ならびに破壊応力および靱性のうちの少なくとも1つを含む、請求項13記載の方法。 - 前記第1の金属層に対する前記第2の金属層の前記所望の体積比率が、1から2.5までの間であり、
前記第1の金属層に対する前記第2の金属層の前記所望の体積比率が、反りおよび内部の熱応力を最小にする応力バランスの取れた表面実装型パッケージおよびインターコネクト構造を与える、請求項14記載の方法。 - 前記第1のレベルの金属インターコネクト構造を形成するサブステップが、
スパッタリング、電気めっき、金属堆積の1以上により、前記金属膜を形成するステップと、
パターニングした前記第1のレベルの金属インターコネクト構造をはんだマスク層で覆うステップと、
を含み、
第2のレベルのI/O接続部を形成するサブステップが、前記第2のレベルのI/O接続部を前記はんだマスク層にはんだ付けするステップを含む、請求項13乃至15のいずれかに記載の方法。 - 前記誘電体フィラー材料を設けるステップが、
前記誘電体層と前記基板構造の前記第1の表面との間に配置されたセラミックまたは誘電体シートを設けるサブステップであって、前記セラミックまたは誘電体シートが前記複数の半導体デバイスを受けるために前記シート内に形成された切欠きを有する、セラミックまたは誘電体シートを設けるサブステップと、
前記セラミックまたは誘電体シートと前記基板構造との間のギャップを埋めるために、前記セラミックまたは誘電体シートと前記基板構造の前記第1の表面との間に配置されたアンダーフィル材料または成形コンパウンドを設けるサブステップと
を含む、請求項13乃至16のいずれかに記載の方法。 - パワーオーバーレイ(POL)サブモジュールであって、
柔軟な誘電体層と、
前記誘電体層に取り付けられた複数の半導体デバイスと、
前記複数の半導体デバイスに電気的に結合された第1のレベルのインターコネクト構造であり、前記第1のレベルのインターコネクト構造が前記複数の半導体デバイスに接続されるように前記誘電体層を貫通して形成されたビアを通って延伸する、第1のレベルのインターコネクト構造と、
外部回路構造に前記POLサブモジュールを電気的に結合するための第2のレベルのインターコネト構造であり、前記第2のレベルのインターコネクト構造が、前記誘電体層および前記第1のレベルのインターコネクト構造の上方に形成された複数のはんだバンプを備え、かつ前記外部回路構造へのインターコネクションを作るように構成される、第2のレベルのインターコネクト構造と
を備えた、POLサブモジュールと、
第1の表面および第2の表面を有する多層基板構造であって、前記POLサブモジュールの前記複数の半導体デバイスが前記多層基板構造の前記第1の表面に取り付けられ、前記多層基板構造が、
前記多層基板構造の前記第1の表面を形成する第1のダイレクトボンド銅(DBC)層と、
前記多層基板構造の前記第2の表面を形成する第2のDBC層と、
前記第1のDBC層と前記第2のDBC層との間に挟まれたセラミック層と
を含む、多層基板構造と、
前記誘電体層と前記多層基板構造の前記第1の表面との間でかつ前記サブモジュールの前記複数の半導体デバイスのまわりに少なくとも一部が配置された誘電体フィラー材料と
を備え、
前記第1のレベルのインターコネクト構造が、金属膜を備え、
前記第1のレベルの金属インターコネクト構造と前記第2のレベルのI/O接続部とが各々の半導体デバイスにおいて独立して形成される、パワーオーバーレイ(POL)パッケージング構造。 - 前記第2のDBC層が前記第1のDBC層よりも大きな体積を有する状態で、前記第1のDBC層と前記第2のDBC層との間に体積不均衡があり、
前記第2のDBC層の前記体積が、前記誘電体フィラー材料の厚さおよび材料特性、前記複数の半導体デバイスの密度、厚さ、および間隔、ならびに前記セラミック層の厚さおよび材料特性のうちの少なくとも1つに基づいて決定され、前記誘電体フィラー材料および前記セラミック層の前記材料特性が、弾性係数、熱膨張係数(CTE)、ならびに破壊応力および靱性のうちの少なくとも1つを含むことをともなう、請求項18記載のPOLパッケージング構造。 - 前記第1のDBC層と前記第2のDBC層との間の前記体積不均衡が、1から2.5までの間である、請求項19記載のPOLパッケージング構造。
- 前記誘電体フィラー材料が、アンダーフィル材料、封入剤、シリコーンもしくは成形コンパウンド、またはセラミックもしくは誘電体シートと誘電体フィラー材料との組み合わせを含む、請求項18乃至20のいずれかに記載のPOLパッケージング構造。
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