WO2023184414A1 - 芯片封装结构、电子设备及芯片封装结构的制备方法 - Google Patents
芯片封装结构、电子设备及芯片封装结构的制备方法 Download PDFInfo
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- WO2023184414A1 WO2023184414A1 PCT/CN2022/084602 CN2022084602W WO2023184414A1 WO 2023184414 A1 WO2023184414 A1 WO 2023184414A1 CN 2022084602 W CN2022084602 W CN 2022084602W WO 2023184414 A1 WO2023184414 A1 WO 2023184414A1
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- Prior art keywords
- substrate
- chip
- heat dissipation
- chips
- dissipation cover
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- 238000002360 preparation method Methods 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 408
- 230000017525 heat dissipation Effects 0.000 claims abstract description 276
- 239000000463 material Substances 0.000 claims abstract description 71
- 238000004806 packaging method and process Methods 0.000 claims description 187
- 239000000853 adhesive Substances 0.000 claims description 148
- 230000001070 adhesive effect Effects 0.000 claims description 148
- 239000010410 layer Substances 0.000 claims description 128
- 239000003292 glue Substances 0.000 claims description 111
- 238000000034 method Methods 0.000 claims description 54
- 239000012790 adhesive layer Substances 0.000 claims description 37
- 238000003825 pressing Methods 0.000 claims description 28
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 230000032798 delamination Effects 0.000 abstract description 33
- 238000010586 diagram Methods 0.000 description 48
- 239000002184 metal Substances 0.000 description 14
- 229910052751 metal Inorganic materials 0.000 description 14
- 230000000694 effects Effects 0.000 description 6
- RKUAZJIXKHPFRK-UHFFFAOYSA-N 1,3,5-trichloro-2-(2,4-dichlorophenyl)benzene Chemical compound ClC1=CC(Cl)=CC=C1C1=C(Cl)C=C(Cl)C=C1Cl RKUAZJIXKHPFRK-UHFFFAOYSA-N 0.000 description 5
- 238000003466 welding Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 230000003014 reinforcing effect Effects 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 230000035772 mutation Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000003190 augmentative effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000003631 expected effect Effects 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
Definitions
- the present application relates to the field of chip packaging technology, and in particular to a chip packaging structure, electronic equipment and a method for preparing the chip packaging structure.
- Multi-chip packaging can also be called multi-chip module (MCM) packaging.
- MCM packaging can effectively shorten the interconnection wiring length between traditional single chips, providing high-density and high-reliability packaging. feasibility.
- the thermal expansion coefficient CTE here can be understood as: during the process of installing the chip on the substrate, or after the chip has been integrated on the substrate, the substrate with integrated chip will expand and contract due to temperature changes. During the expansion and contraction, the unit The volume change caused by temperature change can be expressed by the thermal expansion coefficient CTE.
- a heat dissipation cover (Lid) 03 covers the two chips 02 and is fixedly connected to the substrate 01 .
- a thermal interface material (TIM) layer 04 is provided between the chip 02 and the heat dissipation cover 03 .
- Embodiments of the present application provide a chip packaging structure, electronic equipment, and a method for manufacturing the chip packaging structure.
- the main purpose is to provide a chip packaging structure that can weaken the risk of TIM layer delamination.
- the present application provides a chip packaging structure, which is a multi-chip module MCM packaging structure.
- the chip packaging structure may include: a substrate, multiple chips integrated on the substrate, and a heat dissipation cover.
- the multiple chips are located on the same surface of the substrate, and any one of the multiple chips is connected through an electrical connection structure (such as a soldering layer). ) is disposed on the substrate, and the heat dissipation cover includes a central portion covering the side of the plurality of chips away from the substrate, and an outer edge portion surrounding the periphery of the plurality of chips and fixedly connected to the substrate.
- a thermal interface material layer is formed between the surface away from the substrate and the central part of any one of the plurality of chips; wherein the surface of the central part of the heat dissipation cover facing the substrate has one or more protrusions, And one or more protrusions are in contact with the thermal interface material layer of at least one chip among the plurality of chips.
- the protruding part fixedly connected to the heat dissipation cover can be pressed against the thermal interface material. layer.
- the protrusions will be pressed against the heat sink. on the interface material layer to prevent the risk of delamination between the thermal interface material layer and the chip. In this case, the heat dissipation resistance of the chip can be reduced and the heat dissipation effect of the chip can be improved.
- the protruding portion has a plurality of pressing surfaces, and the plurality of pressing surfaces abut on the plurality of thermal interface material layers on a one-to-one basis.
- the protrusion has multiple pressing surfaces that can press against the TIM layer
- other structural components are installed on the heat dissipation cover, such as installing a heat sink.
- the heat sink exerts pressure on the heat dissipation cover towards the chip, in this case, the protruding part will deform and exert a resisting force on the TIM layer to adhere closely to the TIM layer. Therefore, the protruding part with a resisting surface helps Reduce the possibility of TIM delamination.
- the protruding portion is disposed close to the center of the first area, the plurality of resisting surfaces are arranged along the circumference of the protruding portion, and the rectangle formed by the orthographic projection of the plurality of chips on the substrate is the first area. a region; and, along the direction from the central part of the heat dissipation cover to the substrate, any pressing surface is inclined from the edge of the first region toward the center of the first region. That is to say, the pressing surface is a surface that is inclined relative to the chip.
- the pressing surface can be more closely aligned with the TIM layer on the warped chip.
- the heat dissipation cover, TIM layer and chip can be further closely aligned.
- the pressing surface may be an inclined plane or an inclined curved surface.
- the chip packaging structure further includes an adhesive pillar, the adhesive pillar is located between the protrusion and the substrate, and one end of the adhesive pillar is bonded to the protrusion, and the other end is bonded to the substrate. bonding.
- the adhesive pillars can be used to pull the protruding part and the substrate together.
- the pulling force of the adhesive pillars on the heat dissipation cover and the substrate can be used to avoid the interference between the partial area of the substrate and the heat dissipation cover. There is a large distance between them, that is, the warping of the package is resisted through pulling force.
- the chip packaging structure also includes one or more dummy chips, one or more dummy chips and multiple chips are located on the same surface of the substrate; the orthographic projection of the multiple chips on the substrate forms a The rectangle is the first area, and the orthographic projection of the dummy chip on the substrate is located in the first area.
- the local warpage of the substrate can be adjusted, thereby suppressing the degree of warpage of the substrate carrying multiple chips.
- the delamination phenomenon of the TIM layer between the chip and the heat dissipation cover can also be weakened, which can reduce the heat dissipation resistance of the chip and improve the heat dissipation effect of the chip.
- the orthographic projection of the dummy chip on the substrate is located in the first area, in this case, the area of the entire substrate will not be increased by disposing the dummy chip.
- the dummy chip is located between the protrusion and the substrate, and is bonded to the protrusion through an adhesive layer.
- the outer edge part and the central part have an integrally formed structure.
- the outer edge portion of the heat dissipation cover is fixedly connected to the central portion of the heat dissipation cover through a connecting structure.
- the reinforcing ring is fixedly connected to the central part of the heat dissipation cover through a welded structure.
- the present application also provides a chip packaging structure, which, like the above chip packaging structure, is also a multi-chip module MCM packaging structure.
- the chip packaging structure includes a substrate, multiple chips integrated on the substrate and at least one dummy chip, and also includes a heat dissipation cover.
- the multiple chips are located on the same surface of the substrate, and any one of the multiple chips is electrically connected.
- the connection structure (such as a soldering layer) is disposed on the substrate, the at least one dummy chip and the plurality of chips are located on the same surface of the substrate, and the heat dissipation cover includes a central portion covering the side of the plurality of chips and the at least one dummy chip away from the substrate, and an outer edge portion surrounding the plurality of chips and at least one dummy chip and fixedly connected to the substrate; wherein the rectangle surrounded by the orthographic projections of the plurality of chips on the substrate is the first area, and the at least one dummy chip The orthographic projection on the substrate is located within the first area.
- the chip packaging structure given in this application includes not only chips with electrical functions, but also dummy chips without electrical functions. By arranging dummy chips in local positions of the substrate, the local warpage of the substrate can be adjusted. This can further suppress the degree of warpage of a substrate carrying multiple chips. Finally, the delamination phenomenon of the TIM layer between the chip and the heat dissipation cover can also be weakened, which can reduce the heat dissipation resistance of the chip and improve the heat dissipation effect of the chip.
- the orthographic projection of at least one dummy chip on the substrate is located in the first area. That is to say, the relationship between chips is fully utilized.
- the dummy chip is placed in the idle space between them. In this way, on the basis of suppressing the warpage of the entire package, it will not increase the size of the substrate or the entire package structure.
- the area of any dummy chip is smaller than the area of the chip.
- the idle space between chips is used to set up smaller-sized dummy chips to achieve the purpose of suppressing the degree of warpage.
- the surface of any dummy chip away from the substrate is bonded to the central part through an adhesive layer.
- Bonding the dummy chip to the central part of the heat dissipation cover through the adhesive layer can pull the heat dissipation cover and the substrate together through the dummy chip. Through the pulling force, the warpage of the entire package can also be suppressed.
- the plurality of chips include a first chip, a second chip, a third chip and a fourth chip; at least one dummy chip is a dummy chip; the first chip, the second chip, the third chip and The fourth chip is placed near the corner of the first area; a dummy chip is placed near the center of the first area.
- the plurality of chips includes a first chip and a second chip; at least one dummy chip includes a first dummy chip and a second dummy chip; the first chip and the second chip are located on the first pair of the rectangular structure On the diagonal line, the first dummy chip and the second dummy chip are located on the second diagonal line of the rectangular structure, and the first diagonal line and the second diagonal line intersect.
- this application also provides a chip packaging structure.
- the chip packaging structure is also a multi-chip module MCM packaging structure.
- the chip packaging structure includes a substrate, multiple chips integrated on the substrate, and a heat dissipation cover.
- the multiple chips are located on the same surface of the substrate, and any one of the multiple chips is connected through an electrical connection structure (such as The soldering layer) is provided on the substrate, and the heat dissipation cover includes a central part covering the side of the multiple chips away from the substrate, and an outer edge part surrounding the periphery of the multiple chips and fixedly connected to the substrate;
- the chip packaging structure also includes The pulling column is located between the central part of the heat dissipation cover and the substrate.
- the orthographic projection of the pulling column on the substrate is located in the first area.
- the rectangle formed by the orthographic projection of the multiple chips on the substrate is the first area.
- the pulling column is fixedly connected to the central part of the heat dissipation cover and the base plate respectively.
- the central part of the heat dissipation cover is fixedly connected to the substrate through the pulling column, in this way, when multiple chips are integrated on the substrate during preparation, even if there is a gap between the chip and the substrate.
- the degree of warpage of the substrate carrying the chip will be suppressed due to the pulling force of the pulling column on the substrate and the heat dissipation cover. It can also be understood in this way, Because of the pulling force of the pulling column on the substrate, a large distance between some areas of the substrate and the heat dissipation cover is avoided, that is, the pulling structure is used to resist the warping of the package.
- the TIM layer located between the chip and the heat dissipation cover will basically not have delamination, thereby reducing the heat dissipation thermal resistance of the chip and improving the thermal resistance of the chip.
- the heat dissipation effect Among the structures that can be selected, for the materials that can be selected for the TIM layer, you only need to choose materials with high thermal conductivity. There is no need to consider the bonding strength of the TIM layer too much. In this way, the TIM layer will not be selected. The material is too restrictive.
- the orthographic projection of the pulling column on the substrate is located in the first region. Compared with arranging the pulling column outside the first region, , will not produce greater stress on some chips, therefore, it can play a role in protecting the chips.
- the pulling column includes an adhesive column, one end of the adhesive column is bonded to the central part of the heat dissipation cover, and the other end is bonded to the substrate.
- the pulling column here can adopt a structure made of adhesive glue, and the central part of the heat dissipation cover and the substrate are pulled together through the adhesive force of the adhesive glue.
- the outer edge portion is fixedly connected to the substrate through an adhesive layer surrounding the periphery of multiple chips; and the adhesive pillars and the adhesive layer are made of the same material.
- the adhesive pillars can be bonded at the same time. Therefore, on the basis of suppressing the warpage of the chip and the substrate, the preparation process will not become complicated.
- the pulling structure includes a boss and an adhesive pillar.
- the boss is formed on the surface of the central part of the heat dissipation cover facing the substrate; one end of the adhesive pillar is bonded to the boss, and the other end of the adhesive pillar is bonded to the boss. One end is bonded to the substrate.
- a boss protruding toward the substrate can be provided in the central part of the heat dissipation cover.
- an adhesive post is provided to bond the boss and the substrate to pull the boss on the heat dissipation cover and the substrate together.
- the pulling strength of the pulling column to the heat dissipation cover and the substrate can also be enhanced.
- the boss and the central part of the heat dissipation cover are an integrally formed structure.
- it can be an integrally formed metal piece.
- the distance between the surface of the boss facing the substrate and the substrate is d1; the distance between the surface of the outer edge portion facing the substrate and the substrate is d2; where d1 is greater than or equal to d2.
- the boss formed on the heat dissipation cover cannot be too high. If it is too high, it may cause greater stress on the package, and this stress may affect the performance of the chip.
- the distance d2 between the outer edge part of the heat dissipation cover and the base plate can be smaller than or equal to the distance d1 between the boss and the base plate.
- the chip packaging structure further includes at least one dummy chip, the at least one dummy chip and the plurality of chips are located on the same surface of the substrate, and the orthographic projection of the at least one dummy chip on the substrate is located on the third within a region.
- the chip packaging structure further includes an adhesive glue column, one end of the adhesive glue column is bonded to the central part, and the other end is bonded to the dummy chip.
- the pulling column includes an adhesive glue column and a support column.
- the adhesive glue column includes a first adhesive glue column and a second adhesive glue column; one end of the support column passes through the first adhesive glue column.
- the column is bonded to the central part, and the other end of the support column is bonded to the base plate through a second adhesive glue column.
- the strength of the pulling column can also be improved on the premise of meeting the pulling force.
- the present application also provides a method for preparing a chip packaging structure.
- the method for preparing a chip packaging structure includes:
- any one of the multiple chips is arranged on the substrate through an electrical connection structure
- thermal interface material layer on a surface of any one of the plurality of chips away from the substrate
- the heat dissipation cover is provided such that one or more protrusions on the central portion of the heat dissipation cover are in contact with the thermal interface material layer of at least one chip among the plurality of chips; wherein the central portion of the heat dissipation cover is covered by the heat dissipation cover.
- One or more protrusions are provided on the surface of the central portion of the heat dissipation cover facing the substrate on the portion of the plurality of chips on the side away from the substrate.
- the central part of the heat dissipation cover has one or more protrusions
- the protrusions will abut against the thermal interface material layer superior.
- the radiator will exert pressure on the heat dissipation cover. Under the action of this pressure, the protruding portion will deform, giving the thermal interface material layer extrusion force. , to reduce the possibility of delamination of the thermal interface material layer.
- the preparation method before setting the heat dissipation cover, further includes: dotting adhesive glue on a surface of the substrate that is opposite to the central part of the heat dissipation cover to form an adhesive glue column, so that on After the heat dissipation cover is installed, the adhesive posts are fixedly connected between the base plate and the protruding portion.
- glue is dotted on the surface of the substrate that is opposite to the central part of the heat dissipation cover.
- the preparation method further includes: glue is dotted along the circumference of the outer edge of the substrate to form The adhesive layer is bonded so that the outer edge part of the heat dissipation cover is fixedly connected to the substrate through the adhesive adhesive layer, and the material of the adhesive glue pillar and the adhesive adhesive layer is the same; wherein, the outer edge part of the heat dissipation cover is surrounded by the heat dissipation cover On the periphery of multiple chips.
- a dispensing process can be used to form an adhesive layer and an adhesive column at the same time.
- the preparation method before arranging the heat dissipation cover, the preparation method further includes: arranging one or more dummy chips on the surface of the substrate on which the plurality of chips are arranged, and the one or more dummy chips are placed on the front side of the substrate.
- the projection is located in the first area, and the rectangle surrounded by the orthographic projections of the plurality of chips on the substrate is the first area.
- the preparation method further includes: dotting glue on the surface of the one or more dummy chips away from the substrate, so that After the heat dissipation cover is installed, the dummy chip is fixedly connected to the protruding part through adhesive glue.
- the present application also provides a method for preparing a chip packaging structure.
- the method for preparing a chip packaging structure includes:
- any one of the multiple chips is arranged on the substrate through an electrical connection structure
- One or more dummy chips are arranged on the surface of the substrate on which multiple chips are arranged, and the orthographic projection of the one or more dummy chips on the substrate is located in the first area, and the orthographic projection of the plurality of chips on the substrate forms a rectangle. is the first area;
- the heat dissipation cover is arranged so that the central part of the heat dissipation cover covers the side of the plurality of chips away from the substrate.
- the local warpage of the substrate can be improved, thereby also reducing the risk of delamination of the thermal interface material layer.
- the dummy chips are located in the first area, the area of the substrate will not be increased by adding dummy chips.
- the preparation method before setting the heat dissipation cover, the preparation method further includes: dotting glue on the surface of one or more dummy chips away from the substrate, so that after the heat dissipation cover is set, the dummy chips pass through the adhesive The glue is firmly connected to the central part of the heat dissipation cover.
- adhesive is applied on the surface of one or more dummy chips away from the substrate.
- the preparation method further includes: adhesive is applied along the circumference of the outer edge of the substrate to form an adhesive bond.
- Adhesive layer so that the outer edge part of the heat dissipation cover is fixedly connected to the substrate through the adhesive adhesive layer, and the adhesive glue located on the dummy chip and the adhesive adhesive layer are made of the same material; wherein, the outer edge part of the heat dissipation cover is the heat dissipation cover The part surrounding multiple chips.
- a dispensing process can be used to simultaneously form an adhesive layer and an adhesive layer located on the dummy chip.
- the present application also provides a method for preparing a chip packaging structure.
- the method for preparing a chip packaging structure includes:
- a pulling column is provided on the surface of a substrate provided with multiple chips, a rectangle surrounded by orthographic projections of the plurality of chips on the substrate is the first region, and the orthographic projection of the pulling column on the substrate is located in the first region;
- the heat dissipation cover is arranged so that the heat dissipation cover covers the central portion of the plurality of chips on the side away from the substrate and is fixedly connected to the substrate through the pulling column.
- a pulling column In the method for preparing the chip packaging structure provided by this application, before setting the heat dissipation cover, a pulling column must be set on the substrate, and then the heat dissipation cover can be installed. If designed in this way, the pulling column can ensure the connection between the heat dissipation cover and the substrate.
- the stability of the distance between the chip and the substrate will not cause the phenomenon of larger distance in some areas and smaller distance in some areas due to the thermal expansion coefficient mismatch between the chip and the substrate.
- the pulling column will suppress the degree of warpage and avoid the phenomenon of larger distances due to the larger distance between the chip and the substrate.
- a large degree of warpage causes some phenomena, such as delamination of the TIM layer between the chip and the heat dissipation cover.
- arranging a pulling column on the surface of a substrate provided with multiple chips includes: dotting adhesive glue on a surface of the substrate that is opposite to the central part of the heat dissipation cover to form an adhesive.
- the adhesive posts are fixedly connected between the base plate and the central part of the heat dissipation cover, and the adhesive posts form pulling posts.
- glue is dispensed on the substrate to form a pulling column that bonds the substrate and the heat dissipation cover together through adhesive force.
- the pulling column of this structure is not only simple in structure, but also easy to implement in technology.
- glue is dotted on the surface of the substrate that is opposite to the central part of the heat dissipation cover.
- the preparation method further includes: glue is dotted along the circumference of the outer edge of the substrate to form The adhesive layer is bonded so that the outer edge part of the heat dissipation cover is fixedly connected to the substrate through the adhesive adhesive layer, and the material of the adhesive glue pillar and the adhesive adhesive layer is the same.
- the outer edge part of the heat dissipation cover is surrounded by multiple layers of the heat dissipation cover. peripheral part of the chip.
- a glue dispensing process can be used to form an adhesive layer on the edge of the substrate for bonding to the outer edge of the heat dissipation cover, and an adhesive pillar to form a pulling column.
- a protruding portion is formed on a surface of the central portion of the heat dissipation cover facing the substrate; before setting the heat dissipation cover, the preparation method further includes: placing a convex portion on a surface of any one of the plurality of chips away from the substrate.
- a thermal interface material layer is formed on the surface of the chip; setting the heat dissipation cover includes: installing the heat dissipation cover so that the protruding portion of the heat dissipation cover abuts the thermal interface material layer of any chip.
- the protruding portion fixedly connected to the heat dissipation cover can be located on the thermal interface material layer.
- the protruding portion can be deformed to press against the thermal interface material layer.
- the thermal interface material layer from delaminating due to the thermal expansion coefficient mismatch between the chip and the substrate, that is, applying pressure to the thermal interface material layer through the protrusions to prevent delamination of the thermal interface material layer.
- the preparation method before arranging the heat dissipation cover, the preparation method further includes: arranging dummy chips on the surface of the substrate on which the plurality of chips are arranged.
- the degree of warpage of the package can be suppressed.
- the present application also provides an electronic device, which includes a printed circuit board and the chip packaging structure in any of the above implementations, and the chip packaging structure is disposed on the printed circuit board and connected with the printed circuit board. Circuit board electrical connections.
- the electronic device provided by the embodiment of the present application includes the chip packaging structure in any of the above implementations. Therefore, the electronic device provided by the embodiment of the present application and the chip packaging structure of the above technical solution can solve the same technical problem and achieve the same expected effect. .
- Figure 1 is a schematic structural diagram of a chip packaging structure in the prior art
- Figure 2 is a schematic diagram of a partial structure of an electronic device
- Figure 3 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application.
- Figure 4a is a schematic structural diagram of a substrate in the chip packaging structure according to the embodiment of the present application.
- Figure 4b is a schematic structural diagram of another substrate in the chip packaging structure according to the embodiment of the present application.
- Figure 4c is a schematic structural diagram of another substrate in the chip packaging structure according to the embodiment of the present application.
- Figure 5 is a side view of the heat dissipation cover in the chip packaging structure according to the embodiment of the present application.
- Figure 6 is a view in direction A of Figure 5;
- Figure 7 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application.
- Figure 8 is a structural schematic diagram of a chip packaging structure in the related art that is warped
- Figure 9 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application.
- Figure 10 is a schematic diagram of the positional relationship between the substrate, the chip and the adhesive pillar in the chip packaging structure according to the embodiment of the present application;
- Figure 11 is another schematic diagram of the positional relationship between the substrate, the chip and the adhesive pillar in the chip packaging structure according to the embodiment of the present application;
- Figure 12 is another schematic diagram of the positional relationship between the substrate, the chip and the adhesive pillar in the chip packaging structure according to the embodiment of the present application;
- Figure 13a is a scanned image of the chip packaging structure without adhesive posts
- Figure 13b is a scanned image of a chip packaging structure provided with adhesive pillars
- Figure 14 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application.
- Figure 15 is a schematic diagram of the connection relationship between the heat dissipation cover and the substrate in the chip packaging structure according to the embodiment of the present application;
- Figures 16a and 16b are schematic diagrams of the positional relationship between the boss on the heat dissipation cover and the adhesive pillar according to the embodiment of the present application;
- Figures 17a and 17b are another schematic diagram of the positional relationship between the boss on the heat dissipation cover and the adhesive pillar according to the embodiment of the present application;
- Figures 18a and 18b are another schematic diagram of the positional relationship between the boss on the heat dissipation cover and the adhesive pillar according to the embodiment of the present application;
- Figure 19 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application.
- Figure 20a is a schematic diagram of the positional relationship between the substrate, the chip and the pulling column in the chip packaging structure of the embodiment of the present application;
- Figure 20b is a schematic diagram of another positional relationship between the substrate, the chip and the pulling column in the chip packaging structure of the embodiment of the present application;
- Figure 20c is a schematic diagram of another positional relationship between the substrate, the chip and the pulling column in the chip packaging structure of the embodiment of the present application;
- Figure 21 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application.
- Figure 22 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application.
- Figure 23 is a schematic structural diagram of the protruding portion in the chip packaging structure according to the embodiment of the present application.
- Figure 24 is a schematic diagram of the positional relationship between the substrate, the chip and the protruding portion in the chip packaging structure according to the embodiment of the present application;
- Figure 25 is a schematic diagram of the positional relationship between the substrate, the chip and the protruding portion in the chip packaging structure according to the embodiment of the present application;
- Figure 26 is a schematic diagram of the positional relationship between the substrate, the chip and the protruding portion in the chip packaging structure according to the embodiment of the present application;
- Figure 27 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application.
- Figure 28 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application.
- Figure 29 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application.
- Figure 30 is a schematic diagram of the positional relationship between the substrate, the chip and the dummy chip in the chip packaging structure according to the embodiment of the present application;
- Figure 31 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application.
- Figure 32 is a schematic diagram of the positional relationship between the substrate, the chip and the dummy chip in the chip packaging structure according to the embodiment of the present application;
- Figure 33 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application.
- Figure 34 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application.
- Figure 35 is a flow chart of a method for preparing a chip packaging structure according to an embodiment of the present application.
- Figures 36a to 36d are schematic diagrams of the corresponding structures after completion of each step in the method for producing a chip packaging structure according to the embodiment of the present application;
- Figure 37 is a flow chart of another method of preparing a chip packaging structure according to an embodiment of the present application.
- Figures 38a to 38c are schematic diagrams of the corresponding structures after completion of each step in the method for producing a chip packaging structure according to the embodiment of the present application;
- Figure 39 is a flow chart of another preparation method of the chip packaging structure according to the embodiment of the present application.
- 40a to 40d are schematic structural diagrams of the corresponding structures after completion of each step in the method for manufacturing a chip packaging structure according to an embodiment of the present application.
- 02-chip 021-first chip; 022-second chip; 023-third chip; 024-fourth chip;
- 03-Heat dissipation cover 031-Outer edge part; 032-Central part;
- 04-Thermal interface material layer 041-The first thermal interface material layer; 042-The second thermal interface material layer;
- 071-bonding glue column 071a-first bonding glue column; 071b-second bonding glue column;
- An embodiment of the present application provides an electronic device.
- the electronic device may include a mobile phone (mobile phone), a tablet computer (pad), smart wearable products (such as smart watches, smart bracelets), virtual reality (VR) devices, augmented reality (AR), It can also be equipment such as household appliances.
- the embodiments of the present application do not place special restrictions on the specific forms of the above-mentioned electronic devices.
- the above-mentioned electronic device may include a printed circuit board (PCB) 100 and a chip packaging structure 300.
- the chip packaging structure 300 is electrically connected to the PCB 100 through the electrical connection structure 200, so that the chip packaging structure 300 can achieve signal interconnection with other chips or other electronic modules on the PCB 100.
- the electronic device may also include a heat sink 400 .
- the heat sink 400 covers the chip packaging structure 300 and other electronic modules on the PCB 100 , and is fixedly connected to the PCB 100 .
- the heat sink 400 here serves as a heat dissipation structure and can dissipate and cool down the chip packaging structure 300 and other electronic modules on the PCB 100 .
- the heat sink 400 can also provide physical protection to the chip packaging structure 300 .
- the electrical connection structure 200 may include a plurality of solder balls, such as a ball grid array (BGA), or a plurality of metal pillars.
- BGA ball grid array
- the above-mentioned chip packaging structure 300 may be a structure in which multiple dies are packaged.
- the chip packaging structure 300 may be a processor, including a dynamic random access memory (DRAM) and a system on chip (SOC), or may include a system on chip SOC, an analog chip, etc., or it may Including analog chips and other digital chips.
- DRAM dynamic random access memory
- SOC system on chip
- FIG. 3 is a schematic cross-sectional view of a chip packaging structure 300 provided by an embodiment of the present application.
- the chip packaging structure 300 includes: multiple chips, which are integrated on the substrate 01 , and the multiple chips are located on the substrate 01 on the same surface.
- FIG. 3 exemplarily shows that the first chip 021 and the second chip 022 are integrated on the substrate 01 .
- FIG. 3 is only an exemplary structure, and more chips can also be provided on the substrate 01 .
- this application relates to a chip integrated on the substrate 01, which may be one chip or multiple chips stacked in three dimensions.
- the first chip 021 in FIG. 3 may refer to one chip
- the second chip 022 may include multiple chips stacked in three dimensions.
- the three-dimensional stacking here refers to stacking in a direction perpendicular to the substrate 01 .
- any chip can be electrically connected to the substrate 01 through a controlled collapse chip connection (C4) 05, and a metal layer is formed in the substrate 01 , the metal layer includes wiring structures.
- the substrate 01 establishes signal paths between chips or between chips and other electronic devices through the wiring structure.
- the chip here refers to a chip that can realize electrical functions.
- the chip When the chip is disposed on the substrate 01, it can use flip-chip ball grid array (FCBGA) technology.
- FCBGA flip-chip ball grid array
- the active surface of the chip faces the substrate 01
- the passive surface of the chip faces away from the substrate 01
- the active surface of the chip is arranged on the substrate 01 through the BGA electrical connection structure.
- the passive surface here can be understood as the substrate of the chip
- the active surface can be understood as the part of the chip that integrates electronic devices such as transistors and metal wiring.
- wire bonding technology can also be used to place the chip on the substrate 01.
- the substrate 01 involved in this application has a variety of structures that can be implemented.
- the substrate 01 may be a packaging substrate 01a shown in FIG. 4a.
- the packaging substrate 01a includes a substrate 011 and a rewiring structure 01b located on the upper surface and lower surface of the substrate 011.
- the substrate 01 may be a redistribution layer (RDL) 01b produced through a redistribution process as shown in FIG. 4b.
- the RDL01b includes a multi-layer metal trace 012 and a multi-layer dielectric layer 013. Each adjacent layer The two layers of metal traces 012 are separated by a dielectric layer 013 .
- a conductive channel 014 can be made in the dielectric layer 013 so that the metal traces 012 on different layers are electrically connected through the conductive channel 014 .
- RDL01b is used as the substrate, the flexibility of the substrate can also be improved and the warpage of the package can be suppressed.
- the substrate 01 may be an interposer 01c shown in FIG. 4c.
- the interposer 01c includes a substrate 011, a rewiring layer RDL01b integrated on the substrate 011, and a conductive channel penetrating the substrate 011. 014, the conductive channel 014 is electrically connected to the metal traces in the redistribution layer RDL01b.
- a glue dispensing process can be used to fill an underfill layer (underfill) 06 between the first chip 021 and the substrate 01, and The primer layer 06 is filled between the second chip 022 and the substrate 01 .
- the chip packaging structure 300 also includes a heat dissipation cover (Lid) 03.
- the heat dissipation cover 03 covers the side of the multiple chips away from the substrate 01 and is fixedly connected to the substrate 01.
- the heat dissipation cover 03 is connected to the upper surface of the chip through a thermal interface material (TIM) layer.
- TIM thermal interface material
- the upper surface of the first chip 021 is connected to the heat dissipation cover 03 through the first TIM layer 041
- the upper surface of the second chip 022 is connected to the heat dissipation cover 03 through the second TIM layer 042 .
- the heat dissipated by the first chip 021 and the second chip 022 will be conducted to the heat dissipation cover 03 through the corresponding first TIM layer 041 and the second TIM layer 042, and the heat will be dissipated through the heat dissipation cover 03 with a larger heat conduction area. Diffuse out to cool down the first chip 021 and the second chip 022 to ensure the normal operation of these chips.
- the first TIM layer 041 and the second TIM layer 042 in FIG. 3 can be made of the same material or different materials.
- Figures 5 and 6 show one possible structure of the heat dissipation cover 03, and Figure 5 shows a axial side view of the heat dissipation cover 03, and Figure 6 shows a view along the A direction of Figure 5.
- the heat dissipation cover 03 includes an outer edge part 031 and a central part 032.
- the outer edge part 031 is the part of the heat dissipation cover 03 that is fixedly connected to the substrate 01 as shown in Figure 2, that is, the part surrounding the periphery of multiple chips.
- the central part 032 is the part of the heat dissipation cover 03 that is located away from the multiple chips from the substrate 01. part of one side.
- the outer edge part 031 and the central part 032 are an integrally formed structure.
- the heat dissipation cover 03 including the outer edge portion 031 and the central portion 032 can be an integrally formed metal structural member.
- the outer edge part 031 and the central part 032 are two independent structural members, and the outer edge part 031 and the central part 032 are connected through a connecting structure.
- the outer edge portion 031 can be welded together with the central portion 032 through the welding layer 11 .
- the outer edge part 031 and the central part 032 are two independent structural members, the outer edge part 031 here may also be called a reinforcing ring.
- the materials of the reinforcing ring and central portion 032 may be the same or different.
- chip packaging structure 300 since it includes multiple chips, and these chips are integrated on the substrate 01 through electrical connection structures as shown in Figures 3 and 7, such a packaging structure can be called a multi-chip packaging structure.
- Chip module multi-chip module, MCM packaging. With the increase in the number and speed of chip cores, larger chips are gradually being used in MCM packaging structures. The CTE mismatch between larger chips and substrate 01 makes it more difficult to control thermal deformation of the package, and the degree of warpage is getting worse.
- FIG. 8 shows a structural diagram of a chip packaging structure 300 in the related art.
- the area of the substrate 01 where the second chip 022 is arranged forms a warped area due to the mismatch in thermal expansion coefficient, which further causes a larger distance between the area of the substrate 01 where the first chip 021 is arranged and the heat dissipation cover 03 .
- the third The first TIM layer 041 delaminates, and the second chip 022 will also warp along with the substrate 01, causing delamination to occur at the edge of the second TIM layer 041.
- Figure 8 is only to illustrate an exemplary structure of the risk of delamination occurring in the TIM layer, and does not include all situations where delamination occurs.
- pulling posts 07 can be provided in the chip packaging structure 300 .
- the central part 032 of the heat dissipation cover 03 and the substrate 01 are pulled together by using the pulling column 07, so that the degree of warpage can be reduced.
- FIG. 9 is a structural diagram of a chip packaging structure 300 provided in this application, which includes a pulling column.
- the pulling column includes an adhesive (AD) column 071.
- the adhesive column 071 is located between the central part 032 of the heat dissipation cover 03 and the substrate 01, and the adhesive column 071 is close to the part of the heat dissipation cover 03. It is bonded to the central part 032, and the part close to the base plate 01 is bonded to the base plate 01.
- the shape of the adhesive pillar 071 involved in this application is not limited to a cylindrical structure.
- the adhesive layer structure located between the central part 032 of the heat dissipation cover 03 and the substrate 01 can be called adhesive.
- the principle of the adhesive post 071 to suppress the degree of warpage can be understood as follows: As shown in Figure 9, since the adhesive post 071 is bonded to the heat dissipation cover 03 and the substrate 01 respectively, the adhesive post 071 will give the heat dissipation cover The central part 032 of 03 exerts a downward pulling force f1. At the same time, the adhesive pillar 071 will also give the substrate 01 an upward pulling force f2. Then, even if warping occurs due to CTE mismatch between the chip and the substrate 01, for example, in the Q area as shown in Figure 9, the distance d between the heat dissipation cover 03 and the substrate 01 is larger than other areas.
- the chip packaging structure 300 also includes an adhesive layer 08 , through which the outer edge portion 031 of the heat dissipation cover 03 is fixedly connected to the substrate 01 . Therefore, in an achievable structure, the same material can be used to form the adhesive glue pillar 071 and the adhesive glue layer 08 .
- the material of the adhesive layer may be a silicone material or an epoxy resin material. This application does not specifically limit the material of the adhesive layer.
- the pulling column shown in Figure 9 above is an adhesive column made of adhesive glue. Then, when selecting the material of the TIM layer, you only need to choose a material with a relatively high thermal conductivity. For example, you can choose Polymers, metals or graphene, etc.
- Figure 10 shows a top view of a substrate 01 integrated with two chips.
- the two chips are the first chip 021 and the second chip 022 respectively, and the adhesive post 071 can be disposed between the first chip 021 and the second chip 022 .
- Figure 11 shows a top view of a substrate 01 integrated with four chips.
- the four chips are respectively the first chip 021 and the second chip 022, and the third chip 023 and the fourth chip 024.
- the adhesive pillar 071 is arranged in the center of the area surrounded by the four chips.
- the number of adhesive posts 071 can be selected in many ways.
- FIG. 12 shows a top view of the substrate 01 integrated with two chips.
- the two chips are the first chip 021 and the second chip 022 respectively.
- a plurality of adhesive glue posts 071 are provided between the first chip 021 and the second chip 022. These multiple adhesive glue posts 071 are arranged at intervals. cloth.
- both Figures 13a and 13b show the chip packaging structure 300, and the image is viewed from above the chip packaging structure 300 (ie, the upper side of the heat dissipation cover 03) through an ultrasonic scanning microscope (scanning acoustic microscope, SAM). ) scanned image.
- the chip packaging structure 300 shown in FIG. 13a does not have a scanned image of the adhesive glue column 071 involved in this application, while the chip packaging structure shown in FIG. 13b includes a scanned image of the adhesive glue column 701.
- Both Figures 13a and 13b show four chips 02. It can be understood that Figure 13b is a structural diagram after adding adhesive posts 071 based on the structure shown in Figure 13a.
- FIG. 14 is a structural diagram of another chip packaging structure 300 provided in this application, which also includes a pulling column 07.
- the pulling column 07 includes an adhesive glue column 071 and a boss 072.
- the boss 072 is formed on the surface of the central part 032 of the heat dissipation cover 03 facing the substrate 01.
- One end of the adhesive glue column 071 is connected to the boss 072.
- the other end of the bonding glue post 071 is bonded to the substrate 01.
- the pulling structure shown in Figure 14 is similar to the pulling column shown in Figure 9 in the above-mentioned principle of suppressing warpage of the package. That is, as shown in Figure 14, since one end of the adhesive glue column 071 is bonded to the boss 072 of the heat dissipation cover 03, a downward pulling force f1 will be exerted on the heat dissipation cover 03, and because the adhesive glue column 071 The other end is bonded to the substrate 01, which will give the substrate 01 an upward pulling force f2.
- the adhesive pillar 071 in this embodiment can be the same as the adhesive pillar 071 in FIG. 9 , and the same material as the adhesive layer 08 can be selected.
- the boss 072 can be an integrally formed structure with the central portion 032 of the heat dissipation cover 03 . It can also be that the boss 072 and the central part 032 of the heat dissipation cover 03 are structural parts independent of each other, and the boss 072 is fixedly connected to the central part 032 of the heat dissipation cover 03 through a connecting structure. For example, the boss 072 is connected to the central part 032 of the heat dissipation cover 03 through a welding structure. The heat sink cover 03 is connected together.
- Figure 15 shows the assembly relationship between the heat dissipation cover 03 and the substrate 01 of the present application.
- the distance between the surface of the boss 072 facing the substrate 01 and the substrate 01 is d1.
- the distance is d2, and d1 is greater than or equal to d2.
- Figure 15 shows that d1 is greater than d2.
- d1 is greater than or equal to d2
- the boss 072 causes the heat dissipation cover 03 to exert greater stress on the chip.
- the heat dissipation cover 03 shown in Figure 15 is used, the risk of damage to the chip caused by large stress can be eliminated.
- Figure 16a shows a top view of the substrate 01 integrated with two chips
- Figure 16b shows a bottom view of the heat dissipation cover 03 with a boss 072 (i.e. View from direction B in Figure 15).
- an adhesive glue post 071 is provided on the substrate 01.
- a boss 072 bonded to the adhesive glue post 071 can be provided on the central part 032 of the heat dissipation cover 03.
- Figure 17a shows a top view of the substrate 01 integrated with two chips
- Figure 17b shows a bottom view of the heat dissipation cover 03 with the boss 072.
- a plurality of adhesive posts 071 are provided on the substrate 01.
- a plurality of bosses 072 can be provided on the central part 032 of the heat dissipation cover 03, and the plurality of bosses 072 are connected to The plurality of bonding glue posts 071 are bonded one-to-one.
- Figure 18a shows a top view of the substrate 01 integrated with two chips
- Figure 18b shows a bottom view of the heat dissipation cover 03 with the boss 072.
- a plurality of adhesive posts 071 are provided on the substrate 01.
- a boss 072 can be provided on the central part 032 of the heat dissipation cover 03, and a plurality of adhesive posts 071 All are bonded to the one boss 072.
- FIG. 19 is a structural diagram of another chip packaging structure 300 provided in this application, which also includes a pulling column 07.
- the pulling column 07 includes a first bonding glue column 071a, a second bonding glue column 071b, and a support column 073.
- the support column 073 is located between the first bonding glue column 071a and the second bonding glue column 071b.
- the first adhesive glue pillar 071a is bonded to the central portion 032 of the heat dissipation cover 03
- the second adhesive glue pillar 071b is bonded to the substrate 01.
- the support pillar 073 can be made of glass; as another example, the support pillar 073 can be made of a metal block. Of course, you can also choose other support pillars 073 with greater hardness.
- the first adhesive glue column 071a and the second adhesive glue column 071b here can be selected from the same material as the adhesive glue layer 08.
- the pulling column 07 is used to form a pulling force between the heat dissipation cover 03 and the substrate 01 to prevent the heat dissipation cover 03 and the substrate from being caused by warping. Some areas of 01 produce larger distances.
- the arrangement position of the pulling column 07 can be understood as: the rectangle enclosed by the orthographic projections of the multiple chips of the present application on the substrate 01 can be called the first area, and the orthogonal position of the pulling column 07 on the substrate 01 The projection is located within this first area.
- Figure 20a shows a top view of the substrate 01 integrated with two chips.
- the two chips include a first chip 021 and a second chip 022.
- the orthographic projections of the first chip 021 and the second chip 022 on the substrate 01 have boundaries B1, B2, B3 and B4, and the boundaries B1, B2,
- the area M enclosed by the boundary B3 and the boundary B4 is a rectangle. It can be understood that the rectangular area M is the above-mentioned first area.
- Figure 20b also shows a top view of the substrate 01 integrated with two chips.
- the two chips include a first chip 021 and a second chip 022, and the orthographic projections of the first chip 021 and the second chip 022 on the substrate 01 have boundaries B1, B2, B3 and B4, and the boundaries B1, B4
- the area M enclosed by B2, the boundary B3 and the boundary B4 is a rectangle. It can be understood that the rectangular area M is the above-mentioned first area.
- Figure 20c shows a top view of a substrate 01 integrated with three chips.
- the three chips include the first chip 021, the second chip 022, and the third chip 023, and the orthographic projections of the first chip 021, the second chip 022, and the third chip 023 on the substrate 01 have boundaries B1, B2,
- the boundary B3 and the boundary B4, and the area M enclosed by the boundary B1, the boundary B2, the boundary B3 and the boundary B4 is a rectangle. It can be understood that the rectangular area M is the above-mentioned first area.
- the orthographic projection of the central part 032 of the heat dissipation cover 03 and the pulling column of the base plate 01 involved in this application is located in the first area. Compared with arranging the pulling column outside the first area, greater stress will not be generated on some chips, and therefore, the chip can be protected.
- Figure 21 shows a structural diagram of a chip packaging structure 300, and the chip packaging structure 300 includes a protruding portion 09.
- the protruding portion 09 is formed on the central portion 032 of the heat dissipation cover 03 toward the substrate. 01, and is in contact with the thermal interface material layer.
- the protruding portion 09 is formed with a pressing surface 09a, and the pressing surface 09a is in contact with the thermal interface material layer.
- the central portion 032 of the heat dissipation cover 03 has a protruding portion 09 that can press against the TIM layer, during the process flow, when the first chip 021 and the second chip 022 are both Integrated on the substrate 01, and after covering the heat dissipation cover 03 on the chip, when the heat sink 400 shown in Figure 2 is installed on the heat dissipation cover 03, the heat sink 400 presses the heat dissipation cover 03, and the protruding portion 09 is easily deformed so that the pressing surface presses against the TIM layer and is closely attached to the TIM layer, thereby preventing the delamination of the TIM layer and improving the heat dissipation performance of the chip.
- the protruding portion 09 can be an integrally formed structure with the heat dissipation cover 03, or can be connected with the heat dissipation cover 03 through a welding process.
- FIG. 22 shows a structural diagram of yet another chip packaging structure 300.
- the chip packaging structure 300 also includes a protruding portion 09 that can abut on the TIM layer.
- the difference from the protruding portion 09 shown in FIG. 21 is that the pressing surface 09a of the protruding portion 09 is opposite to the chip. Inclined surface for tilt settings. For example, along the direction from the central part 032 of the heat dissipation cover 03 to the substrate 01, that is, along the P direction shown in FIG. 22, any of the pressing surfaces 09a extends from the edge of the area surrounded by the plurality of chips toward It is inclined close to the center of the area surrounded by the plurality of chips.
- the surface of the chip facing the heat dissipation cover 03 is generally an inclined surface.
- the pressing surface 09a is designed to be inclined relative to the chip. Inclined surface, in this case, can make the pressing surface 09a fit more closely to the TIM layer to further prevent gaps between the TIM layer, the chip and the heat dissipation cover.
- a protruding portion 09 with a gentle slope as shown in Figure 23 can be formed on the surface of the heat dissipation cover 03 facing the substrate 01, where the gentle slope is the inclined pressing surface 09a shown in Figure 23.
- the number of gentle slopes is equal to the number of chips. For example, when four chips are installed on the substrate 01, it can be designed as a protrusion 09 with four gentle slopes as shown in Figure 23, and Four gentle slopes (that is, the pressing surfaces 09 a ) are arranged along the circumferential direction of the protruding portion 09 .
- the pressing surface 09a can be an inclined plane; in other structures that can be implemented, the pressing surface 09a can also be an inclined curved surface. If the pressing surface 091a is a curved surface, the curvature of the curved surface can be designed according to the degree of chip warpage.
- the area size or the inclination angle of the pressing surface 09a is not specifically limited in this application, and can be determined based on the position where the TIM layer is prone to delamination.
- Figure 24 shows a top view of the substrate 01 integrated with two chips, and Figure 24 reflects the positional relationship between the protruding portion 09 and the two chips.
- the two chips include a first chip 021 and a second chip 022.
- the orthographic projection of the protruding portion 09 on the substrate 01 is located in the first area. This first area has been introduced above and will not be repeated here.
- the protruding portion 09 is located in the first area. Part 09 is close to the center of the first area.
- a structure formed on the heat dissipation cover can act on multiple chips at the same time.
- the resisting force exerted by the protruding portion 09 on different chips remains basically the same. In this case, there will be no There is a problem of large stress in parts of the entire packaging structure.
- Figure 25 shows a top view of the substrate 01 integrated with four chips, and Figure 25 reflects the positional relationship between the protruding portion 09 and the four chips.
- the four chips include the first chip 021 and the second chip 022, and the third chip 023 and the fourth chip 024.
- the orthographic projection of the protrusion 09 on the substrate 01 is located in the first area, and , the protruding portion 09 is close to the center of the first area.
- Figure 26 shows a top view of the substrate 01 integrated with four chips, and Figure 26 shows the positional relationship between the protruding portion 09 and the four chips.
- Figure 25 shows that the first chip 021 and the second chip 022 are also integrated on the substrate 01, as well as the third chip 023 and the fourth chip 024.
- the difference from the above Figure 25 is that the protruding portion 09 is close to the The edge setting of an area.
- the above-mentioned protruding portion 09 and adhesive glue pillar 071 can be integrated into a chip packaging structure 300.
- the protruding portion 09 is formed On the surface of the central portion 032 of the heat dissipation cover 03 facing the substrate 01, and the protruding portion 09 is formed with a pressing surface 09a that presses against the TIM layer, and an adhesive glue column 071 is provided between the protruding portion 09 and the substrate 01 , that is, one end of the adhesive pillar 071 is bonded to the protruding portion 09 , and the other end of the adhesive pillar 071 is bonded to the substrate 01 .
- the protruding portion 09 in Figure 27 can be located at a position on the heat dissipation cover 03, and the bonding position of the adhesive post 071 and the heat dissipation cover 03 is not on the protruding portion 09, but on the heat dissipation area. Cover 03 at another location.
- Figure 28 also shows a chip packaging structure 300, in which the above-mentioned pulling posts and protrusions are integrated.
- a protrusion 09 can be formed on the surface of the central portion 032 of the heat dissipation cover 02 facing the substrate 01 , and a support column 073 is provided on the substrate 01 , and the support column 073 is connected to the protrusion through an adhesive glue column 071 09glued together.
- this application also provides some implementable methods that can suppress the degree of warpage and weaken the delamination of the TIM layer, as detailed below.
- the first chip 021 and the second chip 022 are also integrated with a dummy die 10 on the substrate 01, and the dummy die 10 and multiple chips for signal interconnection are integrated on the same surface of the substrate 01.
- the fake chip 10 involved in this application is a chip that has no signal interconnection with other chips.
- the warpage mutation of the entire package can be reduced, and further, the warpage mutation of the entire package can be eliminated.
- the position of the dummy chip 10 on the substrate 01 is: the rectangle surrounded by the orthographic projections of the multiple chips on the substrate 01 is the first area, and the orthographic projection of the dummy chip 10 on the substrate 01 is located in the first area, that is, this
- the definition of the first area at is the same as the definition of the first area mentioned above.
- the first area can also be understood as the structure shown in Figure 30.
- Figure 30 shows a top view of the substrate 01 integrated with four chips, and Figure 30 reflects the positional relationship between the dummy chip 10 and the four chips. .
- the first chip 021 and the second chip 022, the third chip 023 and the fourth chip 024, the first chip 021 and the second chip 022, and the third chip 023 and the fourth chip 024 are provided on the substrate 01
- the orthographic projection on the substrate 01 has boundaries B1, B2, B3 and B4, and the area M enclosed by the boundaries B1, B2, B3 and B4 is a rectangle and can be understood as the above-mentioned first area.
- the orthographic projection of the dummy chip 10 on the substrate 01 is within the area M.
- Figure 32 shows a top view of the substrate 01 integrated with two chips
- Figure 32 reflects the positional relationship between the two dummy chips 10 and the two chips.
- the first chip 021 and the second chip 022 are provided on the substrate 01
- the orthographic projection of the first chip 021 and the second chip 022 on the substrate 01 has boundaries B1, B2, B3 and B4
- the area M enclosed by the boundaries B1, B2, B3 and B4 is a rectangle
- the orthographic projections of the two dummy chips 10 on the substrate 01 are all within the area M.
- the dummy chip 10 By designing the dummy chip 10 in this way, compared with arranging the dummy chip 10 outside the area M, the area of the substrate 01 will not be increased, and further, the size of the entire package structure will not be increased.
- this application does not limit the number of dummy chips 10.
- one dummy chip 10 can be provided on the substrate 01; as another example, see Figure 32, one dummy chip 10 can be provided on the substrate 01. Set at least two dummy chips 10 on it.
- the first chip 021, the second chip 022, the third chip 023 and the fourth chip 023 form a rectangular structure
- the first chip 021, the second chip 022, the third chip 023 and the fourth chip 023 form a rectangular structure
- the third chip 023 and the fourth chip 024 are arranged close to the corners of the rectangular structure
- a dummy chip 10 is arranged close to the center of the rectangular structure.
- the first chip 021, the second chip 022, and the two dummy chips 10 form a rectangular structure, and the first chip 021 and the second chip 022 are arranged on the first diagonal of the rectangular structure.
- two dummy chips 10 are arranged on the second diagonal line A2 of the rectangular structure, and the first diagonal line A1 and the second diagonal line A2 intersect.
- the area of the dummy chip 10 can be smaller than the area of the chip. In this case, using a smaller area dummy chip can make full use of the comparison between chips. Small unused space.
- the dummy chip 10 and the above-mentioned protruding portion 09 can be combined and integrated into a chip packaging structure 300 .
- the chip packaging structure 300 shown in Figure 33 includes a dummy chip 10 and a protruding portion 09 formed on the heat dissipation cover 03, and an adhesive pillar 071 is used to bond the dummy chip 10 to the protruding portion 09. together.
- Figure 34 is a cross-sectional view of Figure 32, that is, the protruding portion 09 may not be provided, but the dummy chip 10 can be directly Bond it with the heat dissipation cover through adhesive glue post 071.
- a chip packaging structure 300 not only the dummy chip 10 but also the pulling column 07 and the protruding portion 09 can be provided.
- the achievable structure of improving the TIM layering by arranging the dummy chip 10 can be combined with the achievable structure of improving the TIM layering by arranging the pulling column 07 and the protruding portion 09 mentioned above.
- the obtained chip packaging structures are all within the scope of protection of this application.
- the embodiment of the present application also provides a method for preparing the chip packaging structure 300.
- the preparation method includes:
- a pulling column is provided on the surface of a substrate with multiple chips.
- a rectangle surrounded by orthographic projections of multiple chips on the substrate is the first area, and the orthographic projection of the pulling column on the substrate is located in the first area.
- the heat dissipation cover is arranged so that the heat dissipation cover covers the central portion of the plurality of chips on the side away from the substrate and is fixedly connected to the substrate through the pulling column.
- the pulling column is provided so that the pulling column generates pulling force to the central part of the heat dissipation cover and the substrate respectively. Then, when the substrate integrated with multiple chips changes in temperature, through the The pulling force can prevent the distance between the heat dissipation cover and the substrate from suddenly changing, so that large warping will not occur. In this case, some problems that affect the performance of the chip will not be derived. For example, the distance between the chip and the substrate will not be TIM layering between thermal covers.
- Step S11 Referring to Figure 36a, multiple chips 02 are arranged on the substrate 01.
- Step S12 Referring to FIG. 36b, dispensing glue along the circumference of the edge of the substrate 01, and dispensing glue at a position of the substrate 01 opposite to the central part of the heat dissipation cover 03.
- the glue When dispensing glue at a position opposite to the central portion of the heat dissipation cover of the substrate 01 , the glue may be dispensed at a central position close to the first area of the orthographic projection of the plurality of chips on the substrate.
- Step S13 Referring to FIG. 36c, form a TIM layer 04 on the surface of the chip 02 away from the substrate 01.
- Step S14 Combined with Figure 36d, install the heat dissipation cover 03.
- an adhesive layer 08 for bonding with the outer edge of the heat dissipation cover and a central part of the heat dissipation cover can be formed on the substrate 01
- the surface of the heat dissipation cover 03 facing the substrate 01 also has a protrusion. Then, when the heat dissipation cover 03 is covered on the multiple chips 02, the pressing surface of the protrusion will be located at the TIM of the chip. Then, when a heat sink is installed on the heat dissipation cover of the chip packaging structure, the protruding portion will deform under the force of the heat sink to press against the TIM layer.
- At least one dummy chip may also be integrated on the substrate 01.
- the embodiment of the present application also provides another method for preparing the chip packaging structure 300.
- the preparation method includes:
- any one of the multiple chips is arranged on the substrate through an electrical connection structure
- thermal interface material layer on a surface of any one of the plurality of chips away from the substrate
- the heat dissipation cover is provided such that one or more protrusions on the central portion of the heat dissipation cover are in contact with the thermal interface material layer of at least one chip among the plurality of chips; wherein the central portion of the heat dissipation cover is covered by the heat dissipation cover.
- One or more protrusions are provided on the surface of the central portion of the heat dissipation cover facing the substrate on the portion of the plurality of chips on the side away from the substrate.
- Step S21 Referring to Figure 38a, multiple chips 02 are arranged on the substrate 01.
- Step S22 Referring to FIG. 38b, form a thermal interface material layer 04 on the surface of any chip 02 away from the substrate 01.
- Step S23 With reference to Figure 38c, install the heat dissipation cover 03; wherein, the central portion 032 of the heat dissipation cover 03 has a protruding portion 09 on the surface facing the substrate, and the protruding portion 09 abuts the thermal interface of at least one chip among the plurality of chips. on material layer 04.
- At least one dummy chip may also be integrated on the substrate 01. That is, the degree of warpage of the package is suppressed by the dummy chip 10 integrated on the substrate 01 .
- an adhesive layer may also be formed on the upper surface of the dummy chip 10 so as to be pulled together with the protruding portion through the adhesive layer.
- glue can also be dispensed on the substrate 01 at a position facing the protruding portion, so that the protruding portion and the substrate are pulled together by the cured adhesive glue. Together.
- the embodiment of the present application also provides another method for preparing the chip packaging structure 300.
- the preparation method includes:
- any one of the multiple chips is arranged on the substrate through an electrical connection structure
- One or more dummy chips are arranged on the surface of the substrate on which multiple chips are arranged, and the orthographic projection of the one or more dummy chips on the substrate is located in the first area, and the orthographic projection of the plurality of chips on the substrate forms a rectangle. is the first area;
- the heat dissipation cover is arranged so that the central part of the heat dissipation cover covers the side of the plurality of chips away from the substrate.
- Step S31 Referring to FIG. 40a, multiple chips 02 and at least one dummy chip 10 are arranged on the substrate 01.
- Step S32 Referring to Figure 40b, form a thermal interface material layer 04 on the surface of any chip 02 away from the substrate 01.
- Step S33 Referring to Figure 40c, glue is applied to the surface of the dummy chip 10 away from the substrate 01.
- step S32 and step S33 can be executed simultaneously or in two steps one after another.
- Step S34 In conjunction with FIG. 40d, install the heat dissipation cover 03 so that the central portion 032 of the heat dissipation cover 03 covers the side of the plurality of chips and one or more dummy chips away from the substrate 01.
- the substrate 01 is pulled together with the heat dissipation cover 03 through the dummy chip 10 and the adhesive glue. Suppress the warpage of the entire package.
- the material of the adhesive on the dummy chip 10 may be the same as the material of the adhesive layer 08 on the outer edge of the substrate 01 .
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Abstract
本申请实施例提供一种芯片封装结构、电子设备及芯片封装结构的制备方法,涉及芯片封装技术领域,可以降低热界面材料TIM出现分层的风险。该芯片封装结构包括基板,设置在基板上的多个芯片,设置在基板上、用于对多个芯片进行散热的散热盖,以及用于形成散热通道的TIM层。散热盖的中心部分朝向基板的方向具有凸出部。该凸出部通过抵接在这些芯片的TIM层上,将TIM层材料抵压。由于具有能够抵压在TIM层上的凸出部,那么,将散热盖覆盖在芯片上后,再在散热盖上安装其他结构件时,这些结构件会对散热盖施加朝向芯片的压力,这样的话,凸出部发生变形,就会对TIM层产生抵压力,以与TIM层贴紧,因此凸出部有助于降低TIM出现分层的可能性。
Description
本申请涉及芯片封装技术领域,尤其涉及一种芯片封装结构、电子设备及芯片封装结构的制备方法。
随着高速数据通信和人工智能对算力的需求激增,芯片集成度进一步提升。其中,多芯片合封技术被广泛采用。多芯片合封也可以被称为多芯片模组(multi-chip module,MCM)封装,MCM封装可以有效地缩短传统单芯片之间的互联走线长度,为高密度和高可靠性封装提供了可行性。
随着MCM封装技术的发展,芯片与基板的热膨胀系数(coefficient of thermal expansion,CTE)失配会让封装热变形控制变得越来越困难,封装热变形变大会直接导致整个芯片封装结构发生较大的翘曲(warpage)。这里的热膨胀系数CTE可以理解为:在基板上安装芯片的过程中,或者,芯片已经被集成在基板上后,由于温度改变而使得集成有芯片的基板产生胀缩现象,在胀缩中,单位温度变化所导致的体积变化,可以用热膨胀系数CTE表示。
在如图1所示的芯片封装结构中,两个芯片02均被设置在基板01上,散热盖(Lid)03覆盖在两个芯片02上,并与基板01固定连接。并且,在芯片02与散热盖03之间设置有热界面材料(thermal interface material,TIM)层04。
封装过程中,由于芯片02与基板01之间可能存在CTE失配现象,因此使得两个芯片集成在基板01后,在温度变化时产生翘曲。进而,发生翘曲的基板01与散热盖03之间容易产生较大的距离,这样的话,很容易导致TIM层04、散热盖03、芯片02之间出现分层风险。简单理解的就是,如图1所示的,可能是TIM层04与芯片02之间出现缝隙d,或者,TIM层04与散热盖03之间出现缝隙(Gap),又或者,TIM层04与芯片02之间,以及,TIM层04与散热盖034之间均出现缝隙。
如此一来,就会增加芯片02的散热路径中的热阻,容易导致芯片02出现高温风险,从而影响芯片02的工作性能。
发明内容
本申请的实施例提供一种芯片封装结构、电子设备及芯片封装结构的制备方法。主要目的是提供一种可以削弱TIM层分层风险的芯片封装结构。
为达到上述目的,本申请的实施例采用如下技术方案:
一方面,本申请提供了一种芯片封装结构,该芯片封装结构是一种多芯片模组MCM封装结构。
该芯片封装结构可以包括:基板、集成在基板上的多个芯片和散热盖,多个芯片位于基板的同一表面上,且多个芯片中的任一个芯片均通过电连接结构(比如,焊接 层)设置在基板上,散热盖包括覆盖在多个芯片的远离基板一侧的中心部分,和环绕在多个芯片***的且与基板固定连接的外沿部分。还有,多个芯片中的任一个芯片的远离基板的表面与中心部分之间均形成有热界面材料层;其中,散热盖的中心部分的朝向基板的表面具有一个或多个凸出部,且一个或多个凸出部抵接在多个芯片中至少一个芯片的所述热界面材料层上。
本申请给出的芯片封装结构中,由于在散热盖的中心部分和热界面材料层之间设置有凸出部,也就是,通过与散热盖固定连接的凸出部可以压紧在热界面材料层上。这样一来,当把散热盖覆盖在多个芯片上后,即使芯片与基板之间因为存在CTE失配现象,而导致承载有芯片的基板发生翘曲时,会通过凸出部压紧在热界面材料层上,以防止热界面材料层与芯片之间发生分层的风险,如此的话,可以降低芯片的散热热阻,提升对芯片的散热效果。
在一种可以实现的方式中,凸出部具有多个抵压面,多个抵压面一对一地抵接在多个热界面材料层上。
可以这样理解,由于凸出部具有能够抵压在TIM层上的多个抵压面,那么,将散热盖覆盖在芯片上后,再在散热盖上安装其他结构件时,比如,安装散热器时,散热器会对散热盖施加朝向芯片的压力,这样的话,凸出部就会发生变形对TIM层产生抵压力,以与TIM层贴紧,因此具有抵压面的凸出部有助于降低TIM出现分层的可能性。
在一种可以实现的方式中,凸出部靠近第一区域的中心设置,多个抵压面沿着凸出部的周向布置,多个芯片在基板上的正投影围成的矩形为第一区域;并且,沿着散热盖的中心部分至基板的方向,任一抵压面自第一区域的边缘朝靠近第一区域的中心倾斜。也就是说,抵压面是一种相对芯片倾斜设置的面。
采用倾斜设置的面,可以使得抵压面与发生翘曲的芯片上的TIM层更加的贴合,这样的话,会进一步的使得散热盖、TIM层和芯片紧密贴合。
在一种可以实现的方式中,抵压面可以是倾斜的平面,也可以是倾斜的曲面。
在一种可以实现的方式中,芯片封装结构还包括粘接胶柱,粘接胶柱位于凸出部和基板之间,且粘接胶柱的一端与凸出部粘接,另一端与基板粘接。
也就是说,可以利用粘接胶柱将凸出部与基板牵拉在一起,这样的话,利用粘接胶柱对散热盖和基板的牵拉力,而避免了基板的部分区域与散热盖之间具有较大的距离,即就是通过牵拉力来抵抗封装体的翘曲。
在一种可以实现的方式中,芯片封装结构还包括一个或多个假芯片,一个或多个假芯片和多个芯片位于基板的同一表面上;多个芯片在基板上的正投影围成的矩形为第一区域,假芯片在基板上的正投影位于第一区域内。
在这个实施例中,通过在基板上设置假芯片,可以对基板的局部翘曲进行调整,进而可以起到抑制承载有多个芯片的基板的翘曲程度。最终,也可以削弱位于芯片和散热盖之间的TIM层的分层现象,可以降低芯片的散热热阻,提升对芯片的散热效果。
并且,由于假芯片在基板上的正投影位于第一区域内,这样的话,还不会因为设置假芯片而增加整个基板的面积。
在一种可以实现的方式中,假芯片位于凸出部和基板之间,并通过粘接胶层与凸 出部粘接。
也就是说,通过假芯片与凸出部的相结合,可以进一步的抑制翘曲程度。
在一种可以实现的方式中,外沿部分与中心部分为一体成型结构。
在一种可以实现的方式中,散热盖的外沿部分通过连接结构与散热盖的中心部分固定连接。比如,通过焊接结构将加固环与散热盖的中心部分固定连接在一起。
另一方面,本申请还提供了一种芯片封装结构,该芯片封装结构和上述芯片封装结构一样,也是一种多芯片模组MCM封装结构。
该芯片封装结构包括基板、集成在基板上的多个芯片和至少一个假芯片,以及,还包括散热盖,多个芯片位于基板的同一表面上,且多个芯片中的任一个芯片均通过电连接结构(比如,焊接层)设置在基板上,至少一个假芯片和多个芯片位于基板的同一表面上,散热盖包括覆盖在多个芯片和至少一个假芯片的远离基板一侧的中心部分,和环绕在所述多个芯片和至少一个假芯片***的,且与基板固定连接的外沿部分;其中,多个芯片在基板上的正投影围成的矩形为第一区域,至少一个假芯片在基板上的正投影位于第一区域内。
在本申请给出的芯片封装结构中,不仅包括了具有电气功能的芯片,还包括了没有电气功能的假芯片,通过在基板的局部位置设置假芯片,可以对基板的局部翘曲进行调整,进而可以起到抑制承载有多个芯片的基板的翘曲程度。最终,也可以削弱位于芯片和散热盖之间的TIM层的分层现象,可以降低芯片的散热热阻,提升对芯片的散热效果。
除此之外,由于多个芯片在基板上的正投影围成的矩形为第一区域,至少一个假芯片在基板上的正投影位于第一区域内,也就是说,充分利用芯片与芯片之间的闲置空间安置假芯片,这样的话,在能够抑制整个封装体翘曲程度的基础上,还不会增加基板的尺寸,不会增加整个封装结构的尺寸。
在一种可以实现的方式中,任一个假芯片的面积小于芯片的面积。
也就是说,利用芯片与芯片之间的闲置空间,设置较小尺寸的假芯片,来达到抑制翘曲程度的目的。
在一种可以实现的方式中,任一个假芯片的远离基板的表面通过粘接胶层粘接在中心部分上。
将假芯片通过粘接胶层与散热盖的中心部分粘接在一起,能够使得通过假芯片将散热盖和基板牵拉在一起,通过牵拉力,也可以抑制整个封装体的翘曲程度。
在一种可以实现的方式中,多个芯片包括第一芯片、第二芯片、第三芯片和第四芯片;至少一个假芯片为一个假芯片;第一芯片、第二芯片、第三芯片和第四芯片靠近第一区域的角落设置;一个假芯片靠近第一区域的中心设置。
在一种可以实现的方式中,多个芯片包括第一芯片和第二芯片;至少一个假芯片包括第一假芯片和第二假芯片;第一芯片和第二芯片位于矩形结构的第一对角线上,第一假芯片和第二假芯片位于矩形结构的第二对角线上,且第一对角线和第二对角线相交。
再一方面,本申请还提供了一种芯片封装结构,该芯片封装结构和上述两种芯片封装结构一样,也是一种多芯片模组MCM封装结构。
该芯片封装结构包括基板、集成在基板上的多个芯片,以及,还包括散热盖,多个芯片位于基板的同一表面上,且多个芯片中的任一个芯片均通过电连接结构(比如,焊接层)设置在基板上,散热盖包括覆盖在多个芯片的远离基板一侧的中心部分,和环绕在多个芯片***的且与基板固定连接的外沿部分;另外,芯片封装结构还包括牵拉柱,牵拉柱位于散热盖的中心部分和基板之间,牵拉柱在基板上的正投影位于第一区域内,多个芯片在基板上的正投影围成的矩形为第一区域,牵拉柱分别与散热盖的中心部分和基板固定连接。
本申请提供的芯片封装结构中,由于散热盖的中心部分通过牵拉柱与基板固定连接,这样的话,在制备时,当将多个芯片集成在基板上之后,即使芯片与基板之间因为存在CTE失配现象,而将要导致承载有芯片的基板发生翘曲时,会因为牵拉柱对基板和散热盖的牵拉力,而抑制承载有芯片的基板的翘曲程度,也可以这样理解,因为牵拉柱对基板的拉力,而避免了基板的部分区域与散热盖之间具有较大的距离,即就是通过牵拉结构来抵抗封装体的翘曲。
如此的话,由于承载有芯片的基板的翘曲程度被削弱了,这样,位于芯片和散热盖之间的TIM层基本不会出现分层现象,从而,可以降低芯片的散热热阻,提升对芯片的散热效果。在可以选择的结构中,对于TIM层可以选择的材料,只需要选择导热系数高的材料,不需再过多的考虑TIM层的粘接强度,这样一来,也不会对TIM层可以选择的材料有过多的限定。
还有,由于多个芯片在基板上的正投影围成的矩形为第一区域,牵拉柱在基板上的正投影位于第一区域内,相比将牵拉柱设置在第一区域的外部,不会对部分芯片产生较大的应力,因而,可以起到保护芯片的作用。
在一种可以实现的方式中,牵拉柱包括粘接胶柱,粘接胶柱的一端与散热盖的中心部分粘接,另一端与基板粘接。
也就是说,这里的牵拉柱可以采用粘接胶制得的结构,通过粘接胶的粘接力将散热盖的中心部分与基板牵拉在一起。
在一种可以实现的方式中,外沿部分通过环绕在多个芯片***的粘接胶层,与基板固定连接;且粘接胶柱和粘接胶层的材料相同。
这样的话,在制备工艺时,在基板上点粘接胶层时,可以同时点粘接胶柱。从而,在实现抑制芯片和基板翘曲程度的基础上,不会使得制备工艺变的复杂。
在一种可以实现的方式中,牵拉结构包括凸台和粘接胶柱,凸台形成在散热盖的中心部分的朝向基板的面上;粘接胶柱的一端与凸台粘接,另一端与基板粘接。
可以这样理解,可以在散热盖的中心部分设置朝基板凸出的凸台,除外,再设置粘接凸台和基板的粘接胶柱,以将散热盖上的凸台和基板牵拉在一起。
通过在散热盖上形成凸台,还可以增强该牵拉柱对散热盖和基板的牵拉强度。
在一种可以实现的方式中,凸台和散热盖的中心部分为一体成型结构。比如,可以为一体成型的金属件。
在一种可以实现的方式中,凸台的朝向基板的面,与基板之间的间距为d1;外沿部分的朝向基板的面,与基板之间的间距为d2;其中,d1大于或等于d2。
也就是说,形成在散热盖上的凸台不能太高,如果太高的话,可能会使得该封装 体产生较大的应力,该应力有可能会对芯片的性能造成影响。进而,在可以选择的结构中,可以使得散热盖的外沿部分与基板之间的间距d2,小于或等于凸台至基板之间的间距d1。
在一种可以实现的方式中,芯片封装结构还包括至少一个假芯片,至少一个假芯片和多个芯片位于基板的同一表面上,且所述的至少一个假芯片在基板上的正投影位于第一区域内。
也就是说,通过设置假芯片,也可以进一步的抑制整个封装体的翘曲程度。
在一种可以实现的方式中,芯片封装结构还包括粘接胶柱,粘接胶柱的一端与中心部分粘接,另一端与假芯片粘接。
在一种可以实现的方式中,牵拉柱包括粘接胶柱和支撑柱,粘接胶柱包括第一粘接胶柱和第二粘接胶柱;支撑柱的一端通过第一粘接胶柱与中心部分粘接,支撑柱的另一端通过第二粘接胶柱与基板粘接。
通过设置具有强度的支撑柱结构作为牵拉结构,在满足牵拉力的前提下,还可以提升牵拉柱的强度。
又一方面,本申请还提供了一种芯片封装结构的制备方法,该芯片封装结构的制备方法包括:
在基板的同一表面上设置多个芯片,且多个芯片中的任一个芯片均通过电连接结构设置在基板上;
在多个芯片的任一个芯片的远离基板的表面上形成热界面材料层;
设置散热盖,以使得散热盖的中心部分上的一个或者多个凸出部抵接在多个芯片中至少一个芯片的热界面材料层上;其中,散热盖的中心部分为散热盖的覆盖在多个芯片的远离基板一侧的部分,一个或者多个凸出部设置在散热盖的中心部分的朝向基板的表面上。
在本申请提供的芯片封装结构的制备方法中,由于散热盖的中心部分上具有一个或者多个凸出部,那么,当把散热盖安装后,凸出部就会抵接在热界面材料层上。进一步,当在散热盖上安装其他结构件时,比如,安装散热器时,散热器会对散热盖施加压力,在该压力的作用下,凸出部会发生变形,给热界面材料层挤压力,以降低热界面材料层发生分层的可能性。
在一种可以实现的方式中,在设置散热盖之前,制备方法还包括:在基板的用于与散热盖的中心部分相对的面上点粘接胶,以形成粘接胶柱,以使得在设置散热盖之后,粘接胶柱固定连接在基板和凸出部之间。
通过在基板上形成具有粘性的粘接胶柱,以将凸出部与基板牵拉在一起,这样的话,会抑制整个封装体的翘曲程度,也会改善热界面材料层发生分层风险。
在一种可以实现的方式中,在基板的用于与散热盖的中心部分相对的面上点粘接胶,制备方法还包括:沿着基板的外缘的周向点粘接胶,以形成粘接胶层,以使得散热盖的外沿部分通过粘接胶层与基板固定连接,且粘接胶柱和粘接胶层的材料相同;其中,散热盖的外沿部分为散热盖的环绕在多个芯片***的部分。
也就是说,在可以实现的工艺步骤中,可以采用点胶工艺,同时形成粘接胶层和粘接胶柱。
在一种可以实现的方式中,在设置散热盖之前,制备方法还包括:在设置多个芯片的基板的表面上设置一个或者多个假芯片,且一个或多个假芯片在基板上的正投影位于第一区域内,多个芯片在基板上的正投影围成的矩形为第一区域。
可以这样讲,通过在基板上设置无电气功能的假芯片,可以对基板的局部翘曲进行改善,从而,也可以削弱热界面材料层发生分层风险。
在一种可以实现的方式中,在设置一个或者多个假芯片之后,在设置散热盖之前,制备方法还包括:在一个或者多个假芯片的远离基板的表面上点粘接胶,以使得在设置散热盖之后,假芯片通过粘接胶与凸出部固定连接。
又一方面,本申请还提供了一种芯片封装结构的制备方法,该芯片封装结构的制备方法包括:
在基板的同一表面上设置多个芯片,且多个芯片中的任一个芯片均通过电连接结构设置在基板上;
在设置多个芯片的基板的表面上设置一个或者多个假芯片,且一个或多个假芯片在基板上的正投影位于第一区域内,多个芯片在基板上的正投影围成的矩形为第一区域;
设置散热盖,以使得散热盖的中心部分覆盖在多个芯片的远离基板一侧。
本申请给出的芯片封装结构的制备方法中,通过在基板上设置无电气功能的假芯片,可以对基板的局部翘曲进行改善,从而,也可以削弱热界面材料层发生分层风险。
并且,由于假芯片位于第一区域内,这样的话,不会因为增加假芯片而增加基板的面积。
在一种可以实现的方式中,在设置散热盖之前,制备方法还包括:在一个或者多个假芯片的远离基板的表面上点粘接胶,以使得在设置散热盖之后,假芯片通过粘接胶与散热盖的中心部分固定连接。
在一种可以实现的方式中,在一个或者多个假芯片的远离基板的表面上点粘接胶,制备方法还包括:沿着基板的外缘的周向点粘接胶,以形成粘接胶层,以使得散热盖的外沿部分通过粘接胶层与基板固定连接,且位于假芯片上的粘接胶和粘接胶层的材料相同;其中,散热盖的外沿部分为散热盖的环绕在多个芯片***的部分。
也就是说,在可以实现的工艺步骤中,可以采用点胶工艺,同时形成粘接胶层和位于假芯片上的粘接胶。
又一方面,本申请还提供了一种芯片封装结构的制备方法,该芯片封装结构的制备方法包括:
在设置有多个芯片的基板的表面上设置牵拉柱,多个芯片在基板上的正投影围成的矩形为第一区域,牵拉柱在基板上的正投影位于第一区域内;
设置散热盖,以使得散热盖覆盖在多个芯片的远离基板一侧的中心部分通过牵拉柱与基板固定连接。
在本申请提供的芯片封装结构的制备方法中,在设置散热盖之前,先要在基板上设置牵拉柱,然后再安装散热盖,如此设计的话,可以通过牵拉柱保障散热盖和基板之间距离的稳定性,不会因为芯片与基板的热膨胀系数失配,导致部分区域距离较大,部分区域距离较小的现象,也就是说通过牵拉柱,会抑制翘曲程度,避免因为较大的 翘曲程度引发一些现象,比如,位于芯片和散热盖之间的TIM层出现分层现象。
在一种可以实现的方式中,在设置有多个芯片的基板的表面上设置牵拉柱,包括:在基板的用于与散热盖的中心部分相对的面上点粘接胶,以形成粘接胶柱,以使得粘接胶柱固定连接在基板和散热盖的中心部分之间,粘接胶柱形成牵拉柱。
也可以这样理解,在该实施例中,是通过在基板上点胶,以形成通过粘接力将基板和散热盖粘接在一起的牵拉柱。该种结构的牵拉柱不仅结构简单,且在工艺上很容易实现。
在一种可以实现的方式中,在基板的用于与散热盖的中心部分相对的面上点粘接胶,制备方法还包括:沿着基板的外缘的周向点粘接胶,以形成粘接胶层,以使得散热盖的外沿部分通过粘接胶层与基板固定连接,且粘接胶柱和粘接胶层的材料相同,散热盖的外沿部分为散热盖的环绕在多个芯片***的部分。
在具体工艺流程中,可以采用点胶工艺,同时在基板的边缘形成用于与散热盖的外沿部分粘接的粘接胶层,和形成牵拉柱的粘接胶柱。
在一种可以实现的方式中,散热盖的中心部分的用于朝向基板的表面上形成有凸出部;在设置散热盖之前,制备方法还包括:在多个芯片的任一个芯片的远离基板的表面上形成热界面材料层;在设置散热盖,包括:安装散热盖,并使得散热盖的凸出部抵接在任一芯片的热界面材料层上。
也就是说,可以通过与散热盖固定连接的凸出部位于热界面材料层上,这样的话,在后续的安装散热器时,可以使得凸出部发生变形,以抵压在热界面材料层上,以防止因为芯片和基板的热膨胀系数失配,而造成热界面材料层出现分层现象,即就是通过凸出部给热界面材料层施加压力,杜绝热界面材料层分层。
在一种可以实现的方式中,在设置散热盖之前,制备方法还包括:在设置多个芯片的基板的表面上设置假芯片。
比如,通过在基板上集成无其他芯片没有任何电连接关系的假芯片,以起到抑制封装体的翘曲程度。
又一方面,本申请还提供一种电子设备,该电子设备包括印制电路板和上述任一实现方式中的芯片封装结构,并且,芯片封装结构设置在印制电路板上,并与印制电路板电连接。
本申请实施例提供的电子设备包括上述任一实现方式中的芯片封装结构,因此本申请实施例提供的电子设备与上述技术方案的芯片封装结构能够解决相同的技术问题,并达到相同的预期效果。
图1为现有技术中一种芯片封装结构的结构示意图;
图2为电子设备中的部分结构示意图;
图3为本申请实施例的芯片封装结构的结构示意图;
图4a为本申请实施例的芯片封装结构中的一种基板的结构示意图;
图4b为本申请实施例的芯片封装结构中的另一种基板的结构示意图;
图4c为本申请实施例的芯片封装结构中的再一种基板的结构示意图;
图5为本申请实施例的芯片封装结构中的散热盖的轴侧图;
图6为图5的A向视图;
图7为本申请实施例的芯片封装结构的结构示意图;
图8为相关技术的一种芯片封装结构发生翘曲的结构示意图;
图9为本申请实施例的芯片封装结构的结构示意图;
图10为本申请实施例的芯片封装结构中的基板、芯片和粘结胶柱的一种位置关系示意图;
图11为本申请实施例的芯片封装结构中的基板、芯片和粘结胶柱的另一种位置关系示意图;
图12为本申请实施例的芯片封装结构中的基板、芯片和粘结胶柱的再一种位置关系示意图;
图13a为未设置粘接胶柱的芯片封装结构的扫描图像;
图13b为设置有粘接胶柱的芯片封装结构的扫描图像;
图14为本申请实施例的芯片封装结构的结构示意图;
图15为本申请实施例的芯片封装结构中的散热盖和基板的连接关系结构示意图;
图16a和图16b为本申请实施例的散热盖上的凸台,和粘接胶柱的一种位置关系示意图;
图17a和图17b为本申请实施例的散热盖上的凸台,和粘接胶柱的再一种位置关系示意图;
图18a和图18b为本申请实施例的散热盖上的凸台,和粘接胶柱的又一种位置关系示意图;
图19为本申请实施例的芯片封装结构的结构示意图;
图20a为本申请实施例的芯片封装结构中的基板、芯片和牵拉柱的一种位置关系示意图;
图20b为本申请实施例的芯片封装结构中的基板、芯片和牵拉柱的再一种位置关系示意图;
图20c为本申请实施例的芯片封装结构中的基板、芯片和牵拉柱的再一种位置关系示意图;
图21为本申请实施例的芯片封装结构的结构示意图;
图22为本申请实施例的芯片封装结构的结构示意图;
图23为本申请实施例的芯片封装结构中的凸出部的结构示意图;
图24为本申请实施例的芯片封装结构中的基板、芯片和凸出部的一种位置关系示意图;
图25为本申请实施例的芯片封装结构中的基板、芯片和凸出部的一种位置关系示意图;
图26为本申请实施例的芯片封装结构中的基板、芯片和凸出部的一种位置关系示意图;
图27为本申请实施例的芯片封装结构的结构示意图;
图28为本申请实施例的芯片封装结构的结构示意图;
图29为本申请实施例的芯片封装结构的结构示意图;
图30为本申请实施例的芯片封装结构中的基板、芯片和假芯片的一种位置关系示意图;
图31为本申请实施例的芯片封装结构的结构示意图;
图32为本申请实施例的芯片封装结构中的基板、芯片和假芯片的一种位置关系示意图;
图33为本申请实施例的芯片封装结构的结构示意图;
图34为本申请实施例的芯片封装结构的结构示意图;
图35为本申请实施例的芯片封装结构的一种制备方法的流程框图;
图36a至图36d为本申请实施例制得芯片封装结构的方法中各步骤完成后相对应的结构示意图;
图37为本申请实施例的芯片封装结构的另一种制备方法的流程框图;
图38a至图38c为本申请实施例制得芯片封装结构的方法中各步骤完成后相对应的结构示意图;
图39为本申请实施例的芯片封装结构的又一种制备方法的流程框图;
图40a至图40d为本申请实施例制得芯片封装结构的方法中各步骤完成后相对应的结构示意图。
附图标记:
100-PCB;
200-电连接结构;
300-芯片封装结构;
400-散热器;
01-基板;
01a-封装基板;
01b-重新布线结构;
01c-转接板;
011-衬底;
012-金属走线;
013-介电层;
014-导电通道;
02-芯片;021-第一芯片;022-第二芯片;023-第三芯片;024-第四芯片;
03-散热盖;031-外沿部分;032-中心部分;
04-热界面材料层;041-第一热界面材料层;042-第二热界面材料层;
05-可控塌陷芯片连接焊点;
06-底胶层;
07-牵拉柱;
071-粘接胶柱;071a-第一粘接胶柱;071b-第二粘接胶柱;
072-凸台;
073-支撑柱;
08-粘接胶层;
09-凸出部;09a-抵压面;
10-假芯片;
11-焊接层。
本申请实施例提供一种电子设备。该电子设备可以包括手机(mobile phone)、平板电脑(pad)、智能穿戴产品(例如,智能手表、智能手环)、虚拟现实(virtual reality,VR)设备、增强现实(augmented reality,AR),还可以是家用电器等设备。本申请实施例对上述电子设备的具体形式不做特殊限制。
如图2所示,上述电子设备可以包括印制电路板(printed circuit board,PCB)100和芯片封装结构300。芯片封装结构300通过电连接结构200与PCB100电连接,从而使得芯片封装结构300能够与PCB100上的其他芯片或者其他电子模块实现信号互连。
另外,再如图2所示的,电子设备还可以包括散热器400,散热器400覆盖芯片封装结构300,以及PCB100上的其他电子模块,并与PCB100固定连接。这里的散热器400作为一种散热结构,可以对芯片封装结构300,以及PCB100上的其他电子模块进行散热降温。另外,散热器400也可以对芯片封装结构300起到物理保护作用。
在可选择的实施方式中,该电连接结构200可以包括多个焊球,例如球栅阵列(ball grid array,BGA),或者包括多个金属柱。
上述芯片封装结构300可以是多个裸片(die)合封后的结构。例如,芯片封装结构300可以是处理器,包括动态随机存取存储器(dynamic random access memory,DRAM)和片上***(system on chip,SOC),也可以包括片上***SOC和模拟芯片等,或者也可以包括模拟芯片和其他数字芯片等。
以下对上述芯片封装结构300的结构进行详细的说明。
图3为本申请实施例提供的一种芯片封装结构300的剖面示意图,该芯片封装结构300包括:多个芯片,这些多个芯片均被集成在基板01上,并且这些多个芯片位于基板01的同一表面上。图3示例性的给出在基板01上集成了第一芯片021和第二芯片022。当然,图3仅是一种示例性结构,也可以在基板01上设置更多的芯片。
还有,本申请涉及集成在基板01上的芯片,可以是一个芯片,也可以是呈三维堆叠的多个芯片。比如,图3中的第一芯片021可以指的是一个芯片,而第二芯片022可以是包含呈三维堆叠的多个芯片,这里的三维堆叠指的是沿与基板01相垂直的方向堆叠。
在一些可选择的实施方式中,见图3所示的,任一个芯片可以通过可控塌陷芯片连接焊点(controlled collapse chip connection,C4)05与基板01电连接,基板01内形成有金属层,该金属层包括布线结构。基板01通过该布线结构在芯片与芯片之间、或者芯片与其他电子器件之间,建立信号通路。也就是说,这里的芯片指的是可以实现电气功能的芯片。
芯片在被设置在基板01上时,可以采用倒装芯片球栅阵列封装(flip-chip ball grid array,FCBGA)技术。简单理解的就是,将芯片的有源面朝向基板01,芯片的无源面 背离基板01,并将芯片的有源面通过BGA电连接结构设置在基板01上。这里的无源面可以理解为芯片的衬底,有源面可以理解为芯片的集成有晶体管等电子器件和金属走线的部分。在另外一些封装结构中,也可以采用引线键合(wire bonding)技术,将芯片设置在基板01上。
本申请涉及的基板01具有多种可以实现的结构。
示例的,基板01可以采用图4a示出的封装基板(substrate)01a,封装基板01a包括衬底011、位于衬底011上表面和下表面的重新布线结构01b。
再示例的,基板01可以是图4b示出的通过重布线工艺制得的重新布线层(redistribution layer,RDL)01b,RDL01b包括多层金属走线012、多层介电层013,每相邻两层金属走线012通过介电层013间隔开。为了使不同层上的金属走线012实现电连接,可以在介电层013内制作导电通道014,以使不同层的金属走线012通过该导电通道014电连接。当采用RDL01b作为基板时,还可以提升基板的柔性,抑制封装体的翘曲程度。
又示例的,基板01可以是图4c示出的转接板(Interposer)01c,转接板01c包括衬底011,集成在衬底011上的重新布线层RDL01b,以及贯通衬底011的导电通道014,导电通道014与重新布线层RDL01b中的金属走线电连接。
为了提升芯片与基板01之间连接的可靠性,如图3,在一种实施方式中,可以采用点胶工艺,在第一芯片021与基板01之间填充底胶层(underfill)06,以及在第二芯片022与基板01之间填充底胶层06。
除此之外,该芯片封装结构300还包括散热盖(Lid)03,散热盖03覆盖在多个芯片的远离基板01的一侧,并与基板01固定连接。
继续见图3所示的,当芯片封装结构300包括散热盖03时,散热盖03通过导热界面材料(thermal interface material,TIM)层与芯片的上表面相连接。比如,在图3中,第一芯片021的上表面通过第一TIM层041与散热盖03连接,第二芯片022的上表面通过第二TIM层042与散热盖03连接。
这样的话,第一芯片021和第二芯片022散发的热量会通过相对应的第一TIM层041和第二TIM层042传导至散热盖03上,通过具有较大热传导面积的散热盖03将热量扩散出去,实现对第一芯片021和第二芯片022的降温,保证这些芯片的正常运行。
在一些实现方式中,上述图3中的第一TIM层041和第二TIM层042可以选择相同的材料,也可以选择不同的材料。
图5和图6给出了散热盖03的其中一种可以实现的结构,且图5示出的是散热盖03的轴侧图,图6示出的是图5的A向视图。一并结合图5和图6,该散热盖03包括外沿部分031和中心部分032。外沿部分031是散热盖03的如图2所示的与基板01固定连接的部分,也就是环绕在多个芯片***的部分,中心部分032是散热盖03的位于多个芯片的远离基板01一侧的部分。
在可以实现的结构中,外沿部分031和中心部分032为一体成型结构。比如,包括外沿部分031和中心部分032的散热盖03可以为一体成型的金属结构件。
在另一些实现结构中,如图7所示的芯片封装结构300中,外沿部分031和中心 部分032为两个彼此独立的结构件,并且,通过连接结构将外沿部分031与中心部分032固定连接,例如,外沿部分031可以通过焊接层11与中心部分032焊接在一起。
当外沿部分031和中心部分032为两个彼此独立的结构件时,这里的外沿部分031也可以被称为加固环(ring)。加固环和中心部分032的材料可以相同,也可以不同。在本申请给出的芯片封装结构300中,由于包括多个芯片,且这些芯片如图3和图7所示的均通过电连接结构集成在基板01上,这样的封装结构可以被称为多芯片模组(multi-chip module,MCM)封装。随着芯片核数和速度的提升,尺寸较大的芯片逐渐也被应用在MCM封装结构中,较大尺寸的芯片与基板01的CTE失配让封装热变形控制变的更加困难,翘曲程度在不断加剧。
图8示出的是相关技术中的一种芯片封装结构300的结构图。明显的,基板01的设置第二芯片022的区域因为热膨胀系数失配形成翘曲区域,进而,使得基板01的设置第一芯片021的区域与散热盖03之间产生较大距离,从而,第一TIM层041出现分层现象,还有,第二芯片022也会随基板01发生翘曲,导致第二TIM层041的边缘部分也出现分层。图8仅是为了示出TIM层出现分层风险的一种示例性结构,不包含出现分层的所有情况。
为了抑制翘曲程度,降低TIM层出现分层的风险,如图3和图7所示的,可以在该芯片封装结构300中设置牵拉柱07。利用牵拉柱07将散热盖03的中心部分032和基板01牵拉在一起,从而可以削弱翘曲程度。
下面结合附图,介绍牵拉柱07的设置位置,具体可实现的结构,以及如何抑制翘曲程度。
图9是本申请给出的一种芯片封装结构300的结构图,在该图中包括了牵拉柱。具体的,牵拉柱包括粘接胶(adhesive,AD)柱071,粘接胶柱071位于散热盖03的中心部分032和基板01之间,并且,粘接胶柱071靠近散热盖03的部分与中心部分032粘接,靠近基板01的部分与基板01粘接。
需要说明的是:本申请涉及的粘接胶柱071的形状不局限为圆柱状结构,位于散热盖03的中心部分032和基板01之间的粘接胶层结构都可以被称为粘接胶柱071结构。
粘接胶柱071抑制翘曲程度的原理可以理解为:见图9所示的,由于粘接胶柱071分别与散热盖03和基板01粘接,从而,粘接胶柱071会给散热盖03的中心部分032朝下的牵拉力f1,同时,粘接胶柱071也会给基板01朝上的牵拉力f2。那么,即使芯片与基板01之间因为CTE失配而要产生翘曲时,比如,如图9所示的Q区域,散热盖03与基板01之间的距离d相比其他区域要变大时,会在牵拉力f1和牵拉力f2的作用下,阻止距离d变大,进而,就会抑制整个封装结构的翘曲程度,当翘曲程度被削弱后,就会降低如图9中的第一TIM层041与散热盖03和第一芯片021之间分层的几率。同理的,也会降低第二TIM层042与散热盖03和第二芯片022之间分层的几率,如此的话,就会降低芯片散热路径中的热阻,提升芯片的散热效果。
继续见图9所示的芯片封装结构300,该芯片封装结构300还包括粘接胶层08,散热盖03的外沿部分031通过粘接胶层08与基板01固定连接。从而,在可以实现的结构中,可以采用相同的材料形成粘接胶柱071和粘接胶层08。比如,粘接胶层的材 料可能是硅树脂(silicone)材料,也可以是环氧树脂(epoxy)材料,本申请对粘接胶层的材料不做特殊限定。
另外,在上述的图9所示的牵拉柱为利用粘接胶制得的粘接胶柱,那么,在选取TIM层的材料时,只需要选取导热系数比较高的材料,比如,可以选择聚合物、金属或者石墨烯等。
粘接胶柱071的设置位置具有多种可以选择的情况。下面给出了几种可以实现的方式。
比如,如图10所示,图10示出的是集成有两个芯片的基板01的俯视图。具体的,两个芯片分别为第一芯片021和第二芯片022,可以将粘接胶柱071设置在第一芯片021和第二芯片022之间。
再比如,如图11所示,图11示出的是集成有四个芯片的基板01的俯视图。四个芯片分别为第一芯片021和第二芯片022,以及第三芯片023和第四芯片024。粘接胶柱071设置在这四个芯片围成区域的中心。
粘接胶柱071的数量具有多种可以选择的情况。
示例的,见图10和图11,均在多个芯片围成区域的中心位置设置了一个粘接胶柱071。
再示例的,如图12所示,图12示出的是集成有两个芯片的基板01的俯视图。具体的,两个芯片分别为第一芯片021和第二芯片022,在第一芯片021和第二芯片022之间设置有多个粘接胶柱071,这些多个粘接胶柱071间隔排布。
如图13a和图13b所示,图13a和图13b均示出的是芯片封装结构300,并且是通过超声波扫描显微镜(scanning acoustic microscope,SAM)从芯片封装结构300上方(即散热盖03上侧)扫描后的图像。其中,图13a示出的芯片封装结构300中没有设置本申请涉及的粘结胶柱071的扫描图像,而图13b示出的芯片封装结构中包含了粘结胶柱701的扫描图像,另外,图13a和图13b均示出了四个芯片02,可以理解为图13b是在图13a所示结构基础上增加粘结胶柱071后的结构图。
一并结合图13a和图13b,可以很容易的看出,在图13a中,当芯片封装结构中未设置粘接胶柱071时,在超声波扫描显微镜SAM的扫描下,每一个芯片02的投影面积明显的,小于图13b中的每一个芯片02的投影面积。由此推出,在图13a所示的芯片封装结构中,可能因为翘曲,使得位于芯片和散热盖之间的TIM层出现分层现象,而导致扫描图像中的芯片投影面积比较小。
所以,通过将图13a和图13b对比,可以得到:若采用本申请的在散热盖03的中心部分032和基板01之间设置粘结胶柱071时,可以降低TIM层出现分层的风险,以提升对芯片的散热效果,也可以提升整个封装体的可靠性。
图14是本申请给出的另一种芯片封装结构300的结构图,在该图中也包括牵拉柱07。具体的,牵拉柱07包括粘接胶柱071,以及凸台072,凸台072形成在散热盖03的中心部分032的朝向基板01的表面上,粘接胶柱071的一端与凸台072粘接,粘接胶柱071的另一端与基板01粘接。
图14所示的牵拉结构和上述图9所示牵拉柱对封装体的抑制翘曲原理是类似的。也就是如图14所示的,由于粘接胶柱071的一端与散热盖03的凸台072粘接,从而 会给散热盖03朝下的牵拉力f1,以及,因为粘接胶柱071的另一端与基板01粘接,会给基板01朝上的牵拉力f2。那么,即使芯片与基板01之间因为CTE失配而要产生翘曲时,散热盖03与基板01之间的距离d相比其他区域要变大时,会在牵拉力f1和牵拉力f2的作用下,阻止距离d变大,进而,就会抑制整个封装结构的翘曲程度。当翘曲程度被削弱后,就会降低TIM层与散热盖03和芯片之间分层的几率。
该实施例中的粘接胶柱071,可以和上述图9中的粘接胶柱071一样,可以选择与粘接胶层08同样的材料。
继续见图14所示的,在一些实现结构中,该凸台072可以和散热盖03的中心部分032为一体成型结构。也可以为:凸台072和散热盖03的中心部分032为相互彼此独立的结构件,凸台072通过连接结构与散热盖03的中心部分032固定连接,比如,通过焊接结构将凸台072与散热盖03连接在一起。
如图15,图15示出了本申请的散热盖03与基板01的装配关系图。其中,凸台072的朝向基板01的面,与基板01之间的间距为d1,散热盖03的外沿部分031(也可以是加固环)的朝向基板01的面,与基板01之间的间距为d2,并且,d1大于或等于d2,比如,图15示出的是d1大于d2。
当d1大于或等于d2时,首先是可以保障位于凸台072与基板01之间的粘接胶柱071,可以对散热盖03和基板01产生相反的牵拉力;其次,还不会因为设置凸台072,而使得散热盖03对芯片产生较大的应力。进而,采用图15所示的散热盖03时,可以杜绝较大应力对芯片造成损坏的风险。
下面结合附图给出了几种不同结构的凸台072和粘接胶柱071。
比如,见图16a和图16b所示的结构,图16a示出的是集成有两个芯片的基板01的俯视图,图16b示出的是具有凸台072的散热盖03的仰视图(也就是图15的B向视图)。见图16a,在基板01上设置有一个粘接胶柱071,对应的,如图16b,可以在散热盖03的中心部分032上设置一个与粘接胶柱071粘接的凸台072。
再比如,见图17a和图17b所示的结构,图17a示出的是集成有两个芯片的基板01的俯视图,图17b示出的是具有凸台072的散热盖03的仰视图。在图17a中,在基板01上设置有多个粘接胶柱071,对应的,如图17b,可以在散热盖03的中心部分032上设置多个凸台072,且多个凸台072与多个粘接胶柱071呈一对一粘接。
又比如,见图18a和图18b所示的结构,图18a示出的是集成有两个芯片的基板01的俯视图,图18b示出的是具有凸台072的散热盖03的仰视图。在图18a中,在基板01上设置有多个粘接胶柱071,对应的,如图18b,可以在散热盖03的中心部分032上设置一个凸台072,且多个粘接胶柱071均与该一个凸台072粘接。
图19是本申请给出的又一种芯片封装结构300的结构图,在该图中也包括牵拉柱07。具体的,牵拉柱07包括第一粘接胶柱071a、第二粘接胶柱071b,以及支撑柱073,支撑柱073位于第一粘接胶柱071a和第二粘接胶柱071b之间,并且,第一粘接胶柱071a与散热盖03的中心部分032粘接,第二粘接胶柱071b与基板01粘接。
在图19所示的结构中,示例的,支撑柱073可以采用玻璃;再示例的,支撑柱073可以采用金属块。当然,也可以选择其他硬度比较大的支撑柱073。
这里的第一粘接胶柱071a和第二粘接胶柱071b可以选择,与粘接胶层08同样的 材料。
基于上述对抑制翘曲程度的牵拉柱07的结构可以看出,是通过牵拉柱07给散热盖03和基板01之间形成牵拉力,以防止因为翘曲,使得散热盖03和基板01的部分区域产生较大的距离。
另外,对于牵拉柱07的设置位置可以理解为:本申请的多个芯片在基板01上的正投影围成的矩形可以被称为第一区域,且牵拉柱07在基板01上的正投影位于该第一区域内。
需要解释的是:本申请涉及的多个芯片在基板01上的正投影围成的矩形,可以这样理解,具体见下述。
比如,见图20a所示的结构,图20a示出的是集成有两个芯片的基板01的俯视图。两个芯片包括第一芯片021和第二芯片022,第一芯片021和第二芯片022在基板01上的正投影具有边界B1、边界B2、边界B3和边界B4,且边界B1、边界B2、边界B3和边界B4围成的区域M为矩形,可以被理解为矩形的区域M为上述的第一区域。
再比如,见图20b所示的结构,图20b示出的也是集成有两个芯片的基板01的俯视图。两个芯片包括第一芯片021和第二芯片022,并且,第一芯片021和第二芯片022在基板01上的正投影具有边界B1、边界B2、边界B3和边界B4,且边界B1、边界B2、边界B3和边界B4围成的区域M为矩形,可以被理解为矩形的区域M为上述的第一区域。
又比如,见图20c所示的结构,图20c示出的集成有三个芯片的基板01的俯视图。三个芯片包括第一芯片021和第二芯片022,以及第三芯片023,并且,第一芯片021、第二芯片022和第三芯片023在基板01上的正投影具有边界B1、边界B2、边界B3和边界B4,且边界B1、边界B2、边界B3和边界B4围成的区域M为矩形,可以被理解为矩形的区域M为上述的第一区域。
再一并结合图20a、图20b和图20c,本申请涉及的牵拉散热盖03的中心部分032和基板01的牵拉柱,在基板01上的正投影位于所述的第一区域内。相比将牵拉柱设置在第一区域的外部,不会对部分芯片产生较大的应力,因而,可以起到保护芯片的作用。
下面结合附图还给出一些可以降低TIM层出现分层风险的芯片封装结构300。
如图21,图21示出了一种芯片封装结构300的结构图,并且,在该芯片封装结构300中包含了凸出部09,凸出部09形成在散热盖03的中心部分032朝向基板01的面上,且抵接在热界面材料层上。比如,在图20中,凸出部09形成有抵压面09a,抵压面09a抵接在热界面材料层上。该凸出部09可以为一个或者多个。
根据图21所示结构,由于在散热盖03的中心部分032上具有可以抵压在TIM层上的凸出部09,那么,在工艺流程中,当将第一芯片021和第二芯片022均集成在基板01上,以及,将散热盖03覆盖在芯片上后,再在散热盖03上安装图2所示的散热器400时,通过散热器400对散热盖03的施压,凸出部09很容易发生变形而使得抵压面抵压在TIM层上,并与TIM层紧密贴合在一起,从而防止TIM层的分层,改善芯片的散热性能。
在该实施例中,凸出部09可以和散热盖03为一体成型结构,也可以是通过焊接 工艺与散热盖03连接在一起。
如图22,图22示出了又一种芯片封装结构300的结构图。在该芯片封装结构300中,也包括了可以抵接在TIM层上的凸出部09,和上述图21所示凸出部09不同的是:凸出部09的抵压面09a为相对芯片倾斜设置的倾斜面。比如,沿着散热盖03的中心部分032至基板01的方向,即就是沿着图22所示的P方向,任一所述抵压面09a自所述多个芯片围成的区域的边缘朝靠近所述多个芯片围成的区域的中心倾斜。
因为在一些芯片封装结构的工艺结构中,当承载有芯片的基板发生翘曲时,芯片的朝向散热盖03的面一般为倾斜的面,进而,将抵压面09a设计为相对芯片倾斜设置的倾斜面,这样的话,可以使得抵压面09a更加贴合在TIM层,以进一步的防止TIM层、芯片和散热盖之间出现间隙。
也可以这样理解,可以在散热盖03的朝向基板01的面上形成如图23所示的带有缓坡的凸出部09,这里的缓坡就是图23中示出的倾斜的抵压面09a。在具体设计时,缓坡的数量和芯片的数量是相等的,比如,当基板01上设置了四个芯片,就可以设计成如图23所示的带有四个缓坡的凸出部09,并且四个缓坡(即就是抵压面09a)沿着凸出部09的周向布置。
在一些可以实现的结构中,抵压面09a可以是倾斜的平面;在另外一些可以实现的结构中,抵压面09a也可以是倾斜的曲面。若抵压面091a为曲面时,对于曲面的曲率可以依据芯片翘曲程度设计。
即就是,对于抵压面09a的面积大小或者倾斜的角度大小,本申请不做特殊限定,可以根据,TIM层容易分层的位置来确定。
还有,凸出部09的布设位置也会有多种情况。下面给出凸出部09可能存在的几种位置。
比如,见图24所示的结构,图24示出的是集成有两个芯片的基板01的俯视图,且图24中体现了凸出部09与两个芯片的位置关系。两个芯片包括第一芯片021和第二芯片022,凸出部09在基板01上的正投影位于第一区域内,该第一区域在上述已经介绍,在此不再赘述,并且,凸出部09靠近第一区域的中心位置。也就是说,通过一个形成在散热盖上的结构,就可以同时作用在多个芯片上,除此之外,凸出部09对不同芯片施加的抵压力基本保持一致,这样的话,不会出现整个封装结构的局部出现应力较大的问题。
再比如,见图25所示的结构,图25示出的是集成有四个芯片的基板01的俯视图,且图25中体现了凸出部09与四个芯片的位置关系。四个芯片包括第一芯片021和第二芯片022,以及,第三芯片023和第四芯片024,和上述图24一样,凸出部09在基板01上的正投影位于第一区域内,并且,凸出部09靠近第一区域的中心位置。
又比如,见图26所示的结构,图26示出的是集成有四个芯片的基板01的俯视图,且图26中体现了凸出部09与四个芯片的位置关系。图25相同的是,在基板01上也集成了第一芯片021和第二芯片022,以及,第三芯片023和第四芯片024,和上述图25不同在处在于,凸出部09靠近第一区域的边缘设置。
上述结合附图分别介绍了采用两种不同结构,来改善TIM层分层现象的实现方式。其中,一种是以上述图9和图14,以及图19为例的,通过设置牵拉柱07,给散热盖 03和基板01施加牵拉力,以削弱翘曲程度,从而改善TIM层分层;另一种是以图21和图22为例的,通过在散热盖03和TIM层之间设置凸出部09,通过凸出部09的变形,改善TIM层分层。
当然,在一些可以选择的实现方式中,如图27所示的,可以将上述涉及的凸出部09和粘接胶柱071集成在一个芯片封装结构300中,具体的,凸出部09形成在散热盖03的中心部分032朝向基板01的表面上,并且凸出部09上形成有与TIM层抵压的抵压面09a,粘接胶柱071设置在凸出部09和基板01之间,即就是粘接胶柱071的一端与凸出部09粘接,粘接胶柱071的另一端与基板01粘接。
另外一些可以实现的方式中,图27中的凸出部09可以位于散热盖03的一位置处,而粘接胶柱071与散热盖03的粘接位置不在凸出部09上,而在散热盖03的另一位置处。
图28还给出了一种芯片封装结构300,在该封装结构中,集成了上述的牵拉柱和凸出部。具体的,可以在散热盖02的中心部分032的朝向基板01的面上形成凸出部09,以及在基板01上设置有支撑柱073,并且支撑柱073通过粘接胶柱071与凸出部09粘接在一起。
针对上述的通过牵拉柱07改善TIM层分层的可以实现的多种实施例,可以和上述的通过凸出部09改善TIM层分层的可以实现的多种实施例进行任意组合。图27和图28仅给出了其中两种可以结合的实现结构。本申请不局限于图27和图28的实现方式,其他组合结构也在本申请的保护范围之内。
除上述给出的几种改善TIM层分层的结构之外,本申请还给出了一些可以抑制翘曲程度,削弱TIM层分层的可实现方式,具体见下述。
如图29和图31,图29和图31示出的芯片封装结构300中,除包括集成在基板01上的多个可以信号互通的芯片以外,比如图29所示的,包括能够实现信号互联的第一芯片021和第二芯片022,在基板01上还集成有假芯片(dummy die)10,且假芯片10和信号互联的多个芯片集成在基板01的同一表面上,
需要解释的是:本申请涉及的假芯片10是一种与其他芯片没有信号互联的芯片。
在图29所示的芯片封装结构300中,通过增加dummy die的方式,利用die与基板01之间的CTE差,进行局部翘曲调整,可以减少整个封装体的翘曲突变,进而,可以消除TIM分层的产生。
假芯片10在基板01上所处的位置为:多个芯片在基板01上的正投影围成的矩形为第一区域,假芯片10在基板01上的正投影位于第一区域内,即此处的对于第一区域的定义和上述对第一区域的定义是相同的。
也可以这样理解该第一区域,如图30所示的结构,图30示出的是集成有四个芯片的基板01的俯视图,且图30中体现了假芯片10与四个芯片的位置关系。具体的,在基板01上设置有第一芯片021和第二芯片022,以及第三芯片023和第四芯片024,第一芯片021和第二芯片022,以及第三芯片023和第四芯片024在基板01上的正投影具有边界B1、边界B2、边界B3和边界B4,且边界B1、边界B2、边界B3和边界B4围成的区域M为矩形,可以被理解为上述的第一区域,假芯片10在基板01上的正投影在区域M内。
再如图32所示的结构,图32示出的是集成有两个芯片的基板01的俯视图,且图32中体现了两个假芯片10与两个芯片的位置关系。具体的,在基板01上设置有第一芯片021和第二芯片022,并且,第一芯片021和第二芯片022在基板01上的正投影具有边界B1、边界B2、边界B3和边界B4,且边界B1、边界B2、边界B3和边界B4围成的区域M为矩形,两个假芯片10在基板01上的正投影均在区域M内。
这样设计假芯片10,相比将假芯片10设置在区域M的外部,不会增加基板01的面积,进而,就不增加整个封装结构的尺寸。
另外,本申请对假芯片10的数量也不做限定,示例的,在图30所示的结构中,可以在基板01上设置一个假芯片10;再示例的,见图32,可以在基板01上设置至少两个假芯片10。
当采用图30所示的结构中,具体的是:第一芯片021、第二芯片022、第三芯片023和第四芯片023围成矩形结构,且第一芯片021、第二芯片022、第三芯片023和第四芯片024靠近矩形结构的角落设置,一个假芯片10靠近矩形结构的中心设置。
当采用图32所示的结构中,第一芯片021、第二芯片022、两个假芯片10围成矩形结构,且第一芯片021和第二芯片022设置在矩形结构的第一对角线A1上,两个假芯片10设置在矩形结构的第二对角线A2上,第一对角线A1和第二对角线A2相交。
在一些可以选择的实现结构中,如图30和图32所示的,假芯片10的面积可以小于芯片的面积,这样的话,采用较小面积的假芯片可以充分利用芯片与芯片之间的较小的闲置空间。
为了抑制封装体的翘曲程度,可以将假芯片10和上述的凸出部09组合,集成在一个芯片封装结构300中。比如,图33所示的芯片封装结构300中,包含了假芯片10,和形成在散热盖03上的凸出部09,并采用粘接胶柱071将假芯片10与凸出部09粘接在一起。
或者,在另外一些实现方式中,如图34所示的芯片封装结构300中,可以理解为图34是图32的剖面图,即就是可以不设置凸出部09,而是直接将假芯片10通过粘接胶柱071与散热盖粘接在一起。
又或者,在另外一些实现方式中,也可以在一个芯片封装结构300中,不仅设置假芯片10,还可以设置牵拉柱07和凸出部09。
针对通过设置假芯片10来改善TIM分层的可实现结构,可以和上述涉及的通过设置牵拉柱07和设置凸出部09改善TIM分层的可实现结构,进行组合,对于通过不同组合方式得到的芯片封装结构均在本申请保护的范围之内。
本申请实施例还提供了一种芯片封装结构300的制备方法,该制备方法包括:
在设置有多个芯片的基板的表面上设置牵拉柱,多个芯片在基板上的正投影围成的矩形为第一区域,牵拉柱在基板上的正投影位于第一区域内。
设置散热盖,以使得散热盖覆盖在多个芯片的远离基板一侧的中心部分通过牵拉柱与基板固定连接。
在该制备方法中,通过设置牵拉柱,使得牵拉柱给散热盖的中心部分,和基板分别产生牵拉力,那么,当集成有多个芯片的基板在温度变化的过程中,通过该牵拉力,可以使得散热盖和基板之间的间距不会突变,从而不会出现较大的翘曲现象,这样的 话,也不会衍生出一些影响芯片性能的问题,比如,杜绝位于芯片和散热盖之间的TIM分层。
下面结合图35所示的工艺流程图,和图36a至图36d的工艺结构图,具体介绍芯片封装结构300的一种可实现的制备方法。
步骤S11:结合图36a,在基板01上设置多个芯片02。
步骤S12:结合图36b,沿着基板01的边缘的周向点胶,以及,在基板01的与用于与散热盖03的中心部分相对的位置处点胶。
当在基板01的用于与散热盖的中心部分相对的位置处点胶时,可以在靠近多个芯片在基板的正投影的第一区域的中心位置处点粘接胶。
步骤S13:结合图36c,在芯片02的远离基板01的表面上形成TIM层04。
步骤S14:结合图36d,安装散热盖03。
待图36b在基板01上的粘接胶固化后,就可以在基板01上形成用于与散热盖的外沿部分粘接的粘接胶层08,和用于与散热盖的中心部分粘接的粘接胶柱071。
在执行上述步骤S14时,散热盖03的朝向基板01的面上还具有凸出部,那么,当把散热盖03覆盖在多个芯片02上后,凸出部的抵压面会位于芯片的TIM层上,那么,当在该芯片封装结构的散热盖上安装散热器时,凸出部会在散热器的作用力下发生变形,以抵压在TIM层上。
另外,在执行步骤S11时,也可以在基板01上集成至少一个假芯片。
本申请实施例还提供了另一种芯片封装结构300的制备方法,该制备方法包括:
在基板的同一表面上设置多个芯片,且多个芯片中的任一个芯片均通过电连接结构设置在基板上;
在多个芯片的任一个芯片的远离基板的表面上形成热界面材料层;
设置散热盖,以使得散热盖的中心部分上的一个或者多个凸出部抵接在多个芯片中至少一个芯片的热界面材料层上;其中,散热盖的中心部分为散热盖的覆盖在多个芯片的远离基板一侧的部分,一个或者多个凸出部设置在散热盖的中心部分的朝向基板的表面上。
下面结合图37所示的工艺流程图,和图38a至图38c的工艺结构图,具体介绍芯片封装结构300的一种可实现的制备方法。
步骤S21:结合图38a,在基板01上设置多个芯片02。
步骤S22:结合图38b,在任一个芯片02的远离基板01的表面形成热界面材料层04。
步骤S23:结合图38c,安装散热盖03;其中,散热盖03的中心部分032的朝向基板的面上具有凸出部09,凸出部09抵接在多个芯片中至少一个芯片的热界面材料层04上。
在一些可以实现的工艺步骤中,在执行步骤S21时,也可以在基板01上集成至少一个假芯片。也就是说,通过集成在基板01上的假芯片10抑制封装体的翘曲程度。
并且,也可以在假芯片10的上表面形成粘接胶层,以通过粘接胶层与凸出部牵拉在一起。
另外,在一些工艺中,在执行步骤S24的安装散热盖03之前,还可以在基板01 的朝向凸出部的位置处点胶,以使得凸出部通过固化的粘接胶与基板牵拉在一起。
还有,在基板01的朝向凸出部09的位置处点胶时,也可以沿着基板01的外缘的周向点同样材料的粘接胶,以使得散热盖的外沿部分通过外缘处的粘接胶层08与基板01固定连接。
本申请实施例还提供了另一种芯片封装结构300的制备方法,该制备方法包括:
在基板的同一表面上设置多个芯片,且多个芯片中的任一个芯片均通过电连接结构设置在基板上;
在设置多个芯片的基板的表面上设置一个或者多个假芯片,且一个或多个假芯片在基板上的正投影位于第一区域内,多个芯片在基板上的正投影围成的矩形为第一区域;
设置散热盖,以使得散热盖的中心部分覆盖在多个芯片的远离基板一侧。
下面结合图39所示的工艺流程图,和图40a至图40c的工艺结构图,具体介绍芯片封装结构300的一种可实现的制备方法。
步骤S31:结合图40a,在基板01上设置多个芯片02和至少一个假芯片10。
步骤S32:结合图40b,在任一个芯片02的远离基板01的表面形成热界面材料层04。
步骤S33:结合图40c,在假芯片10的远离基板01的表面点粘接胶。
在一种可以实现的工艺中,步骤S32和步骤S33,可以同步执行,也可以分两步先后执行。
步骤S34:结合图40d,安装散热盖03,以使得散热盖03的中心部分032覆盖在多个芯片和一个或者多个假芯片的远离基板01一侧。
这样的话,就使得基板01通过假芯片10和粘接胶与散热盖03牵拉在一起。抑制整个封装体的翘曲程度。
在一些工艺手段中,在假芯片10上点胶时,也可以沿着基板01的外缘的周向点同样材料的粘接胶,以使得散热盖的外沿部分通过外缘处的粘接胶层08与基板01固定连接。在一种结构中,假芯片10上的粘接胶的材料,可以与基板01外缘的粘接胶层08的材料相同。
在本说明书的描述中,具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述,仅为本申请的具体实施方式,但本申请的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本申请揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本申请的保护范围之内。因此,本申请的保护范围应以所述权利要求的保护范围为准。
Claims (35)
- 一种芯片封装结构,其特征在于,包括:基板;多个芯片,位于所述基板的同一表面上,且所述多个芯片中的任一个芯片均通过电连接结构设置在所述基板上;散热盖,所述散热盖包括覆盖在所述多个芯片的远离所述基板一侧的中心部分,和环绕在所述多个芯片***的且与所述基板固定连接的外沿部分;热界面材料层,形成在所述多个芯片中的任一个芯片的远离所述基板的表面与所述散热盖的所述中心部分之间;其中,所述散热盖的所述中心部分的朝向所述基板的表面具有一个或多个凸出部,且所述一个或多个凸出部抵接在所述多个芯片中至少一个芯片的所述热界面材料层上。
- 根据权利要求1所述的芯片封装结构,其特征在于,所述凸出部具有多个抵压面,所述多个抵压面一对一地抵接在多个所述热界面材料层上。
- 根据权利要求2所述的芯片封装结构,其特征在于,所述凸出部靠近第一区域的中心设置,所述多个抵压面沿着所述凸出部的周向布置,所述多个芯片在所述基板上的正投影围成的矩形为所述第一区域;沿着所述散热盖的所述中心部分至所述基板的方向,任一所述抵压面自所述第一区域的边缘朝靠近所述第一区域的中心倾斜。
- 根据权利要求1-3中任一项所述的芯片封装结构,其特征在于,所述芯片封装结构还包括:粘接胶柱,位于所述凸出部和所述基板之间,且所述粘接胶柱的一端与所述凸出部粘接,另一端与所述基板粘接。
- 根据权利要求1-3中任一项所述的芯片封装结构,其特征在于,所述芯片封装结构还包括:一个或多个假芯片,所述一个或多个假芯片和所述多个芯片位于所述基板的同一表面上;所述一个或多个假芯片在所述基板上的正投影位于第一区域内,所述多个芯片在所述基板上的正投影围成的矩形为所述第一区域。
- 根据权利要求5所述的芯片封装结构,其特征在于,所述假芯片位于所述凸出部和所述基板之间,并通过粘接胶层与所述凸出部粘接。
- 根据权利要求1-6中任一项所述的芯片封装结构,其特征在于,所述散热盖的所述外沿部分与所述散热盖的所述中心部分为一体成型结构。
- 根据权利要求1-6中任一项所述的芯片封装结构,其特征在于,所述散热盖的所述外沿部分通过连接结构与所述散热盖的所述中心部分固定连接。
- 一种芯片封装结构,其特征在于,包括:基板;多个芯片,位于所述基板的同一表面上,且所述多个芯片中的任一个芯片均通过电连接结构设置在所述基板上;至少一个假芯片,所述至少一个假芯片和所述多个芯片位于所述基板的同一表面 上;散热盖,所述散热盖包括覆盖在所述多个芯片和所述至少一个假芯片的远离所述基板一侧的中心部分,和环绕在所述多个芯片和所述至少一个假芯片***的,且与所述基板固定连接的外沿部分;其中,所述至少一个假芯片在所述基板上的正投影位于第一区域内,所述多个芯片在所述基板上的正投影围成的矩形为所述第一区域。
- 根据权利要求9所述的芯片封装结构,其特征在于,任一个所述假芯片的面积小于所述芯片的面积。
- 根据权利要求9或10所述的芯片封装结构,其特征在于,任一个所述假芯片的远离所述基板的表面通过粘接胶层粘接在所述中心部分上。
- 根据权利要求9-11中任一项所述的芯片封装结构,其特征在于,所述多个芯片包括第一芯片、第二芯片、第三芯片和第四芯片;所述至少一个假芯片为一个假芯片;第一芯片、所述第二芯片、所述第三芯片和所述第四芯片靠近所述第一区域的角落设置;所述一个假芯片靠近所述第一区域的中心设置。
- 根据权利要求9-11中任一项所述的芯片封装结构,其特征在于,所述多个芯片包括第一芯片和第二芯片;所述至少一个假芯片包括第一假芯片和第二假芯片;第一芯片和所述第二芯片位于所述矩形的第一对角线上,所述第一假芯片和所述第二假芯片位于所述矩形的第二对角线上,且所述第一对角线和所述第二对角线相交。
- 一种芯片封装结构,其特征在于,包括:基板;多个芯片,位于所述基板的同一表面上,且所述多个芯片中的任一个芯片均通过电连接结构设置在所述基板上;散热盖,所述散热盖包括覆盖在所述多个芯片的远离所述基板一侧的中心部分,和环绕在所述多个芯片***的且与所述基板固定连接的外沿部分;牵拉柱,位于所述散热盖的所述中心部分和所述基板之间;所述牵拉柱在所述基板上的正投影位于第一区域内,所述多个芯片在所述基板上的正投影围成的矩形为所述第一区域,所述牵拉柱分别与所述散热盖的所述中心部分和所述基板固定连接。
- 根据权利要求14所述的芯片封装结构,其特征在于,所述牵拉柱包括:粘接胶柱,所述粘接胶柱的一端与所述散热盖的所述中心部分粘接,另一端与所述基板粘接。
- 根据权利要求14所述的芯片封装结构,其特征在于,所述牵拉柱包括:凸台,所述凸台形成在所述散热盖的所述中心部分的朝向所述基板的面上;粘接胶柱,所述粘接胶柱的一端与所述凸台粘接,另一端与所述基板粘接。
- 根据权利要求16所述的芯片封装结构,其特征在于,所述凸台的朝向所述基板的面,与所述基板之间的间距为d1;所述外沿部分的朝向所述基板的面,与所述基板之间的间距为d2;其中,d1大于或等于d2。
- 根据权利要求14所述的芯片封装结构,其特征在于,所述芯片封装结构还包括:至少一个假芯片,所述至少一个假芯片和所述多个芯片位于所述基板的同一表面上,且所述至少一个假芯片在所述基板上的正投影位于所述第一区域内。
- 根据权利要求18所述的芯片封装结构,其特征在于,所述芯片封装结构还包括:粘接胶柱,所述粘接胶柱的一端与所述散热盖的所述中心部分粘接,另一端与所述假芯片粘接。
- 根据权利要求14所述的芯片封装结构,其特征在于,所述牵拉柱包括:粘接胶柱,所述粘接胶柱包括第一粘接胶柱和第二粘接胶柱;支撑柱;所述支撑柱的一端通过所述第一粘接胶柱与所述散热盖的所述中心部分粘接,所述支撑柱的另一端通过所述第二粘接胶柱与所述基板粘接。
- 根据权利要求15-17、19或20中任一项所述的芯片封装结构,其特征在于,所述芯片封装结构还包括:粘接胶层,所述外沿部分通过环绕在所述多个芯片***的所述粘接胶层,与所述基板固定连接;且所述粘接胶柱和所述粘接胶层的材料相同。
- 一种芯片封装结构的制备方法,其特征在于,包括:在基板的同一表面上设置多个芯片,且所述多个芯片中的任一个芯片均通过电连接结构设置在所述基板上;在所述多个芯片的任一个芯片的远离所述基板的表面上形成热界面材料层;设置散热盖,以使得所述散热盖的中心部分上的一个或者多个凸出部抵接在所述多个芯片中至少一个芯片的所述热界面材料层上;其中,所述散热盖的中心部分为所述散热盖的覆盖在所述多个芯片的远离所述基板一侧的部分,所述一个或者多个凸出部设置在所述散热盖的所述中心部分的朝向所述基板的表面上。
- 根据权利要求22所述的芯片封装结构的制备方法,其特征在于,在所述设置散热盖之前,所述制备方法还包括:在所述基板的用于与所述散热盖的所述中心部分相对的面上点粘接胶,以形成粘接胶柱,以使得在设置所述散热盖之后,所述粘接胶柱固定连接在所述基板和所述凸出部之间。
- 根据权利要求23所述的芯片封装结构的制备方法,其特征在于,在所述基板的用于与所述散热盖的所述中心部分相对的面上点粘接胶,所述制备方法还包括:沿着所述基板的外缘的周向点粘接胶,以形成粘接胶层,以使得所述散热盖的外沿部分通过所述粘接胶层与所述基板固定连接,且所述粘接胶柱和所述粘接胶层的材料相同;其中,所述散热盖的所述外沿部分为所述散热盖的环绕在所述多个芯片***的部分。
- 根据权利要求22所述的芯片封装结构的制备方法,其特征在于,在所述设置散热盖之前,所述制备方法还包括:在设置所述多个芯片的所述基板的表面上设置一个或者多个假芯片,且所述一个或多个假芯片在所述基板上的正投影位于第一区域内,所述多个芯片在所述基板上的正投影围成的矩形为所述第一区域。
- 根据权利要求25所述的芯片封装结构的制备方法,其特征在于,在设置所述一个或者多个假芯片之后,在设置所述散热盖之前,所述制备方法还包括:在所述一个或者多个假芯片的远离所述基板的表面上点粘接胶,以使得在设置所述散热盖之后,所述假芯片通过所述粘接胶与所述凸出部固定连接。
- 一种芯片封装结构的制备方法,其特征在于,包括:在基板的同一表面上设置多个芯片,且所述多个芯片中的任一个芯片均通过电连接结构设置在所述基板上;在设置所述多个芯片的所述基板的表面上设置一个或者多个假芯片,且所述一个或多个假芯片在所述基板上的正投影位于第一区域内,所述多个芯片在所述基板上的正投影围成的矩形为所述第一区域;设置散热盖,以使得所述散热盖的中心部分覆盖在所述多个芯片和所述一个或者多个假芯片的远离所述基板一侧。
- 根据权利要求27所述的芯片封装结构的制备方法,其特征在于,在所述设置散热盖之前,所述制备方法还包括:在所述一个或者多个假芯片的远离所述基板的表面上点粘接胶,以使得在设置所述散热盖之后,所述假芯片通过所述粘接胶与所述散热盖的所述中心部分固定连接。
- 根据权利要求28所述的芯片封装结构的制备方法,其特征在于,在所述一个或者多个假芯片的远离所述基板的表面上点粘接胶,所述制备方法还包括:沿着所述基板的外缘的周向点粘接胶,以形成粘接胶层,以使得所述散热盖的外沿部分通过所述粘接胶层与所述基板固定连接,且位于所述假芯片上的所述粘接胶和所述粘接胶层的材料相同;其中,所述散热盖的所述外沿部分为所述散热盖的环绕在所述多个芯片***的部分。
- 一种芯片封装结构的制备方法,其特征在于,包括:在设置有多个芯片的基板的表面上设置牵拉柱,所述牵拉柱在所述基板上的正投影位于第一区域内,所述多个芯片在所述基板上的正投影围成的矩形为所述第一区域基板;设置散热盖,以使得所述散热盖覆盖在所述多个芯片的远离所述基板一侧的中心部分通过所述牵拉柱与所述基板固定连接。
- 根据权利要求30所述的芯片封装结构的制备方法,其特征在于,所述在设置有多个芯片的基板的表面上设置牵拉柱,包括:在所述基板的用于与所述散热盖的所述中心部分相对的面上点粘接胶,以形成粘接胶柱,以使得所述粘接胶柱固定连接在所述基板和所述散热盖的所述中心部分之间,所述粘接胶柱形成所述牵拉柱。
- 根据权利要求31所述的芯片封装结构的制备方法,其特征在于,在所述基板的用于与所述散热盖的所述中心部分相对的面上点粘接胶,所述制备方法还包括:沿着所述基板的外缘的周向点粘接胶,以形成粘接胶层,以使得所述散热盖的外沿部分通过所述粘接胶层与所述基板固定连接,且所述粘接胶柱和所述粘接胶层的材料相同;其中,所述散热盖的所述外沿部分为所述散热盖的环绕在所述多个芯片***的部分。
- 根据权利要求30-32中任一项所述的芯片封装结构的制备方法,其特征在于,所述散热盖的所述中心部分的用于朝向所述基板的表面上形成有凸出部;在所述设置散热盖之前,所述制备方法还包括:在所述多个芯片的任一个芯片的远离所述基板的表面上形成热界面材料层;在所述设置散热盖,包括:安装所述散热盖,并使得所述散热盖的所述凸出部抵接在任一所述芯片的所述热界面材料层上。
- 根据权利要求30-23中任一项所述的芯片封装结构的制备方法,其特征在于,在所述设置散热盖之前,所述制备方法还包括:在设置所述多个芯片的所述基板的表面上设置至少一个假芯片,且所述至少一个假芯片在所述基板上的正投影位于所述第一区域内。
- 一种电子设备,其特征在于,包括:印制电路板;如权利要求1~21中任一项所述的芯片封装结构,或者如权利要求22~34中任一项所述的芯片封装结构的制备方法制得的芯片封装结构;其中,所述芯片封装结构设置在所述印制电路板上。
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