JP6227010B2 - 撮像装置、撮像システム、および、撮像装置の製造方法 - Google Patents
撮像装置、撮像システム、および、撮像装置の製造方法 Download PDFInfo
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Description
1 N型半導体領域(光電変換部)
2 P型半導体領域(光電変換部)
9 ゲート領域
10 チャネル領域
17 第1のマスク
18 第2のマスク
209 第1の開口
210 第2の開口
Claims (12)
- 半導体基板に配された接合型電界効果トランジスタをそれぞれが含む複数の画素を備える撮像装置の製造方法であって、
第1の開口を規定する第1のマスクを用いて前記半導体基板に不純物を導入することにより、前記接合型電界効果トランジスタのゲート領域を形成する工程と、
第2の開口を規定する第2のマスクを用いて前記半導体基板に不純物を導入することにより、前記接合型電界効果トランジスタのチャネル領域を形成する工程と、を有し、
前記第2の開口は、前記チャネル領域のソース側の部分に対応するソース側部分と前記チャネル領域のドレイン側の部分に対応するドレイン側部分とを含み、
前記半導体基板の表面と平行な面への前記第1の開口の正射影と、前記面への前記第2の開口の正射影とが交差し、
前記面への前記ソース側部分の正射影、および、前記面への前記ドレイン側部分の正射影が、それぞれ、前記第1のマスクの前記面への正射影と重なり、
前記ゲート領域は、互いに異なる深さに形成される表面ゲート領域と埋め込みゲート領域とを含み、
前記ゲート領域を形成する工程は、それぞれが前記第1のマスクを用い、かつ、イオン注入エネルギーが互いに異なる複数のイオン注入工程を含み、
前記表面ゲート領域と前記埋め込みゲート領域との中間の深さに前記チャネル領域を形成し、
前記第1の開口は、前記第1のマスクによって分割された複数の開口を含み、
前記面への前記複数の開口の正射影のそれぞれが、前記第2の開口の正射影と交差し、
前記ソース側部分の正射影は、前記第1のマスクのうち、前記複数の開口の間にある部分の前記面への正射影と重なり、
前記複数の開口に対応して形成される複数の前記埋め込みゲート領域の間の空乏層によって、前記チャネル領域の前記ソース側の部分と前記埋め込みゲート領域の下の半導体領域との間にポテンシャルバリアが形成されるように、前記複数の開口の間隔が定められる、
ことを特徴とする撮像装置の製造方法。 - 前記表面ゲート領域と前記埋め込みゲート領域とが互いに電気的に接続される深さに形成されるように、前記イオン注入エネルギーを選択する、
ことを特徴とする請求項1に記載の撮像装置の製造方法。 - 前記表面ゲート領域と前記埋め込みゲート領域とを電気的に接続する第1の半導体領域を形成する工程をさらに有する、
ことを特徴とする請求項1に記載の撮像装置の製造方法。 - 前記ゲート領域を形成する工程において、前記複数の開口に対応する複数のゲート領域を形成し、
前記複数のゲート領域を互いに電気的に接続する第2の半導体領域を形成する工程をさらに有する、
ことを特徴とする請求項1乃至請求項3のいずれか一項に記載の撮像装置の製造方法。 - 前記第2の半導体領域を形成する工程は、第3の開口を規定する第3のマスクを用いて行われ、
前記第1の開口の正射影が、前記面への前記第3の開口の正射影と部分的に重なり、
前記第2の開口の正射影の全体が、前記第3のマスクの前記面への正射影と重なる、
ことを特徴とする請求項4に記載の撮像装置の製造方法。 - 前記チャネル領域のソース側の部分と電気的に接続されるソース領域を形成する工程をさらに含む、
ことを特徴とする請求項1乃至請求項5のいずれか一項に記載の撮像装置の製造方法。 - 前記半導体基板の表面と平行な面への前記第1の開口の正射影と、前記面への前記第2の開口の正射影との重なった部分によって、前記接合型電界効果トランジスタのチャネル長およびチャネル幅を規定する、
ことを特徴とする請求項1乃至請求項6のいずれか一項に記載の撮像装置の製造方法。 - 前記第1の開口の正射影の外縁は互いに平行な2つの線分を含み、
前記第2の開口の正射影の外縁は互いに平行な2つの線分を含む、
ことを特徴とする請求項1乃至請求項7のいずれか一項に記載の撮像装置の製造方法。 - 半導体基板に配された接合型電界効果トランジスタをそれぞれが含む複数の画素を備える撮像装置の形成方法であって、
前記半導体基板に前記接合型電界効果トランジスタのゲート領域を形成する工程と、
前記半導体基板に前記接合型電界効果トランジスタのチャネル領域を形成する工程と、を有し、
前記半導体基板の表面と平行な面への、前記ゲート領域を形成する工程において不純物が導入される第1領域の正射影と、前記面への、前記チャネル領域を形成する工程において不純物が導入される第2領域の正射影とが交差し、
前記面において、前記第2領域の正射影のソース側の部分、および、ドレイン側の部分が、それぞれ、前記第1領域の正射影から突出し、
前記ゲート領域は、互いに異なる深さに形成される表面ゲート領域と埋め込みゲート領域とを含み、
前記表面ゲート領域と前記埋め込みゲート領域との中間の深さに前記チャネル領域を形成し、
前記第1領域の正射影は、間隔をおいて配された複数の部分を含み、
前記第2領域の正射影の前記ソース側部分は、前記複数の部分の間にあり、
前記複数の部分に対応して形成される複数の前記埋め込みゲート領域の間の空乏層によって、前記チャネル領域の前記ソース側の部分と前記埋め込みゲート領域の下の半導体領域との間にポテンシャルバリアが形成されるように、前記複数の部分の間隔が定められる、
ことを特徴とする撮像装置の形成方法。 - 半導体基板に配された接合型電界効果トランジスタをそれぞれが含む複数の画素を備える撮像装置であって、
前記接合型電界効果トランジスタは、それぞれ異なる深さに配された、表面ゲート領域と埋め込みゲート領域とチャネル領域とを含み、
前記チャネル領域は、前記表面ゲート領域と前記埋め込みゲート領域との中間の深さに配され、
前記半導体基板の表面と平行な面への前記表面ゲート領域の正射影、および、前記埋め込みゲート領域の正射影が、それぞれ、前記面への前記チャネル領域の正射影と交差し、
前記表面ゲート領域および前記埋め込みゲート領域のそれぞれが、前記接合型電界効果トランジスタのソース領域を挟むように配され、かつ、互いに電気的に接続された複数の領域を含み、
前記面への前記複数の領域の正射影のそれぞれが、前記チャネル領域の正射影と交差し、
前記埋め込みゲート領域の前記複数の領域の間の空乏層によって、前記ソース領域と前記埋め込みゲート領域の下の半導体領域との間にポテンシャルバリアが形成される、
ことを特徴とする撮像装置。 - 請求項10に記載の撮像装置と、
被写体の光学像を前記撮像装置に結像させるレンズと、
を備えた撮像システム。 - 請求項10に記載の撮像装置と、
前記撮像装置から出力される信号を処理する信号処理装置と、
を備えた撮像システム。
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JPS5941871A (ja) * | 1982-08-31 | 1984-03-08 | Matsushita Electronics Corp | 接合型電界効果半導体装置 |
JPS59108461A (ja) * | 1982-12-14 | 1984-06-22 | Olympus Optical Co Ltd | 固体撮像装置 |
US5089862A (en) * | 1986-05-12 | 1992-02-18 | Warner Jr Raymond M | Monocrystalline three-dimensional integrated circuit |
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JP2005252083A (ja) * | 2004-03-05 | 2005-09-15 | Nikon Corp | 接合型電界効果トランジスタ、及び固体撮像装置 |
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JP2006351729A (ja) * | 2005-06-14 | 2006-12-28 | Canon Inc | 接合形電界効果トランジスタ及びその製造方法並びに固体撮像装置 |
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CN105830219B (zh) | 2019-01-01 |
US9577004B2 (en) | 2017-02-21 |
US20150179688A1 (en) | 2015-06-25 |
KR101866673B1 (ko) | 2018-06-11 |
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