JP6210619B2 - はんだ回路基板の製造方法、はんだ回路基板及び電子部品の実装方法 - Google Patents
はんだ回路基板の製造方法、はんだ回路基板及び電子部品の実装方法 Download PDFInfo
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- JP6210619B2 JP6210619B2 JP2013081208A JP2013081208A JP6210619B2 JP 6210619 B2 JP6210619 B2 JP 6210619B2 JP 2013081208 A JP2013081208 A JP 2013081208A JP 2013081208 A JP2013081208 A JP 2013081208A JP 6210619 B2 JP6210619 B2 JP 6210619B2
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3494—Heating methods for reflowing of solder
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
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Description
また、はんだ合金は溶融時に表面張力の影響で金属回路の幅が広い部分に移動するため、その部分のはんだ層厚が大きくなる。これにより、はんだ回路基板のはんだ層厚にばらつきが生ずると、はんだ層の形成工程後に行う電子部品の接合工程において、電子部品のリード端子と回路パターンとの接合強度にばらつきが生じる等の悪影響がある。
また、通常図1(g)に示す電子部品9とソルダーレジスト4の間に、電子部品9を固定するための樹脂を充てんするが、ファインピッチになると、電子部品9の電極部10を小さくせざるを得ず、十分な間隔が取れにくい状態であった。
特に、電子部品としてベアチップを用いる際にファインピッチになると、ベアチップに形成するスタッドバンプの影響により電極部を2列以上に形成する必要があるが、これにより電子部品の電極部はますます小さくなり、電子部品と基板との間隔はますます取れにくい状態となっていた。
(1)プリント配線板上の導電性回路電極表面をレジストにより部分的に覆うレジスト形成工程と、前記導電性回路電極表面のうちレジストに覆われていない部分に粘着性を付与して粘着部を形成する粘着部形成工程と、前記粘着部にはんだ粉末を付着させるはんだ付着工程と、前記レジストを除去するレジスト除去工程と、前記プリント配線板を加熱してはんだ粉末を溶融させる第1の加熱工程と、を順次行うことを特徴とするはんだ回路基板の製造方法。
(2)プリント配線板上の導電性回路電極表面をレジストにより部分的に覆うレジスト形成工程と、前記導電性回路電極表面のうちレジストに覆われていない部分に粘着性を付与して粘着部を形成する粘着部形成工程と、前記レジストを除去するレジスト除去工程と、前記粘着部にはんだ粉末を付着させるはんだ付着工程と、前記プリント配線板を加熱してはんだ粉末を溶融させる第1の加熱工程と、を順次行うことを特徴とするはんだ回路基板の製造方法。
(3)前記はんだ付着工程の直後に、第2の加熱工程を設けることを特徴とする前項(1)または(2)に記載のはんだ回路基板の製造方法。
(4)前記レジスト除去工程と前記第1の加熱工程との間に、前記はんだ粉末にフラックスを塗布する工程を設けることを特徴とする前項(1)〜(3)の何れか1項に記載のはんだ回路基板の製造方法。
(5)前記レジストがアルカリ現像型であり、前記レジスト除去工程において、アルカリ性液を用いて前記レジストを除去することを特徴とする前項(1)〜(4)の何れか1項に記載のはんだ回路基板の製造方法。
(6)前記はんだ粉末がSn−Pb系はんだ粉末であり、第1の加熱工程における加熱温度が200℃〜350℃の範囲内であり、第2の加熱工程における加熱温度が100℃〜180℃の範囲内であることを特徴とする前項(2)〜(5)の何れか1項に記載のはんだ回路基板の製造方法。
(7)前記はんだ粉末がSn−Ag系はんだ粉末であり、第1の加熱工程における加熱温度が250℃〜350℃の範囲内であり、第2の加熱工程における加熱温度が100℃〜180℃の範囲内であることを特徴とする前項(2)〜(5)の何れか1項に記載のはんだ回路基板の製造方法。
(8)前記導電性回路電極が銅合金からなり、前記粘着部形成工程において、前記銅合金と、ベンゾトリアゾール系誘導体、ナフトトリアゾール系誘導体、イミダゾール系誘導体、ベンゾイミダゾール系誘導体、メルカプトベンゾチアゾール系誘導体、ベンゾチアゾールチオ脂肪酸系誘導体との反応により、前記レジストに覆われていない部分に粘着性を付与することを特徴とする前項(1)〜(7)の何れか1項に記載のはんだ回路基板の製造方法。
(9)前項(1)〜(8)の何れか1項に記載のはんだ回路基板の製造方法を用いて作製したはんだ回路基板。
(10)前項(9)に記載のはんだ回路基板に、電子部品を載置する電子部品載置工程と、前記はんだ粉末をリフローして前記電子部品の電極部分と前記はんだ回路基板とを接合する電子部品接合工程と、を含むことを特徴とする電子部品の実装方法。
先ず、図2(b)に示すように、プリント配線板24の電子部品の接合箇所26を除く回路パターン25の表面25aをレジスト27で覆う。後述するように、はんだ粉末を溶融させる前にレジスト27を除去するため、レジスト27にははんだの溶融温度に対して耐熱性を有するソルダーレジストを用いる必要はない。本実施形態の製造方法で用いるレジスト27には、後に説明する粘着部形成工程において、回路パターン25の表面25aのうち粘着性を付与しない部分を充分に保護できる性質を持ったレジストであり、かつ、粘着性付与化合物を変質させないレジストを用いる。即ち、レジスト27には、はんだ粉末の溶融温度での耐熱性を有していなくとも、フォトリソグラフィー技術を用いた微細なパターニングに適用可能なレジストを用いることができる。これにより、基板24上にファインピッチ化された微細なパターンの接合箇所26を形成できる。
次に、図2(c)に示すように、電子部品の接合箇所(レジスト27に覆われていない部分)26の回路パターン25の表面25aに粘着性を付与することにより、粘着部28を形成する。具体的には、次に説明するように、接合箇所26の回路パターン25の表面25aにおいて粘着性付与化合物を反応させることにより、粘着部28を形成できる。
一般式(1)で表されるベンゾトリアゾール系誘導体は、一般に、R1〜R4の炭素数が多くなる程、粘着性が強くなる。そのため、R1〜R4の炭素数は5〜16であることが好ましい。
また、粘着性付与化合物を反応させる際の浸漬時間は、特に限定されないが、作業効率の点から5秒〜5分程度の範囲になるように、他の条件を調整することが好ましい。
なお、粘着部28の生成速度、生成量等の生成効率がより高まる点から、粘着性付与化合物溶液中に濃度100〜1000ppm程度の銅イオンを共存させることが好ましい。
次に、プリント配線板29にはんだ粉末をふりかける等の方法により、はんだ粉末30を粘着部28に付着させる。その後、余分なはんだ粉末を除去すると、図2(d)に示すプリント配線板31が得られる。
本実施形態の製造方法では、図2(d)に示す粘着部形成工程の直後に第2の加熱工程を設けるのが好ましい。第2の加熱工程は、粘着部28へのはんだ粉末30の付着力を高めるための工程である。従って、第2の加熱工程を行うことにより、第2の加熱工程以降の各工程において、はんだ粉末30が粘着部28から脱離し難くなる。
次に、プリント配線板31のレジスト27を剥離する。レジスト27の剥離液の種類は、はんだ粉末30と粘着部28を溶解及び変質させないものであれば、特に限定されない。また、上述のように、ナフトトリアゾール系誘導体、ベンゾトリアゾール系誘導体、イミダゾール系誘導体、ベンゾイミダゾール系誘導体、メルカプトベンゾチアゾール系誘導体及びベンゾチアゾールチオ脂肪酸等を粘着性付与化合物として用いる場合は、これらの粘着性付与化合物を変質させない剥離液を用いる。このような剥離液としては、例えば、テトラメチルアンモニウムヒドロキシド(TMAH)、水酸化ナトリウム水溶液、水酸化テトラブチルアンモニウム(TBAH)、アンモニウム塩等のアルカリ性剥離液が挙げられる。
また、本実施形態の製造方法では、レジスト除去工程と次に説明する第1の加熱工程との間に、はんだ粉末30にフラックスを塗布する工程を設けてもよい。この工程により、第1の加熱工程におけるはんだ粉末30の溶融性を高めることができる。はんだ粉末30に塗布するフラックスとしては、ロジン等を用いることができる。
次に、プリント配線板32のはんだ粉末30を溶融させて、図2(f)に示すように接合箇所26の回路パターン25の表面25aにはんだ層33を形成したはんだ回路基板34を得る。はんだ層33は、後にはんだ回路を構成するものである。
次に、電子部品35としてファインピッチのベアチップを実装する場合はフリップチップボンダー等を用いて、図2(g)に示すように、はんだ層33とベアチップの電極上に形成されたバンプ36との位置を合わせ、加熱しながら加圧する。この工程により、図2(h)に示すように、はんだが溶融しはんだ回路37に接続された実装基板38を得る。
これに対し、本実施形態の製造方法では、基板39上の回路パターン40の電極表面に1つおきにレジスト層(図示略)を形成することで、電極の1つおきにはんだ層を形成した図4(a)に示すはんだ回路基板42を作製することができる。このはんだ回路基板42のはんだ層を形成した電極41と電子部品43の電極部44を、図4(b)に示すようにフリップチップボンダー用いて加熱しながら加圧すれば、図4(c)に示すようにはんだが溶融してはんだ回路45に接続された、ブリッジの発生がない実装基板46が得られる。
導電性物質に銅を用いてプリント配線板(以降では、単に「プリント配線板」と記載する)を作製した。導電性物質からなるプリント配線板の回路パターンの線幅は25μm、で最も狭い回路パターンの間隔は25μmとした。このプリント配線板にフォトレジスト(型番:H−7034、日立化成株式会社製)を貼り付けた基板を準備した。フォトマスクを用いてプリント配線板を紫外線露光した後、アルカリ性現像たとえば1%炭酸ナトリウム水溶液を用いてプリント配線板をパターニングした。導電性回路電極表面でレジストに覆われていない領域は、1電極おきにサイズを25×80μmとした。
プリント配線板としてフォトレジストを貼り付けていない基板を使用し、回路パターンをレジストで覆わずに粘着性を付与し、ハンダ粉末を付着させた。他は実施例と同様の工程及び条件によってプリント基板にベアチップを実装した。
上記の工程によりベアチップを実装したはんだ回路基板において、表1に示すように、実施例と比較例の双方で同程度のバンプ高さを有する微小バンプを形成できた。またフリップチップ実装においては、プリント配線板上にフォトレジストを形成した実施例の実装基板は良好であったが、プリント配線板上にフォトレジストを形成しなかった比較例の実装基板にはブリッジの発生が認められた。
Claims (8)
- プリント配線板上の導電性回路電極表面をレジストにより部分的に覆うレジスト形成工程と、
前記導電性回路電極表面のうちレジストに覆われていない部分に粘着性を付与して粘着部を形成する粘着部形成工程と、
前記レジストを除去するレジスト除去工程と、
前記粘着部にはんだ粉末を付着させるはんだ付着工程と、
前記プリント配線板を加熱してはんだ粉末を溶融させる第1の加熱工程と、
を順次行うことを特徴とするはんだ回路基板の製造方法。 - 前記はんだ付着工程の直後に、 第2の加熱工程を設けることを特徴とする請求項1に記載のはんだ回路基板の製造方法。
- 前記レジスト除去工程と前記第1の加熱工程との間に、
前記はんだ粉末にフラックスを塗布する工程を設けることを特徴とする請求項1に記載のはんだ回路基板の製造方法。 - 前記レジストがアルカリ現像型であり、
前記レジスト除去工程において、
アルカリ性液を用いて前記レジストを除去することを特徴とする請求項1に記載のはんだ回路基板の製造方法。 - 前記はんだ粉末がSn−Pb系はんだ粉末であり、
第1の加熱工程における加熱温度が200℃〜350℃の範囲内であり、
第2の加熱工程における加熱温度が100℃〜180℃の範囲内であることを特徴とする請求項2に記載のはんだ回路基板の製造方法。 - 前記はんだ粉末がSn−Ag系はんだ粉末であり、
第1の加熱工程における加熱温度が250℃〜350℃の範囲内であり、
第2の加熱工程における加熱温度が100℃〜180℃の範囲内であることを特徴とする請求項2に記載のはんだ回路基板の製造方法。 - 前記導電性回路電極が銅合金からなり、
前記粘着部形成工程において、
前記銅合金と、ベンゾトリアゾール系誘導体、ナフトトリアゾール系誘導体、イミダゾール系誘導体、ベンゾイミダゾール系誘導体、メルカプトベンゾチアゾール系誘導体、ベンゾチアゾールチオ脂肪酸系誘導体との反応により、前記レジストに覆われていない部分に粘着性を付与することを特徴とする請求項1に記載のはんだ回路基板の製造方法。 - 請求項1〜7のいずれか一項に記載のはんだ回路基板の製造方法を用いてはんだ回路基板を作製する工程と、
前記はんだ回路基板に、電子部品を載置する電子部品載置工程と、
前記はんだ粉末をリフローして前記電子部品の電極部分と前記はんだ回路基板とを接合する電子部品接合工程と、を含むことを特徴とする電子部品の実装方法。
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CN201480019731.9A CN105122957B (zh) | 2013-04-09 | 2014-04-09 | 焊料电路基板的制造方法、焊料电路基板和电子部件的安装方法 |
PCT/JP2014/060279 WO2014168175A1 (ja) | 2013-04-09 | 2014-04-09 | はんだ回路基板の製造方法、はんだ回路基板及び電子部品の実装方法 |
EP14783360.2A EP2986089A4 (en) | 2013-04-09 | 2014-04-09 | Method for manufacturing solder circuit board, solder circuit board, and method for mounting electronic component |
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