JP6179206B2 - メモリ制御装置 - Google Patents
メモリ制御装置 Download PDFInfo
- Publication number
- JP6179206B2 JP6179206B2 JP2013122353A JP2013122353A JP6179206B2 JP 6179206 B2 JP6179206 B2 JP 6179206B2 JP 2013122353 A JP2013122353 A JP 2013122353A JP 2013122353 A JP2013122353 A JP 2013122353A JP 6179206 B2 JP6179206 B2 JP 6179206B2
- Authority
- JP
- Japan
- Prior art keywords
- delay
- value
- register
- circuit
- dll
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2254—Calibration
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
- Memory System (AREA)
Description
先ず、DLL(Delay Locked Loop)を用いた遅延値の制御について説明する。DLLを使えば、基準クロックを入力することにより、クロック周期の期間に相当する遅延素子の段数を出力したり、DLL自体が基準クロックに対し固定位相差を持つ遅延回路として利用したりすることができる。例えば、上記技術を使って初期化時に、ある端子に基準クロックの1/4位相差相当の遅延値を設定したい場合、下記式(1)より求められる端子遅延設定値B0を、前記端子に接続されている遅延回路に設定すれば良い。
ここで、A0はDLLの出力値である。
ここで、A1はDLLの出力値である。
すなわち、
・DQSの遅延設定値=Nで、クロックエッジがDQSエッジより速い.
・DQSの遅延設定値=N+1で、DQSエッジがクロックエッジより速い.
この条件の場合、DQSの遅延設定値は、NまたはN+1で良い。
ここで、A0:初期化時のDLL出力値
B0:初期化時の端子遅延設定値
A1:現在のDLL出力値
B1:補正後の端子遅延設定値
である。
図2は、実施例2によるメモリ制御装置の要部構成を示したブロック図である。本実施例のメモリ制御装置30では、メモリ制御ブロック11とタイミング発生回路15とが接続され、メモリ制御ブロック11からタイミング発生回路15にリフレッシュフラグに関する信号が入力される。そして、タイミング発生回路15は、前記信号に基づいてメモリ22のリフレッシュサイクルに同期した(つまり、リフレッシュ毎に)タイミング信号を、遅延演算回路17に出力するよう構成されている。他の構成は、実施例1の場合と同様である。
図3は、実施例3の要部構成を示したブロック図である。本実施例では、タイミング発生回路15に温度センサ35が接続され、この温度センサ35での検出温度の信号がタイミング発生回路15に入力されるよう構成されている。他の構成は実施例1の場合と同様である。
図4は、実施例4によるメモリ制御装置の要部構成を示したブロック図である。本実施例のメモリ制御装置40では、新たにストローブ遅延制御回路としてWL制御回路41が設けられ、このWL制御回路41は第2レジスタ19に接続されている。なお、図示してないが、WL制御回路41は、第2レジスタ19の代わりに、第2レジスタ20または21に接続されていても良い。
11 メモリ制御ブロック
12,13,14 遅延回路
15 タイミング発生回路
16 DLL(Delay Locked Loop)
17 遅延演算回路
18 第1レジスタ
19,20,21 第2レジスタ
22 メモリ
30 メモリ制御装置
35 温度センサ
40 メモリ制御装置
41 WL制御回路
Claims (3)
- メモリに接続され端子毎に出力遅延値の設定が可変可能な複数の遅延回路と、
前記遅延回路と同じ遅延特性の遅延素子を内蔵するDLL(Delay Locked Loop)と、
前記DLLのロック状態時の出力値を任意のタイミングでレジスタ値として保持する第1レジスタと、
端子毎の遅延設定値をレジスタ値として保持する複数の第2レジスタと、
前記DLLの出力値、前記第1レジスタのレジスタ値、及び前記第2レジスタのレジスタ値に基づいて遅延値を演算する遅延演算回路とを備え、
前記遅延演算回路は、前記演算結果を前記第2レジスタのレジスタ値に上書きすることを特徴とするメモリ制御装置。 - 前記メモリの少なくとも一つの端子には前記遅延回路からストローブ信号が入力され、
WL(Write Leveling)コマンドの応答値により、前記ストローブ信号の遅延設定値を(+1)または(−1)にするストローブ遅延制御回路が設けられていることを特徴とする請求項1に記載のメモリ制御装置。 - 前記遅延回路と前記第2レジスタは、同数設けられていることを特徴とする請求項1又は請求項2に記載のメモリ制御装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013122353A JP6179206B2 (ja) | 2013-06-11 | 2013-06-11 | メモリ制御装置 |
US14/302,044 US20140362653A1 (en) | 2013-06-11 | 2014-06-11 | Memory control device and a delay controller |
US14/879,925 US9396789B2 (en) | 2013-06-11 | 2015-10-09 | Memory control device and a delay controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013122353A JP6179206B2 (ja) | 2013-06-11 | 2013-06-11 | メモリ制御装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014241003A JP2014241003A (ja) | 2014-12-25 |
JP6179206B2 true JP6179206B2 (ja) | 2017-08-16 |
Family
ID=52005360
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013122353A Expired - Fee Related JP6179206B2 (ja) | 2013-06-11 | 2013-06-11 | メモリ制御装置 |
Country Status (2)
Country | Link |
---|---|
US (2) | US20140362653A1 (ja) |
JP (1) | JP6179206B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10930329B2 (en) | 2018-11-07 | 2021-02-23 | Samsung Electronics Co., Ltd. | Storage device adjusting a timing of a data signal and a data strobe signal |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10381055B2 (en) | 2015-12-26 | 2019-08-13 | Intel Corporation | Flexible DLL (delay locked loop) calibration |
JP6832777B2 (ja) * | 2017-03-31 | 2021-02-24 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US11468960B2 (en) * | 2019-12-31 | 2022-10-11 | Micron Technology, Inc. | Semiconductor device with selective command delay and associated methods and systems |
US10892764B1 (en) * | 2020-08-14 | 2021-01-12 | Winbond Electronics Corp. | Delay locked loop device and update method thereof |
Family Cites Families (83)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6493378B1 (en) * | 1998-01-06 | 2002-12-10 | Topcon Gps Llc | Methods and apparatuses for reducing multipath errors in the demodulation of pseudo-random coded signals |
US6240042B1 (en) * | 1999-09-02 | 2001-05-29 | Micron Technology, Inc. | Output circuit for a double data rate dynamic random access memory, double data rate dynamic random access memory, method of clocking data out from a double data rate dynamic random access memory and method of providing a data strobe signal |
US6323705B1 (en) * | 2000-04-25 | 2001-11-27 | Winbond Electronics Corporation | Double cycle lock approach in delay lock loop circuit |
KR100422572B1 (ko) * | 2001-06-30 | 2004-03-12 | 주식회사 하이닉스반도체 | 레지스터 제어 지연고정루프 및 그를 구비한 반도체 소자 |
US6605969B2 (en) * | 2001-10-09 | 2003-08-12 | Micron Technology, Inc. | Method and circuit for adjusting the timing of ouput data based on an operational mode of output drivers |
US6819599B2 (en) * | 2002-08-01 | 2004-11-16 | Micron Technology, Inc. | Programmable DQS preamble |
JP2004110906A (ja) * | 2002-09-17 | 2004-04-08 | Renesas Technology Corp | 半導体記憶装置 |
JP3821787B2 (ja) * | 2003-02-27 | 2006-09-13 | エルピーダメモリ株式会社 | Dll回路 |
US6859397B2 (en) * | 2003-03-05 | 2005-02-22 | Sandisk Corporation | Source side self boosting technique for non-volatile memory |
US7111111B2 (en) * | 2003-07-08 | 2006-09-19 | Broadcom Corporation | Scheme for optimal settings for DDR interface |
US7191279B2 (en) * | 2003-07-08 | 2007-03-13 | Broadcom Corporation | Schmoo runtime reduction and dynamic calibration based on a DLL lock value |
US6960952B2 (en) * | 2003-09-11 | 2005-11-01 | Rambus, Inc. | Configuring and selecting a duty cycle for an output driver |
US7177199B2 (en) * | 2003-10-20 | 2007-02-13 | Sandisk Corporation | Behavior based programming of non-volatile memory |
US7020017B2 (en) * | 2004-04-06 | 2006-03-28 | Sandisk Corporation | Variable programming of non-volatile memory |
US7023733B2 (en) * | 2004-05-05 | 2006-04-04 | Sandisk Corporation | Boosting to control programming of non-volatile memory |
US7020026B2 (en) * | 2004-05-05 | 2006-03-28 | Sandisk Corporation | Bitline governed approach for program control of non-volatile memory |
US7307884B2 (en) * | 2004-06-15 | 2007-12-11 | Sandisk Corporation | Concurrent programming of non-volatile memory |
US7145373B2 (en) * | 2004-07-29 | 2006-12-05 | Intel Corporation | Frequency-controlled DLL bias |
US7173859B2 (en) * | 2004-11-16 | 2007-02-06 | Sandisk Corporation | Faster programming of higher level states in multi-level cell flash memory |
US7116143B2 (en) * | 2004-12-30 | 2006-10-03 | Micron Technology, Inc. | Synchronous clock generator including duty cycle correction |
US7430138B2 (en) * | 2005-03-31 | 2008-09-30 | Sandisk Corporation | Erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells |
US7522457B2 (en) * | 2005-03-31 | 2009-04-21 | Sandisk Corporation | Systems for erase voltage manipulation in non-volatile memory for controlled shifts in threshold voltage |
US7457166B2 (en) * | 2005-03-31 | 2008-11-25 | Sandisk Corporation | Erase voltage manipulation in non-volatile memory for controlled shifts in threshold voltage |
JP4036868B2 (ja) * | 2005-03-31 | 2008-01-23 | 日本テキサス・インスツルメンツ株式会社 | 遅延同期ループ回路 |
US7295478B2 (en) * | 2005-05-12 | 2007-11-13 | Sandisk Corporation | Selective application of program inhibit schemes in non-volatile memory |
JP5153094B2 (ja) * | 2005-09-29 | 2013-02-27 | エスケーハイニックス株式会社 | Dll装置及びdllクロック生成方法 |
JP4764270B2 (ja) * | 2005-09-29 | 2011-08-31 | 株式会社ハイニックスセミコンダクター | ロックフェイル防止のための遅延固定ループクロックの生成方法及びその装置 |
JP4775141B2 (ja) * | 2005-09-29 | 2011-09-21 | 株式会社ハイニックスセミコンダクター | 遅延固定ループ回路 |
US7227809B2 (en) * | 2005-10-14 | 2007-06-05 | Micron Technology, Inc. | Clock generator having a delay locked loop and duty cycle correction circuit in a parallel configuration |
JP2007280562A (ja) * | 2006-04-11 | 2007-10-25 | Sharp Corp | リフレッシュ制御装置 |
US7440322B2 (en) * | 2006-04-20 | 2008-10-21 | Sandisk Corporation | Method and system for flash memory devices |
TWI324858B (en) * | 2006-08-16 | 2010-05-11 | Holtek Semiconductor Inc | Dll and angle generator |
JP4959264B2 (ja) * | 2006-09-15 | 2012-06-20 | 株式会社リコー | メモリ制御装置 |
JP2008084471A (ja) * | 2006-09-28 | 2008-04-10 | Toshiba Corp | 半導体記憶装置 |
US7474561B2 (en) * | 2006-10-10 | 2009-01-06 | Sandisk Corporation | Variable program voltage increment values in non-volatile memory program operations |
US7450426B2 (en) * | 2006-10-10 | 2008-11-11 | Sandisk Corporation | Systems utilizing variable program voltage increment values in non-volatile memory program operations |
US7535766B2 (en) * | 2006-10-13 | 2009-05-19 | Sandisk Corporation | Systems for partitioned soft programming in non-volatile memory |
US7652516B2 (en) * | 2006-10-20 | 2010-01-26 | Marvell Israel (M.I.S.L.) Ltd. | Apparatus and method for generating a clock signal |
US7596031B2 (en) * | 2006-10-30 | 2009-09-29 | Sandisk Corporation | Faster programming of highest multi-level state for non-volatile memory |
US7535763B2 (en) * | 2006-11-16 | 2009-05-19 | Sandisk Corporation | Controlled boosting in non-volatile memory soft programming |
US7697338B2 (en) * | 2006-11-16 | 2010-04-13 | Sandisk Corporation | Systems for controlled boosting in non-volatile memory soft programming |
US7668019B2 (en) * | 2006-11-28 | 2010-02-23 | Samsung Electronics Co., Ltd. | Non-volatile memory device and erasing method thereof |
US7433241B2 (en) * | 2006-12-29 | 2008-10-07 | Sandisk Corporation | Programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data |
US7468918B2 (en) * | 2006-12-29 | 2008-12-23 | Sandisk Corporation | Systems for programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data |
US7450430B2 (en) * | 2006-12-29 | 2008-11-11 | Sandisk Corporation | Programming non-volatile memory with reduced program disturb by using different pre-charge enable voltages |
US7463531B2 (en) * | 2006-12-29 | 2008-12-09 | Sandisk Corporation | Systems for programming non-volatile memory with reduced program disturb by using different pre-charge enable voltages |
US7773429B2 (en) * | 2007-02-22 | 2010-08-10 | Hynix Semiconductor Inc. | Non-volatile memory device and driving method thereof |
JP5045189B2 (ja) * | 2007-03-30 | 2012-10-10 | 富士通セミコンダクター株式会社 | インタフェース回路 |
US7508711B2 (en) * | 2007-04-30 | 2009-03-24 | Intel Corporation | Arrangements for operating a memory circuit |
US7548462B2 (en) * | 2007-06-29 | 2009-06-16 | Macronix International Co., Ltd. | Double programming methods of a multi-level-cell nonvolatile memory |
US7489543B1 (en) * | 2007-07-25 | 2009-02-10 | Micron Technology, Inc. | Programming multilevel cell memory arrays |
US7751245B2 (en) * | 2007-10-10 | 2010-07-06 | Micron Technology, Inc. | Programming sequence in NAND memory |
KR100883140B1 (ko) * | 2007-11-02 | 2009-02-10 | 주식회사 하이닉스반도체 | 데이터 출력 제어회로, 반도체 메모리 장치 및 그의 동작방법 |
JP5369430B2 (ja) * | 2007-11-20 | 2013-12-18 | 富士通株式会社 | 可変遅延回路,メモリ制御回路,遅延量設定装置,遅延量設定方法および遅延量設定プログラム |
US7929361B2 (en) * | 2008-03-31 | 2011-04-19 | Advanced Micro Devices, Inc. | Circuit using a shared delay locked loop (DLL) and method therefor |
US7869287B2 (en) * | 2008-03-31 | 2011-01-11 | Advanced Micro Devices, Inc. | Circuit for locking a delay locked loop (DLL) and method therefor |
US8111548B2 (en) * | 2008-07-21 | 2012-02-07 | Sandisk Technologies Inc. | Programming non-volatile storage using binary and multi-state programming processes |
KR101532754B1 (ko) * | 2008-09-22 | 2015-07-02 | 삼성전자주식회사 | 비휘발성 메모리 장치의 프로그램 방법 |
JP2010086246A (ja) * | 2008-09-30 | 2010-04-15 | Nec Electronics Corp | メモリインターフェース及びメモリインターフェースの動作方法 |
KR20100043935A (ko) * | 2008-10-21 | 2010-04-29 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그것의 프로그램 방법 |
US7876137B2 (en) * | 2008-11-20 | 2011-01-25 | Promos Technologies Pte.Ltd. | Configurable architecture hybrid analog/digital delay locked loop (DLL) and technique with fast open loop digital locking for integrated circuit devices |
US8064252B2 (en) * | 2008-11-21 | 2011-11-22 | Micron Technology, Inc. | Multi-pass programming in a memory device |
KR20100072704A (ko) * | 2008-12-22 | 2010-07-01 | 삼성전자주식회사 | 칼럼 어드레스 스트로브 기입 레이턴시에 의해 제어되는 지연동기 루프 회로 |
US8026544B2 (en) * | 2009-03-30 | 2011-09-27 | Sandisk Technologies Inc. | Fabricating and operating a memory array having a multi-level cell region and a single-level cell region |
KR101572830B1 (ko) * | 2009-06-22 | 2015-11-30 | 삼성전자주식회사 | 비휘발성 메모리 장치의 프로그램 방법, 비휘발성 메모리 장치 및 비휘발성 메모리 시스템 |
US8619474B2 (en) * | 2009-09-10 | 2013-12-31 | Micron Technology, Inc. | Data line management in a memory device |
US8139419B2 (en) * | 2009-12-08 | 2012-03-20 | Micron Technology, Inc. | Programming methods and memories |
KR20110131648A (ko) * | 2010-05-31 | 2011-12-07 | 삼성전자주식회사 | 비휘발성 메모리 장치, 그것을 포함한 메모리 시스템 및 메모리 카드 및 그것의 프로그램 방법 |
KR20120003351A (ko) * | 2010-07-02 | 2012-01-10 | 삼성전자주식회사 | 3차원 비휘발성 메모리 장치 및 그 동작방법 |
JP2012084207A (ja) * | 2010-10-13 | 2012-04-26 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2012100058A (ja) * | 2010-11-01 | 2012-05-24 | Panasonic Corp | 遅延回路、遅延制御装置、メモリ制御装置及び情報端末機器 |
TWI449339B (zh) * | 2010-12-13 | 2014-08-11 | Ind Tech Res Inst | 時脈偏移補償裝置 |
JP5568057B2 (ja) * | 2011-05-30 | 2014-08-06 | 株式会社東芝 | メモリアクセス回路及びメモリシステム |
JP2013008112A (ja) * | 2011-06-22 | 2013-01-10 | Panasonic Corp | メモリコントローラおよび遅延調整方法 |
JP2013097850A (ja) * | 2011-11-07 | 2013-05-20 | Elpida Memory Inc | 半導体装置 |
US8638608B2 (en) * | 2012-03-26 | 2014-01-28 | Sandisk Technologies Inc. | Selected word line dependent select gate voltage during program |
KR101927212B1 (ko) * | 2012-05-09 | 2019-03-07 | 삼성전자주식회사 | 비휘발성 메모리 장치의 프로그래밍 방법 |
US9047237B2 (en) * | 2012-08-03 | 2015-06-02 | Cypress Semiconductor Corporation | Power savings apparatus and method for memory device using delay locked loop |
WO2014137928A2 (en) * | 2013-03-04 | 2014-09-12 | Sandisk Technologies Inc. | Dynamic erase depth for improved endurance of non-volatile memory |
KR102079630B1 (ko) * | 2013-03-13 | 2020-04-07 | 삼성전자주식회사 | 지연동기회로를 가지는 동기 반도체 메모리 장치 및 파워 세이빙을 위한 지연동기회로 블록 구동 제어 방법 |
KR102112596B1 (ko) * | 2013-03-15 | 2020-05-19 | 삼성전자주식회사 | 비휘발성 메모리 장치 및 이의 프로그래밍 방법 |
US8982626B2 (en) * | 2013-06-05 | 2015-03-17 | Sandisk Technologies Inc. | Program and read operations for 3D non-volatile memory based on memory hole diameter |
US8982637B1 (en) * | 2013-09-12 | 2015-03-17 | Sandisk Technologies Inc. | Vread bias allocation on word lines for read disturb reduction in 3D non-volatile memory |
-
2013
- 2013-06-11 JP JP2013122353A patent/JP6179206B2/ja not_active Expired - Fee Related
-
2014
- 2014-06-11 US US14/302,044 patent/US20140362653A1/en not_active Abandoned
-
2015
- 2015-10-09 US US14/879,925 patent/US9396789B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10930329B2 (en) | 2018-11-07 | 2021-02-23 | Samsung Electronics Co., Ltd. | Storage device adjusting a timing of a data signal and a data strobe signal |
US11158359B2 (en) | 2018-11-07 | 2021-10-26 | Samsung Electronics Co., Ltd. | Storage device adjusting a timing of a data signal and a data strobe signal |
Also Published As
Publication number | Publication date |
---|---|
JP2014241003A (ja) | 2014-12-25 |
US20140362653A1 (en) | 2014-12-11 |
US20160035408A1 (en) | 2016-02-04 |
US9396789B2 (en) | 2016-07-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9939839B2 (en) | Low power automatic calibration method for high frequency oscillators | |
JP6179206B2 (ja) | メモリ制御装置 | |
JP4416580B2 (ja) | 遅延制御装置 | |
US6466491B2 (en) | Memory system and memory controller with reliable data latch operation | |
JP4921888B2 (ja) | インターフェース回路 | |
JP5407551B2 (ja) | タイミング調整回路及びタイミング調整方法 | |
US7671647B2 (en) | Apparatus and method for trimming static delay of a synchronizing circuit | |
US9305622B1 (en) | Data strobe to data delay calibration | |
JP2010182149A (ja) | メモリ制御装置、及びメモリ制御方法 | |
TWI703575B (zh) | 記憶體訊號相位差校正電路與方法 | |
JP5653177B2 (ja) | メモリインターフェース回路及び半導体装置 | |
US10408863B2 (en) | Reference voltage prediction in memory subsystem | |
US9286961B1 (en) | Memory controller half-clock delay adjustment | |
WO2010038422A1 (ja) | メモリインターフェース | |
WO2016064454A1 (en) | Dynamic selection of output delay in a memory control device | |
JP5568057B2 (ja) | メモリアクセス回路及びメモリシステム | |
US20180366168A1 (en) | Memory controller | |
KR20230029992A (ko) | 대체 결과들을 사용한 메모리 서브시스템 교정 | |
US8065550B2 (en) | Digital delay locked loop circuit using mode register set | |
US8482326B2 (en) | DLL circuit, semiconductor device including the same, and data processing system | |
JP2009117020A (ja) | 半導体メモリ装置 | |
US8610471B2 (en) | Delay locked loop | |
US6763401B2 (en) | Direct memory access controller | |
JP5919918B2 (ja) | メモリ制御装置及びマスクタイミング制御方法 | |
JP2004220643A (ja) | 半導体メモリ制御装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20160607 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20170321 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170328 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170428 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20170620 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20170703 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 6179206 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
LAPS | Cancellation because of no payment of annual fees |