JP6166525B2 - 電子部品の製造方法 - Google Patents
電子部品の製造方法 Download PDFInfo
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- JP6166525B2 JP6166525B2 JP2012231902A JP2012231902A JP6166525B2 JP 6166525 B2 JP6166525 B2 JP 6166525B2 JP 2012231902 A JP2012231902 A JP 2012231902A JP 2012231902 A JP2012231902 A JP 2012231902A JP 6166525 B2 JP6166525 B2 JP 6166525B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 43
- 238000007747 plating Methods 0.000 claims description 166
- 238000000034 method Methods 0.000 claims description 107
- 238000007789 sealing Methods 0.000 claims description 103
- 239000000758 substrate Substances 0.000 claims description 103
- 230000008569 process Effects 0.000 claims description 60
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 239000010949 copper Substances 0.000 claims description 18
- 238000005520 cutting process Methods 0.000 claims description 11
- 239000012212 insulator Substances 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 257
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 39
- 239000004020 conductor Substances 0.000 description 36
- 229920005989 resin Polymers 0.000 description 12
- 239000011347 resin Substances 0.000 description 12
- 239000010931 gold Substances 0.000 description 10
- 238000009713 electroplating Methods 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 7
- 238000006073 displacement reaction Methods 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 238000010897 surface acoustic wave method Methods 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 239000003960 organic solvent Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 230000002378 acidificating effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003054 catalyst Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- 229910000521 B alloy Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- QDWJUBJKEHXSMT-UHFFFAOYSA-N boranylidynenickel Chemical compound [Ni]#B QDWJUBJKEHXSMT-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- KERTUBUCQCSNJU-UHFFFAOYSA-L nickel(2+);disulfamate Chemical compound [Ni+2].NS([O-])(=O)=O.NS([O-])(=O)=O KERTUBUCQCSNJU-UHFFFAOYSA-L 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- OFNHPGDEEMZPFG-UHFFFAOYSA-N phosphanylidynenickel Chemical compound [P].[Ni] OFNHPGDEEMZPFG-UHFFFAOYSA-N 0.000 description 1
- 239000002952 polymeric resin Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/058—Holders; Supports for surface acoustic wave devices
- H03H9/059—Holders; Supports for surface acoustic wave devices consisting of mounting pads or bumps
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/10—Mounting in enclosures
- H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices
- H03H9/1071—Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the SAW device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Acoustics & Sound (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Description
10a、10b、10c、10d 端子
11 上面
12 デバイスチップ
13 下面
14 封止部
14a 樹脂層
14b 金属層
16 リッド
18、18c、18d、18e、18f メッキ層
18a Ni層
18b Au層
18g、18h Cu層
22、23 レジスト層
26 バレル
62、64、66 導体層
62c、64c、64d 給電線
64a 接地配線
64b 信号配線
100、200.300.400、500、600、700、800、900、1000 電子部品
810 多層基板
Claims (7)
- 絶縁性基板の上面にデバイスチップを実装する工程と、
前記デバイスチップを封止する金属層を含む封止部を設ける工程と、
前記絶縁性基板及び前記封止部を切断する工程と、
バレルメッキ法を用いて前記封止部を覆うメッキ層を設ける工程と、を有し、
前記メッキ層を設ける工程は、電解バレルメッキ法を用いて前記メッキ層を設ける工程を含み、
前記メッキ層を設ける工程は、前記封止部を覆う第1メッキ層と、前記絶縁性基板の下面に設けられた端子に接触する第2メッキ層とを設ける工程であり、
前記メッキ層を設ける工程の後に、前記端子が露出するように前記第2メッキ層を除去する工程を有することを特徴とする電子部品の製造方法。 - 絶縁性基板の上面にデバイスチップを実装する工程と、
前記デバイスチップを封止する絶縁体により形成された封止部を設ける工程と、
前記絶縁性基板及び前記封止部を切断し電子部品に個片化する工程と、
前記個片化する工程の後、バレルメッキ法を用いて前記封止部を覆うメッキ層を設ける工程と、を有し、
前記メッキ層を設ける工程は、前記絶縁性基板の表面が露出した状態で、無電解バレルメッキすることで、前記絶縁性基板の露出した表面には前記メッキ層が形成されず前記封止部を覆うように前記封止部の表面に第3メッキ層を設けた後、前記絶縁性基板の表面が露出した状態で、電解バレルメッキ法を用いて前記第3メッキ層の表面に第4メッキ層を設ける工程を含むことを特徴とする電子部品の製造方法。 - 前記メッキ層を設ける工程の前に前記絶縁性基板の下面に設けられた端子を覆うレジスト層を設ける工程と、
前記メッキ層を設ける工程の後に前記レジスト層を除去する工程と、を有することを特徴とする請求項2記載の電子部品の製造方法。 - 前記封止部を設ける工程は、前記封止部を前記デバイスチップの側面及び上面に沿うような前記封止部を設ける工程であることを特徴とする請求項1から3いずれか一項記載の電子部品の製造方法。
- 前記絶縁性基板の下面には端子が設けられ、
前記切断する工程は、前記絶縁性基板の下面側から前記絶縁性基板及び前記封止部を切断する工程であることを特徴とする請求項1から4いずれか一項記載の電子部品の製造方法。 - 前記メッキ層を設ける工程は、前記封止部を覆う第5メッキ層と、前記絶縁性基板の下面に設けられた端子を覆う第6メッキ層とを設ける工程であり、
前記第5メッキ層及び前記第6メッキ層は銅により形成されることを特徴とする請求項5記載の電子部品の製造方法。 - 前記絶縁性基板の下面に設けられた端子に、銅により形成される第7メッキ層を設ける工程と、
前記メッキ層を設ける工程の前に前記第7メッキ層を覆うレジスト層を設ける工程と、
前記メッキ層を設ける工程の後に前記レジスト層を除去する工程と、を有することを特徴とする請求項2記載の電子部品の製造方法。
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JP2012231902A JP6166525B2 (ja) | 2012-06-18 | 2012-10-19 | 電子部品の製造方法 |
US13/918,002 US8969173B2 (en) | 2012-06-18 | 2013-06-14 | Method of fabricating electronic component |
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JP2012137029 | 2012-06-18 | ||
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JP2012231902A JP6166525B2 (ja) | 2012-06-18 | 2012-10-19 | 電子部品の製造方法 |
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JP6166525B2 true JP6166525B2 (ja) | 2017-07-19 |
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US9847235B2 (en) * | 2014-02-26 | 2017-12-19 | Infineon Technologies Ag | Semiconductor device with plated lead frame, and method for manufacturing thereof |
JP6509147B2 (ja) * | 2016-02-29 | 2019-05-08 | 太陽誘電株式会社 | 電子デバイス |
CN105958963B (zh) * | 2016-05-12 | 2019-03-26 | 锐迪科微电子(上海)有限公司 | 一种封装结构及其制造方法 |
WO2018092529A1 (ja) * | 2016-11-16 | 2018-05-24 | 株式会社村田製作所 | 高周波モジュール |
JP6449836B2 (ja) | 2016-11-25 | 2019-01-09 | 太陽誘電株式会社 | 電子部品およびその製造方法 |
JP6653646B2 (ja) | 2016-12-02 | 2020-02-26 | 太陽誘電株式会社 | 電子部品およびその製造方法 |
WO2020179020A1 (ja) | 2019-03-06 | 2020-09-10 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
CN116157914A (zh) * | 2020-09-08 | 2023-05-23 | 株式会社村田制作所 | 模块和电子部件 |
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JP2001244376A (ja) * | 2000-02-28 | 2001-09-07 | Hitachi Ltd | 半導体装置 |
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JP2004281919A (ja) * | 2003-03-18 | 2004-10-07 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法 |
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US8476115B2 (en) * | 2011-05-03 | 2013-07-02 | Stats Chippac, Ltd. | Semiconductor device and method of mounting cover to semiconductor die and interposer with adhesive material |
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