JP6146486B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6146486B2 JP6146486B2 JP2015557710A JP2015557710A JP6146486B2 JP 6146486 B2 JP6146486 B2 JP 6146486B2 JP 2015557710 A JP2015557710 A JP 2015557710A JP 2015557710 A JP2015557710 A JP 2015557710A JP 6146486 B2 JP6146486 B2 JP 6146486B2
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- 239000004065 semiconductor Substances 0.000 title claims description 122
- 239000010410 layer Substances 0.000 claims description 115
- 239000011229 interlayer Substances 0.000 claims description 58
- 239000002344 surface layer Substances 0.000 claims description 19
- 238000009413 insulation Methods 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 70
- 229920005591 polysilicon Polymers 0.000 description 70
- 239000000758 substrate Substances 0.000 description 35
- 230000015556 catabolic process Effects 0.000 description 30
- 238000011084 recovery Methods 0.000 description 26
- 239000012535 impurity Substances 0.000 description 15
- 238000010586 diagram Methods 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 8
- 230000001939 inductive effect Effects 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Description
実施の形態1にかかる半導体装置について説明する。図1は、本発明の実施の形態1にかかる半導体装置100の構成を示す平面図である。図2は、図1(b)の切断線X1−X1、切断線X2−X2および切断線X3−X3における断面構造を示す断面図である。図1(a)には超接合半導体基板(半導体チップ)1のおもて面に配置されたソース電極14、ゲートパッド電極15およびゲートランナー15aの平面レイアウトを示し、n型領域(nカラム)とp型領域(pカラム)とを交互に繰り返し配置した並列pn層(pn並列カラム)4を破線で示す。
次に、実施の形態2にかかる半導体装置の構成について説明する。図4は、本発明の実施の形態2にかかる半導体装置200の構成を示す断面図である。実施の形態2にかかる半導体装置200の平面レイアウトは実施の形態1にかかる半導体装置(図1)と同様である。図4には、図1(b)の切断線X1−X1における断面構造を示す。この図4は図2(a)に示す断面構造の変形例である。実施の形態2にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、ゲートパッド電極15直下のポリシリコンゲート電極8aを備えていない点である。
次に、実施の形態3にかかる半導体装置の構成について説明する。図5は、本発明の実施の形態3にかかる半導体装置300の構成を示す断面図である。実施の形態3にかかる半導体装置300の平面レイアウトは実施の形態1にかかる半導体装置(図1)と同様である。図5には、図1(b)の切断線X1−X1における断面構造を示す。この図5は図2(a)に示す断面構造の変形例である。実施の形態3にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、ゲートパッド電極15直下のポリシリコンゲート電極8aの大きさ(表面積)をゲートパッド電極15と同じ大きさにした点である。
次に、実施の形態4にかかる半導体装置の構成について説明する。図6は、本発明の実施の形態4にかかる半導体装置400の構成を示す断面図である。実施の形態4にかかる半導体装置400の平面レイアウトは実施の形態1にかかる半導体装置(図1)と同様である。図6には、図1(b)の切断線X4−X4および切断線Y−Yにおける断面構造を示す。図6(a)には、図1(b)の切断線Y−Yにおける断面構造を示す。図6(b)には、図1(b)の切断線X1−X1における断面構造を示す。図6(c)には、図1(b)の切断線X4−X4における断面構造を示す。実施の形態4にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、ソース電極14直下に配置されるポリシリコンゲート電極8cと、ゲートパッド電極15直下に配置されるポリシリコンゲート電極8aとを電気的に切り離した点である。
1a 第1n層
1b 第2n層
2 pカラム
3 nカラム
4 pn並列カラム
5 pチャネル領域
5a,9a 延伸箇所
6 nソース領域
7 ゲート酸化膜
8,8a,8b,8c ポリシリコンゲート電極
9 pコンタクト領域
10 nドレイン領域
11 ドレイン電極
12 層間絶縁膜
13 コンタクトホール
14 ソース電極
15 ゲートパッド電極
16 pウェル領域
17 p高濃度領域
21 ボディダイオード
22,23 pn接合
30 切り欠き
100,200,300,400 半導体装置
101 超接合型MOSFET
W1 pウェル領域の幅
W2 p高濃度領域の幅
W3 pチャネル領域の幅
W4 pコンタクト領域の幅
W5 ゲートパッド電極の直下のポリシリコンゲート電極の幅
W6 ソース電極の直下のポリシリコンゲート電極の幅
Claims (11)
- 第1の第1導電型半導体層と、
前記第1の第1導電型半導体層の第1主面上に、前記第1の第1導電型半導体層の第1主面に水平な方向に延びるストライプ状の平面形状に、第1導電型カラムと第2導電型カラムとを交互に繰り返し配置してなるpn並列カラムと、
前記pn並列カラムの、前記第1の第1導電型半導体層側に対して反対側の表面に配置される第2の第1導電型半導体層と、
前記第2の第1導電型半導体層の内部に、前記第1の第1導電型半導体層の第1主面に水平な方向に延びるストライプ状の平面形状で配置され、かつ前記第2の第1導電型半導体層を深さ方向に貫通して前記第2導電型カラムに接する第2導電型チャネル領域と、
前記第2の第1導電型半導体層の内部に、前記第2導電型チャネル領域がストライプ状に延びる第1方向に平行なストライプ状の平面形状で配置され、前記第2の第1導電型半導体層を深さ方向に貫通して前記第2導電型カラムに接し、かつ前記第1方向の一方の端部が前記第2導電型チャネル領域の前記第1方向の一方の端部に連結された第2導電型ウェル領域と、
前記第2導電型チャネル領域の内部に配置された第1導電型ソース領域と、
前記第2導電型チャネル領域の内部の、前記第1導電型ソース領域よりも前記第1方向と直交する第2方向の内側に、前記第1方向に延びる直線状の平面形状で配置され、前記第1導電型ソース領域に接する第2導電型コンタクト領域と、
前記第2導電型ウェル領域の内部に、前記第1方向に延びる直線状の平面形状で配置され、かつ前記第1方向の一方の端部が前記第2導電型コンタクト領域の前記第1方向の一方の端部に連結された第2導電型高濃度領域と、
前記第2導電型チャネル領域の、前記第1導電型ソース領域と前記第2の第1導電型半導体層とに挟まれた部分の表面上に、前記第2の第1導電型半導体層上に亘って、ゲート絶縁膜を介して配置される第1のゲート電極と、
前記第1のゲート電極の表面に配置される層間絶縁膜と、
前記層間絶縁膜上に配置され、前記層間絶縁膜のコンタクトホールを介して前記第2導電型コンタクト領域および前記第1導電型ソース領域に接続されたソース電極と、
前記層間絶縁膜上の、前記層間絶縁膜を挟んで前記第2導電型ウェル領域および前記第2導電型高濃度領域に対向する位置に前記ソース電極と離間して配置され、前記第1のゲート電極に電気的に接続されたゲートパッド電極と、
前記第1の第1導電型半導体層の第2主面上に配置された第1導電型ドレイン領域と、
前記第1導電型ドレイン領域に接続されたドレイン電極と、
を備え、
前記第2導電型ウェル領域の、前記第2方向の幅は、前記第2導電型チャネル領域の前記第2方向の幅より広いことを特徴とする半導体装置。 - 前記第2導電型ウェル領域および前記第2の第1導電型半導体層の、隣り合う前記第2導電型高濃度領域の間に挟まれた部分の表面上に前記ゲート絶縁膜を介して配置される第2のゲート電極と、
前記第2のゲート電極の表面に配置された前記層間絶縁膜と、
をさらに備えることを特徴とする請求項1に記載の半導体装置。 - 前記ソース電極と前記ゲートパッド電極との間に、
前記第2導電型チャネル領域を前記第1方向に延在させた部分からなり、前記第2の第1導電型半導体層を深さ方向に貫通して前記第2導電型カラムに接し、かつ前記第2導電型ウェル領域の前記第1方向の一方の端部に接して前記第2導電型チャネル領域と前記第2導電型ウェル領域とを連結する第1の第2導電型延伸領域と、
前記第1の第2導電型延伸領域の内部に、前記第2導電型コンタクト領域を前記第1方向に延在させた部分を配置させてなり、前記第2導電型高濃度領域の前記第1方向の一方の端部に接して前記第2導電型コンタクト領域と前記第2導電型高濃度領域とを連結する第2の第2導電型延伸領域と、
前記第1の第2導電型延伸領域および前記第2の第1導電型半導体層の、隣り合う前記第2の第2導電型延伸領域の間に挟まれた部分の表面上に、前記ゲート絶縁膜を介して配置された第3のゲート電極と、
前記第3のゲート電極の表面に配置された前記層間絶縁膜と、をさらに備え、
前記第3のゲート電極は、前記第1のゲート電極と前記第2のゲート電極とを連結することを特徴とする請求項2に記載の半導体装置。 - 第1導電型ドリフト層の第1主面の表面層に、前記第1導電型ドリフト層の第1主面に水平な方向に延びるストライプ状の平面形状で配置された第2導電型チャネル領域と、
前記第1導電型ドリフト層の第1主面の表面層に、前記第2導電型チャネル領域がストライプ状に延びる第1方向に平行なストライプ状の平面形状で配置され、かつ前記第1方向の一方の端部が前記第2導電型チャネル領域の前記第1方向の一方の端部に連結された第2導電型ウェル領域と、
前記第2導電型チャネル領域の内部に配置された第1導電型ソース領域と、
前記第2導電型チャネル領域の内部の、前記第1導電型ソース領域よりも前記第1方向と直交する第2方向の内側に、前記第1方向に延びる直線状の平面形状で配置され、前記第1導電型ソース領域に接する第2導電型コンタクト領域と、
前記第2導電型ウェル領域の内部に、前記第1方向に延びる直線状の平面形状で配置され、かつ前記第1方向の一方の端部が前記第2導電型コンタクト領域の前記第1方向の一方の端部に連結された第2導電型高濃度領域と、
前記第2導電型チャネル領域の、前記第1導電型ソース領域と前記第1導電型ドリフト層とに挟まれた部分の表面上に、ゲート絶縁膜を介して配置された第1のゲート電極と、
前記第1のゲート電極の表面に配置される層間絶縁膜と、
前記層間絶縁膜上に配置され、前記層間絶縁膜のコンタクトホールを介して前記第2導電型コンタクト領域および前記第1導電型ソース領域に接続されたソース電極と、
前記層間絶縁膜上の、前記層間絶縁膜を挟んで前記第2導電型ウェル領域および前記第2導電型高濃度領域に対向する位置に前記ソース電極と離間して配置され、前記第1のゲート電極に電気的に接続されたゲートパッド電極と、
前記第1導電型ドリフト層の第2主面上に配置された第1導電型ドレイン領域と、
前記第1導電型ドレイン領域に接続されたドレイン電極と、
を備え、
前記第2導電型ウェル領域の、前記第2方向の幅は、前記第2導電型チャネル領域の前記第2方向の幅より広いことを特徴とする半導体装置。 - 前記第2導電型ウェル領域および前記第1導電型ドリフト層の、隣り合う前記第2導電型高濃度領域の間に挟まれた部分の表面上に、前記ゲート絶縁膜を介して配置される第2のゲート電極と、
前記第2のゲート電極の表面に配置された前記層間絶縁膜と、
をさらに備えることを特徴とする請求項4に記載の半導体装置。 - 前記ソース電極と前記ゲートパッド電極との間に、
前記第2導電型チャネル領域を前記第1方向に延在させた部分からなり、前記第2導電型ウェル領域の前記第1方向の一方の端部に接して前記第2導電型チャネル領域と前記第2導電型ウェル領域とを連結する第1の第2導電型延伸領域と、
前記第1の第2導電型延伸領域の内部に、前記第2導電型コンタクト領域を前記第1方向に延在させた部分を配置させてなり、前記第2導電型高濃度領域の前記第1方向の一方の端部に接して前記第2導電型コンタクト領域と前記第2導電型高濃度領域とを連結する第2の第2導電型延伸領域と、
前記第1の第2導電型延伸領域および前記第1導電型ドリフト層の、隣り合う前記第2の第2導電型延伸領域の間に挟まれた部分の表面上に、前記ゲート絶縁膜を介して配置される第3のゲート電極と、
前記第3のゲート電極の表面に配置される前記層間絶縁膜と、をさらに備え、
前記第3のゲート電極は、前記第1のゲート電極と前記第2のゲート電極とを連結することを特徴とする請求項5に記載の半導体装置。 - 前記第2導電型高濃度領域の前記第2方向の幅は、前記第2導電型コンタクト領域の前記第2方向の幅より広いことを特徴とする請求項1〜6いずれか一つに記載の半導体装置。
- 前記第2のゲート電極の前記第2方向の幅は、前記第1のゲート電極の前記第2方向の幅より狭いことを特徴とする請求項2、3、5、6のいずれか一つに記載の半導体装置。
- 前記層間絶縁膜を挟んで前記ゲートパッド電極と対向する部分全体に前記第2のゲート電極が配置されていることを特徴とする請求項2、3、5、6のいずれか一つに記載の半導体装置。
- 前記第2のゲート電極は、前記第1のゲート電極と電気的に絶縁されていることを特徴とする請求項2または5に記載の半導体装置。
- 前記pn並列カラムは、前記第1方向に平行なストライプ状の平面形状で、前記第1導電型カラムと前記第2導電型カラムとが繰り返し交互に配置されてなることを特徴とする請求項1〜3のいずれか一つに記載の半導体装置。
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