JP6128756B2 - 半導体パッケージ、積層型半導体パッケージ及びプリント回路板 - Google Patents
半導体パッケージ、積層型半導体パッケージ及びプリント回路板 Download PDFInfo
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Description
図1は、本発明の第1実施形態に係る積層型半導体パッケージを有するプリント回路板の概略構成を示す断面図である。プリント回路板500は、積層型半導体パッケージ300と、積層型半導体パッケージ300を実装したマザーボード400とを備えている。積層型半導体パッケージ300とマザーボード400とは、複数の下段はんだボール320により接合されている。
次に、本発明の第2実施形態に係る積層型半導体パッケージについて説明する。図4は本発明の第2実施形態に係る積層型半導体パッケージの要部の断面図である。この図4は、上段半導体パッケージと上段半導体パッケージとを接続する領域を拡大表示したものである。なお、本第2実施形態において、上記第1実施形態と同様の構成については、同一符号を付して説明を省略する。
本実施例では、上記第1実施形態の積層型半導体パッケージ300の構成において、各構成要素を下記の寸法としてシミュレーションを行った。
比較のために、図6における半導体パッケージの第1伝送路及び第2伝送路の特性差をシミュレートした。比較例の各ランド131a,131bは、同一の径とした。第1ランド131a及び第2ランド131bの径は330μmとし、それ以外は実施例と同じ値としている。図3にこのシミュレーション結果を併記した。伝送路特性の差は31.2%であり、許容差以上となっている。また、比較例における迂回する配線の長さは、102.5μm(径330μm)であった。
Claims (7)
- 多層のプリント配線板と、
第1信号端子及び第2信号端子を有し、前記プリント配線板に実装された半導体素子と、を備え、
前記プリント配線板は、
表層に形成されたはんだ接合用の第1ランド及び第2ランドと、
前記半導体素子の第1信号端子と前記第1ランドとを電気的に接続する第1配線と、
前記半導体素子の第2信号端子と前記第2ランドとを電気的に接続する、前記第1配線よりも配線長が長い第2配線と、を有し、
前記第1配線と前記第2配線の配線長の差による伝送特性の差を、寄生キャパシタンスの差により低減するように、
前記第2ランドの表面は、前記第1ランドの表面よりも面積が大きく、
前記第2ランドと前記第1ランドは、絶縁層を介してグラウンドパターンと対向するように配置されていることを特徴とする半導体パッケージ。 - 前記プリント配線板は、前記表層に形成されたソルダーレジストを有し、
前記ソルダーレジストには、前記第1ランドの表面を露出させる第1開口と、前記第2ランドの表面を露出させる、前記第1開口よりも開口面積が大きい第2開口とが形成されており、
前記第2開口に接続するはんだボールの径は、前記第1開口に接続するはんだボールの径よりも大きいことを特徴とする請求項1に記載の半導体パッケージ。 - 前記第1信号端子及び前記第2信号端子は、データ信号を出力する端子であり、
前記第1配線及び前記第2配線は、データ信号の伝送に用いる配線であることを特徴とする請求項1又は2に記載の半導体パッケージ。 - 前記第1信号端子及び前記第2信号端子は、ストローブ信号を出力する端子であり、
前記第1配線及び前記第2配線は、ストローブ信号の伝送に用いる配線であることを特徴とする請求項1又は2に記載の半導体パッケージ。 - 請求項1乃至4のいずれか1項に記載の半導体パッケージと、
前記半導体パッケージが実装されたマザーボードと、を備えたことを特徴とするプリント回路板。 - 多層の第1プリント配線板及び前記第1プリント配線板に実装された第1半導体素子を有する第1半導体パッケージと、
第2プリント配線板及び前記第2プリント配線板に実装された第2半導体素子を有し、前記第1半導体パッケージに積層された第2半導体パッケージと、を備え、
前記第1プリント配線板は、
表層に形成され、前記第2プリント配線板の各ランドにそれぞれはんだで接合された第1ランド及び第2ランドと、
前記第1半導体素子の第1信号端子と前記第1ランドとを電気的に接続する第1配線と、
前記第1半導体素子の第2信号端子と前記第2ランドとを電気的に接続する、前記第1配線よりも配線長が長い第2配線と、を有し、
前記第1配線と前記第2配線の配線長の差による伝送特性の差を、寄生キャパシタンスの差により低減するように、
前記第2ランドの表面は、前記第1ランドの表面よりも面積が大きく、
前記第2ランドと前記第1ランドは、絶縁層を介してグラウンドパターンと対向するように配置されていることを特徴とする積層型半導体パッケージ。 - 請求項6に記載の積層型半導体パッケージと、
前記積層型半導体パッケージが実装されたマザーボードと、を備えたことを特徴とするプリント回路板。
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JP2012122975A JP6128756B2 (ja) | 2012-05-30 | 2012-05-30 | 半導体パッケージ、積層型半導体パッケージ及びプリント回路板 |
US13/892,538 US8803329B2 (en) | 2012-05-30 | 2013-05-13 | Semiconductor package and stacked semiconductor package |
EP13168859.0A EP2669944A3 (en) | 2012-05-30 | 2013-05-23 | Semiconductor package and stacked semiconductor package |
CN201310199603.4A CN103458611B (zh) | 2012-05-30 | 2013-05-27 | 层叠型半导体封装、印刷布线板和印刷电路板 |
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KR102339899B1 (ko) | 2014-12-12 | 2021-12-15 | 삼성전자주식회사 | 반도체 패키지, 모듈 기판 및 이를 포함하는 반도체 패키지 모듈 |
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JP3016380B2 (ja) * | 1997-07-04 | 2000-03-06 | 日本電気株式会社 | 半導体装置 |
JP3846611B2 (ja) * | 1998-09-25 | 2006-11-15 | ソニー株式会社 | 実装用半導体部品、実装構造及び実装方法 |
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KR100574954B1 (ko) * | 2003-11-15 | 2006-04-28 | 삼성전자주식회사 | 중앙부 패드와 재 배선된 패드에서 와이어 본딩된집적회로 칩패키지 |
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