JP6125730B2 - 半導体素子を選択的にトランスファーする方法 - Google Patents
半導体素子を選択的にトランスファーする方法 Download PDFInfo
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- JP6125730B2 JP6125730B2 JP2016530289A JP2016530289A JP6125730B2 JP 6125730 B2 JP6125730 B2 JP 6125730B2 JP 2016530289 A JP2016530289 A JP 2016530289A JP 2016530289 A JP2016530289 A JP 2016530289A JP 6125730 B2 JP6125730 B2 JP 6125730B2
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- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
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- H01L33/0093—Wafer bonding; Removal of the growth substrate
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Description
a.第一表面及び第二表面を有する基板を提供し;
b.前記第一表面に複数の半導体エピタキシャルスタック層を提供し、前記複数の半導体エピタキシャルスタック層は、第一半導体エピタキシャルスタック層及び第二半導体エピタキシャルスタック層を含み、前記第二半導体エピタキシャルスタック層と前記第一半導体エピタキシャルスタック層とは隔てれられ、前記第一半導体エピタキシャルスタック層と前記基板との間の粘着力は、前記第二半導体エピタキシャルスタック層と前記基板との間の粘着力とは異なり;及び
c.前記基板から前記第一半導体エピタキシャルスタック層又は前記第二半導体エピタキシャルスタック層を選択的に分離するステップを含む。
Claims (18)
- 半導体素子を選択的に分離する方法であって、
a.第一表面及び第二表面を有する基板を提供し;
b.前記第一表面に位置する複数の半導体エピタキシャルスタック層を提供し、そのうち、前記複数の半導体エピタキシャルスタック層は第一半導体エピタキシャルスタック層及び第二半導体エピタキシャルスタック層を含み、前記第一半導体エピタキシャルスタック層と前記第二半導体エピタキシャルスタック層は隔てられ、前記半導体エピタキシャルスタック層と前記基板との間には、粘着構造が設けられ、前記粘着構造は、粘着層及びエネルギーを印加することで粘着力が小さくなる犠牲層からなり、前記犠牲層は、前記第一半導体エピタキシャルスタック層に対応して形成され、前記犠牲層の上の前記第一半導体エピタキシャルスタック層の上には、粘着媒体が設けられ、前記犠牲層と前記粘着媒体との粘着力は異なり;及び
c.前記基板から前記第一半導体エピタキシャルスタック層又は前記第二半導体エピタキシャルスタック層を選択的に分離するステップを含む、方法。 - 請求項1に記載の方法であって、
前記エネルギーは紫外線、レーザー光又は加熱によるものを含む、方法。 - 請求項1に記載の方法であって、
前記cステップは更に前記粘着構造を除去することを含む、方法。 - 請求項1に記載の方法であって、
前記犠牲層と前記粘着層との材料は異なる、方法。 - 請求項4に記載の方法であって、
前記粘着層は前記犠牲層と前記第一半導体エピタキシャルスタック層との間に形成され、前記犠牲層は前記第一表面と接する、方法。 - 請求項4に記載の方法であって、
前記犠牲層は前記粘着層と前記第一半導体エピタキシャルスタック層との間に形成され、前記犠牲層は前記第一半導体エピタキシャルスタック層と接する、方法。 - 請求項4に記載の方法であって、
前記犠牲層は前記第一表面及び前記第一半導体エピタキシャルスタック層と接する、方法。 - 請求項4に記載の方法であって、
前記犠牲層の厚みは10μm以下且つ1μm以上である、方法。 - 請求項1に記載の方法であって、更に、
前記第一半導体エピタキシャルスタック層と粘着される選択素子を提供し、前記選択素子により前記第一半導体エピタキシャルスタック層と前記基板とを分離することを含む、方法。 - 請求項9に記載の方法であって、
前記第一半導体エピタキシャルスタック層と前記選択素子との間には前記粘着媒体を有する、方法。 - 請求項10に記載の方法であって、
前記選択素子は前記第二半導体エピタキシャルスタック層と間隙を以て隔てられる、方法。 - 請求項10に記載の方法であって、
前記粘着媒体は導電材料を含む、方法。 - 請求項9に記載の方法であって、
前記選択素子は導電基板又はプリント回路板を含む、方法。 - 請求項9に記載の方法であって、
前記選択素子は支持構造と該支持構造に位置するフレキシブル基板とを含む、方法。 - 請求項14に記載の方法であって、
前記cステップの後に、前記フレキシブル基板を前記支持構造から分離することを更に含む、方法。 - 請求項1に記載の方法であって、
前記bステップは、前記半導体エピタキシャルスタック層を成長基板に成長させ;前記粘着構造を以て前記半導体エピタキシャルスタック層を前記第一表面に粘着させ;前記成長基板を除去し;及び、前記半導体エピタキシャルスタック層及び前記粘着構造をパターン化して前記複数の半導体エピタキシャルスタック層を形成することを含む、方法。
- 請求項1に記載の方法であって、
前記第一半導体エピタキシャルスタック層の上面図における面積は前記第二半導体エピタキシャルスタック層の上面図における面積よりも小さい、方法。 - 請求項3に記載の方法であって、
前記cステップは、前記粘着構造の除去時間を制御し、前記第二半導体エピタキシャルスタック層と前記基板との間に一部の前記粘着構造を残し、前記第一半導体エピタキシャルスタック層と前記基板との間の前記粘着構造を完全に除去することを含む、方法。
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