JP5968046B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents
Semiconductor device and manufacturing method of semiconductor device Download PDFInfo
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- JP5968046B2 JP5968046B2 JP2012100634A JP2012100634A JP5968046B2 JP 5968046 B2 JP5968046 B2 JP 5968046B2 JP 2012100634 A JP2012100634 A JP 2012100634A JP 2012100634 A JP2012100634 A JP 2012100634A JP 5968046 B2 JP5968046 B2 JP 5968046B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Description
この発明は、半導体装置に関わり、特に部材の接合に焼結銀を用いた半導体装置に関するものである。 The present invention relates to a semiconductor device, and more particularly to a semiconductor device using sintered silver for joining members.
高温動作する半導体素子の接合方法として、ナノ（またはマイクロ）銀粒子ペーストによる焼結接合が広く検討されている。しかしながら銀はマイグレーション感受性が高いことで知られている。接合体の耐マイグレーション性を向上させるために、接合体に添加元素を加え、銀を合金化する方法が検討されている（例えば特許文献１）。 As a method for bonding semiconductor elements that operate at high temperatures, sintered bonding using nano (or micro) silver particle paste has been widely studied. However, silver is known for its high migration sensitivity. In order to improve the migration resistance of the joined body, a method of adding an additive element to the joined body and alloying silver has been studied (for example, Patent Document 1).
銀にCu，Pd，Pt，Auなどの添加元素を加えて合金化することにより耐マイグレーション性が向上することは一般的に知られているが、接合体に不純物を添加するため、本来、焼結銀が有する放熱性は低下する。このため、本発明は、銀粒子ペーストによる焼結接合において、放熱性の向上を目的にしている。 Although it is generally known that migration resistance is improved by adding an additive element such as Cu, Pd, Pt, or Au to silver to improve the resistance to migration. The heat dissipating property of silver is reduced. For this reason, this invention aims at the improvement of heat dissipation in the sintering joining by a silver particle paste.
この発明に係わる半導体装置は、金属製のベース板と、両面に金属膜が形成されていて、一方の金属膜がベース板にはんだ層を介在して接合されている絶縁基板と、絶縁基板のもう一方の金属膜の上に形成された第１の金層と、第２の金層が形成されていて、焼結銀層を介在して第１の金層に接合されている半導体チップと、焼結銀層の周りに形成されていて、はんだと銀からなる合金部と、合金部の周りに形成されていて、はんだの溶融物が固化してなる溶融はんだ部を備え、焼結銀層の面積と合金部の面積と溶融はんだ部の面積の和は、絶縁基板の面積よりも小さい。 A semiconductor device according to the present invention includes a metal base plate, an insulating substrate in which a metal film is formed on both surfaces, and one metal film is bonded to the base plate with a solder layer interposed therebetween, and an insulating substrate A first gold layer formed on the other metal film; a semiconductor chip on which a second gold layer is formed and bonded to the first gold layer with a sintered silver layer interposed therebetween; The sintered silver layer is formed around the sintered silver layer, and includes an alloy portion made of solder and silver, and a molten solder portion formed around the alloy portion and solidified by a melt of the solder. The sum of the area of the layer, the area of the alloy part, and the area of the molten solder part is smaller than the area of the insulating substrate.
半導体チップの直下部分の接合体が純銀成分のため放熱性を低下させることなく耐マイグレーション性が向上する。 Since the joined body immediately below the semiconductor chip is a pure silver component, the migration resistance is improved without deteriorating heat dissipation.
以下に本発明にかかる半導体装置およびその製造方法の実施の形態を図面に基づいて詳細に説明する。なお、本発明は以下の記述に限定されるものではなく、本発明の要旨を逸脱しない範囲において適宜変更可能である。 Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below in detail with reference to the drawings. In addition, this invention is not limited to the following description, In the range which does not deviate from the summary of this invention, it can change suitably.
実施の形態１．
図１に、本願に関わる半導体装置の全体構成を示す。パッケージタイプの半導体装置１００は、半導体チップ１、電極付きセラミックス基板３、ベース板６、ワイヤボンド２２、外部リード１４、モールド樹脂１５などから構成されている。半導体チップ１、電極付きセラミックス基板３、ベース板６、ワイヤボンド２２はモールド樹脂１５で樹脂封止されている。半導体装置１００は、ボンディングの終わった半導体チップを金型にセットして、熱硬化性の樹脂を流し込んで成形される。
Embodiment 1 FIG.
FIG. 1 shows an overall configuration of a semiconductor device according to the present application. The package type semiconductor device 100 includes a semiconductor chip 1, a ceramic substrate with electrodes 3, a base plate 6, wire bonds 22, external leads 14, a mold resin 15, and the like. The semiconductor chip 1, the electrode-attached ceramic substrate 3, the base plate 6, and the wire bond 22 are resin-sealed with a mold resin 15. The semiconductor device 100 is molded by setting a bonded semiconductor chip in a mold and pouring a thermosetting resin.
図２に、本願に関わる半導体装置の別形態を示す。ケースタイプの半導体装置２００は、半導体チップ１、電極付きセラミックス基板３、ベース板６、ワイヤボンド２２、外部リード１４、ケース３１、蓋３２などから構成されている。半導体チップ１、電極付きセラミックス基板３、ベース板６、ワイヤボンド２２は封止樹脂３３で樹脂封止されている。半導体装置２００は、ベース付け、ケース付け、ボンディングの終わった半導体チップに熱硬化性の樹脂を流し込んで成形される。 FIG. 2 shows another embodiment of the semiconductor device according to the present application. The case type semiconductor device 200 includes a semiconductor chip 1, a ceramic substrate 3 with electrodes, a base plate 6, wire bonds 22, external leads 14, a case 31, a lid 32, and the like. The semiconductor chip 1, the electrode-attached ceramic substrate 3, the base plate 6, and the wire bond 22 are sealed with a sealing resin 33. The semiconductor device 200 is formed by pouring a thermosetting resin into a semiconductor chip after base attachment, case attachment, and bonding.
図３は本発明の実施の形態１に関わる半導体装置を得るための接合工程を示す模式図である。半導体チップ１と電極付きセラミックス基板３は焼結銀層２を介して接合されている。半導体チップ（厚さ0.3mm）１には5mm角の大きさのものを用いている。電極付きセラミックス基板３は、銅電極とSi3N4基板から構成されている。銅電極３ａと銅電極３ｃは10mm角のSi3N4基板（厚さ0.5mm）３ｂにロウ付け処理されている。半導体チップ１と電極
付きセラミックス基板３は、マイクロ（またはナノ）銀粒子を含む焼結型銀ペースト２０を使って接合される。
FIG. 3 is a schematic diagram showing a bonding process for obtaining the semiconductor device according to the first embodiment of the present invention. The semiconductor chip 1 and the electrode-attached ceramic substrate 3 are joined via the sintered silver layer 2. A semiconductor chip (thickness 0.3 mm) 1 having a size of 5 mm square is used. The ceramic substrate 3 with an electrode is composed of a copper electrode and a Si3N4 substrate. The copper electrode 3a and the copper electrode 3c are brazed to a 10 mm square Si3N4 substrate (thickness 0.5 mm) 3b. The semiconductor chip 1 and the electrode-attached ceramic substrate 3 are bonded using a sintered silver paste 20 containing micro (or nano) silver particles.
焼結型銀ペースト２０は、半導体チップ１から露出するように、電極付きセラミックス基板３に塗布する。焼結型銀ペースト２０の印刷サイズは、6mm×6mmとし、意図的に半導体チップ１のチップサイズより大きくし、かつ電極付きセラミックス基板３のサイズより小さくする。このため電極付きセラミックス基板３には周囲に余白が残されている。焼結型銀ペースト２０を塗布後、半導体チップ１と電極付きセラミックス基板３は張り合わされる。張り合わした半導体チップ１と電極付きセラミックス基板３は昇温され、焼結が完了する。焼結銀層２の厚みは10μm〜100μmとした。 The sintered silver paste 20 is applied to the electrode-attached ceramic substrate 3 so as to be exposed from the semiconductor chip 1. The printing size of the sintered silver paste 20 is 6 mm × 6 mm, intentionally larger than the chip size of the semiconductor chip 1 and smaller than the size of the ceramic substrate 3 with electrode. For this reason, a margin is left around the ceramic substrate 3 with electrodes. After applying the sintered silver paste 20, the semiconductor chip 1 and the electrode-attached ceramic substrate 3 are bonded together. The bonded semiconductor chip 1 and electrode-attached ceramic substrate 3 are heated to complete the sintering. The thickness of the sintered silver layer 2 was 10 μm to 100 μm.
半導体チップ１は、珪素（Ｓｉ）によって形成したものの他、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって形成したものも好適に使用することができる。ワイドバンドギャップ半導体としては、例えば、炭化珪素（ＳｉＣ）、窒化ガリウム系材料またはダイヤモンドがある。ワイドバンドギャップ半導体を用いた場合、許容電流密度が高く、電力損失も低いため、電力用半導体素子を用いた装置の小型化が可能となる。 As the semiconductor chip 1, in addition to those formed of silicon (Si), those formed of a wide band gap semiconductor having a band gap larger than that of silicon can be suitably used. Examples of the wide band gap semiconductor include silicon carbide (SiC), a gallium nitride material, and diamond. When a wide bandgap semiconductor is used, the allowable current density is high and the power loss is low, so that a device using the power semiconductor element can be downsized.
次に図４のように半導体チップ１が接合された電極付きセラミックス基板３に、厚さ0.1mmtのはんだ枠４を半導体チップ１が内枠内に収まるようにかぶせる。マウント時にはんだ枠４の内側が半導体チップ１の側面に接触しないように、はんだ枠４には開口部２１を設ける。はんだ枠４の内枠寸法は5.3mm×5.3mm、外枠寸法は7mm×7mmとした。はんだ枠４は、Snを主成分とする鉛フリーのはんだペレットで構成し、Ag、Cu、Sb、In、Ni、Bi、Znなどを含む。鉛フリーはんだの代表例にはSn3銀0.5Cuを挙げることが出来る。はんだ枠４は、焼結銀層２の表面と接触するが半導体チップ１の外周には接触しない。 Next, as shown in FIG. 4, a 0.1 mm-thick solder frame 4 is placed on the ceramic substrate 3 with electrodes to which the semiconductor chip 1 is bonded so that the semiconductor chip 1 fits in the inner frame. An opening 21 is provided in the solder frame 4 so that the inner side of the solder frame 4 does not contact the side surface of the semiconductor chip 1 during mounting. The inner frame size of the solder frame 4 was 5.3 mm × 5.3 mm, and the outer frame size was 7 mm × 7 mm. The solder frame 4 is composed of lead-free solder pellets containing Sn as a main component, and includes Ag, Cu, Sb, In, Ni, Bi, Zn, and the like. A typical example of lead-free solder is Sn3 silver 0.5Cu. The solder frame 4 contacts the surface of the sintered silver layer 2 but does not contact the outer periphery of the semiconductor chip 1.
次にはんだ枠４と同程度の融点を有するはんだペレット５をベース板６にマウントし、その上にはんだ枠４がマウントされている電極付きセラミックス基板３をマウントする。はんだペレット５は、Snを主成分とする鉛フリーはんだで構成し、Ag、Cu、Sb、In、Ni、Bi、Znなどを含む。 Next, a solder pellet 5 having a melting point similar to that of the solder frame 4 is mounted on the base plate 6, and the electrode-attached ceramic substrate 3 on which the solder frame 4 is mounted is mounted thereon. The solder pellet 5 is made of lead-free solder containing Sn as a main component, and includes Ag, Cu, Sb, In, Ni, Bi, Zn, and the like.
次に半導体チップ１と電極付きセラミックス基板３とベース板６の一体物を還元性雰囲気でリフロー処理する。はんだペレット５が溶融し電極付きセラミックス基板３とベース板６とのはんだ接合が実行されベース板接合部７が形成される。同時に、半導体チップの外周部のはんだ枠４が溶融する。これにより、焼結銀層２のうち半導体チップ１から露出している部分は合金化して合金部８が形成される。半導体チップ１の内側の部分は外部と遮断された状態となる。この外部から遮断された部分は純銀からなる焼結銀で構成されている。還元性雰囲気は、電極付きセラミックス基板３とベース板６とのはんだ接合に有効であるとともに、はんだ枠４の溶融時にはんだの焼結銀への濡れ性を向上させる。リフロー後のベース板をモジュール用ケースに取り付け、ワイヤボンドを結線し、半導体装置を作製する。 Next, the integrated body of the semiconductor chip 1, the electrode-attached ceramic substrate 3 and the base plate 6 is reflowed in a reducing atmosphere. The solder pellets 5 are melted, and solder joining between the ceramic substrate 3 with electrode and the base plate 6 is executed to form the base plate joint 7. At the same time, the solder frame 4 on the outer periphery of the semiconductor chip is melted. As a result, a portion of the sintered silver layer 2 exposed from the semiconductor chip 1 is alloyed to form an alloy portion 8. The inner part of the semiconductor chip 1 is cut off from the outside. The portion cut off from the outside is composed of sintered silver made of pure silver. The reducing atmosphere is effective for solder joining between the ceramic substrate 3 with electrode and the base plate 6 and improves the wettability of the solder to the sintered silver when the solder frame 4 is melted. The base plate after reflow is attached to the module case, and wire bonds are connected to manufacture a semiconductor device.
次に比較例となる半導体装置の作成方法を説明する。合金粉末（Ag-20%Pd）を接合材として、5mm角の半導体チップ（厚さ0.3mm）を、両面に銅電極がロウ付け処理された10mm角のSi3N4セラミックス基板（厚さ0.5mm）と接合した。チップ接合されたセラミックス基板をはんだペレットを用い、還元性雰囲気でリフロー処理し、ベース板と接合した。リフロー後のベース板をモジュール用ケースに取り付け、ワイヤボンドを結線し、半導体装置の比較サンプル１を作製した。 Next, a method for manufacturing a semiconductor device as a comparative example will be described. With alloy powder (Ag-20% Pd) as a bonding material, a 5mm square semiconductor chip (thickness 0.3mm) and a 10mm square Si3N4 ceramic substrate (thickness 0.5mm) with copper electrodes brazed on both sides Joined. The chip-bonded ceramic substrate was reflowed in a reducing atmosphere using solder pellets and bonded to the base plate. The base plate after the reflow was attached to the module case, and wire bonds were connected to produce a comparative sample 1 of the semiconductor device.
２つのサンプルをパワーサイクル試験にかけて、チップ表面の到達温度をサーモビュアーで計測した。その結果、実施の形態１にかかわる半導体装置のチップ表面の温度は比較サンプル１よりも５℃低い結果となった。以上のように本発明によれば、半導体装置の放熱性を維持したまま、耐マイグレーション性を向上させることができる。 Two samples were subjected to a power cycle test, and the temperature reached on the chip surface was measured with a thermoviewer. As a result, the temperature of the chip surface of the semiconductor device according to the first embodiment was 5 ° C. lower than that of the comparative sample 1. As described above, according to the present invention, it is possible to improve the migration resistance while maintaining the heat dissipation of the semiconductor device.
実施の形態２．
図５は本発明の実施の形態２に関わる半導体装置を得るための接合工程を示す模式図である。接合された半導体チップ１と電極付きセラミックス基板３を鉛フリーのはんだペレット５を介在させてベース板６に載置する。はんだペレット５と同程度の融点を有する厚さ0.1mmtのはんだ枠４を、半導体チップ１が内枠内に収まるようにマウントする。次に半導体チップ１と電極付きセラミックス基板３とベース板６の一体物を還元性雰囲気でリフロー処理する。実施の形態２によれば、実施の形態１と同様に、半導体装置の放熱性を維持したまま、耐マイグレーション性を向上させることができる。
Embodiment 2. FIG.
FIG. 5 is a schematic diagram showing a bonding process for obtaining a semiconductor device according to the second embodiment of the present invention. The bonded semiconductor chip 1 and ceramic substrate 3 with electrodes are placed on the base plate 6 with lead-free solder pellets 5 interposed. A 0.1 mm thick solder frame 4 having the same melting point as that of the solder pellet 5 is mounted so that the semiconductor chip 1 can be accommodated in the inner frame. Next, the integrated body of the semiconductor chip 1, the electrode-attached ceramic substrate 3 and the base plate 6 is subjected to a reflow process in a reducing atmosphere. According to the second embodiment, as in the first embodiment, it is possible to improve the migration resistance while maintaining the heat dissipation of the semiconductor device.
実施の形態３．
図６は本発明の実施の形態３に関わる半導体装置を得るための接合工程を示す模式図である。半導体チップ（厚さ0.3mm）１は、5mm角のものを用い、裏面にAuメタライズ層１２を形成する。電極付きセラミックス基板３は、10mm角のSi3N4基板（厚さ0.5mm）の両面に銅電極３ａと銅電極３ｃをロウ付け処理した構造を有している。銅電極３ａの接合領域付近には厚さ１μmのAuめっき層９を形成する。Auめっき層９の面積は半導体チップ１の面
積よりも大きいが、電極付きセラミックス基板３の面積よりも小さいため、極付きセラミックス基板３の周囲には余白が残されている。半導体チップ１と電極付きセラミックス基板３はマイクロ（またはナノ）銀粒子を含む焼結型銀ペーストを用いて張り合わせる。焼結型銀ペーストの印刷サイズは、焼結銀層２が半導体チップ１の内側に収まるように4.8mm×4.8mmとした。焼結銀層２の厚みは10〜100μmとした。
Embodiment 3 FIG.
FIG. 6 is a schematic view showing a bonding process for obtaining a semiconductor device according to the third embodiment of the present invention. A semiconductor chip (thickness 0.3 mm) 1 is 5 mm square, and an Au metallized layer 12 is formed on the back surface. The ceramic substrate 3 with an electrode has a structure in which a copper electrode 3a and a copper electrode 3c are brazed on both sides of a 10 mm square Si3N4 substrate (thickness 0.5 mm). An Au plating layer 9 having a thickness of 1 μm is formed in the vicinity of the bonding region of the copper electrode 3a. Although the area of the Au plating layer 9 is larger than the area of the semiconductor chip 1 but smaller than the area of the electrode-attached ceramic substrate 3, a blank is left around the electrode-attached ceramic substrate 3. The semiconductor chip 1 and the electrode-attached ceramic substrate 3 are bonded together using a sintered silver paste containing micro (or nano) silver particles. The printing size of the sintered silver paste was set to 4.8 mm × 4.8 mm so that the sintered silver layer 2 fits inside the semiconductor chip 1. The thickness of the sintered silver layer 2 was 10 to 100 μm.
次に半導体チップ１が接合された電極付きセラミックス基板３に、厚さ0.1mmtの鉛フリーはんだで構成されるはんだ枠４を半導体チップ１が内枠内に収まるようにマウントする（図７参照）。はんだ枠４の大きさは、マウント時に半導体チップの側面に接触しないように内枠5.3mm×5.3mm、外枠7mm×7mmとした。はんだ枠４は、Snを主成分とするペレット状はんだで構成され、Ag、Cu、Sb、In、Ni、Bi、Znなどを含む。 Next, a solder frame 4 made of lead-free solder having a thickness of 0.1 mm is mounted on the electrode-attached ceramic substrate 3 to which the semiconductor chip 1 is bonded so that the semiconductor chip 1 fits in the inner frame (see FIG. 7). . The size of the solder frame 4 was set to 5.3 mm × 5.3 mm for the inner frame and 7 mm × 7 mm for the outer frame so as not to contact the side surface of the semiconductor chip during mounting. The solder frame 4 is composed of pelletized solder containing Sn as a main component, and includes Ag, Cu, Sb, In, Ni, Bi, Zn, and the like.
次にはんだ枠４と同程度の融点を有する鉛フリーのはんだペレット５をベース板６にマウントし、さらに、その上にチップ接合され且つはんだ枠４がマウントされている電極付きセラミックス基板３をマウントする。はんだペレット５は、Snを主成分とし、Ag、Cu、Sb、In、Ni、Bi、Znなどを含む。 Next, a lead-free solder pellet 5 having a melting point similar to that of the solder frame 4 is mounted on the base plate 6, and the ceramic substrate 3 with an electrode on which the chip frame is bonded and the solder frame 4 is mounted is mounted thereon. To do. The solder pellet 5 is mainly composed of Sn and contains Ag, Cu, Sb, In, Ni, Bi, Zn, and the like.
次にベース板を還元性雰囲気でリフロー処理し、電極付きセラミックス基板３とベース板６のはんだ接合を実行するとともに半導体チップ１の外周部のはんだを溶融し、半導体チップの外周部をはんだで被覆する。リフロー後のベース板６をモジュール用ケースに取り付け、ワイヤボンドで結線し、実施の形態３に関わる半導体装置を作製する。 Next, the base plate is subjected to reflow treatment in a reducing atmosphere, soldering of the ceramic substrate 3 with electrode and the base plate 6 is performed, the solder on the outer periphery of the semiconductor chip 1 is melted, and the outer periphery of the semiconductor chip is covered with the solder To do. The base plate 6 after reflow is attached to the module case and connected by wire bonding, and the semiconductor device according to the third embodiment is manufactured.
比較例となる半導体装置の作成方法を説明する。両面に銅電極がロウ付け処理された、10mm角のセラミックス基板（Si3N4；厚さ0.5mm）に、厚さ1μmの部分Auめっきを基板の接合領域に施した。合金粉末（Ag-20%Pd）を接合材として、5mm角の半導体チップ（厚さ0.3mm）をセラミックス基板に接合した。チップ接合されたセラミックス基板をはんだペレットを用い、還元性雰囲気でリフロー処理し、ベース板と接合した。リフロー後のベース板をモジュール用ケースに取り付け、ワイヤボンド結線し、半導体装置の比較サンプル２を作製した。 A method for manufacturing a semiconductor device as a comparative example will be described. A 10-mm square ceramic substrate (Si3N4; thickness 0.5 mm) with copper electrodes brazed on both sides was subjected to partial Au plating with a thickness of 1 μm in the bonding area of the substrate. A 5 mm square semiconductor chip (thickness 0.3 mm) was bonded to the ceramic substrate using the alloy powder (Ag-20% Pd) as a bonding material. The chip-bonded ceramic substrate was reflowed in a reducing atmosphere using solder pellets and bonded to the base plate. The base plate after reflow was attached to the module case and wire-bonded to produce a comparative sample 2 of the semiconductor device.
２つのサンプルをパワーサイクル試験にかけて、チップ表面の到達温度をサーモビュアーで計測した。その結果、実施の形態３に関わる半導体装置のチップ表面の温度は、比較サンプル２よりも５℃低い結果となった。以上のように本発明によれば、半導体装置の放熱性を維持したまま、耐マイグレーション性を向上させることができる。 Two samples were subjected to a power cycle test, and the temperature reached on the chip surface was measured with a thermoviewer. As a result, the temperature of the chip surface of the semiconductor device according to the third embodiment was 5 ° C. lower than that of the comparative sample 2. As described above, according to the present invention, it is possible to improve the migration resistance while maintaining the heat dissipation of the semiconductor device.
実施の形態のメカニズムについて以下に補足説明する。接合領域に施されたAuめっき層９により、焼結銀の存在しない未接合領域の濡れ性が向上する。この効果により、溶融はんだは半導体チップ１と電極付きセラミックス基板３の間隙に導かれる。溶融はんだは容易に半導体チップ内の焼結銀層２に到達し、チップ内に収められた焼結銀の界面近傍で焼結銀と固溶し、組成Sn/Agを有する合金部８が形成される。半導体チップの裏面のAuメタ
ライズ層１２により、溶融はんだはチップ内の焼結銀層２に到達した後、チップ裏面のAuメタライズ層１２に達し、濡れ広がり、半導体チップと電極付きセラミックス基板の間隙を完全に埋める。半導体チップの外周部分は、銀と合金化していない溶融はんだ部１０により被覆される。
The mechanism of the embodiment will be supplementarily described below. The Au plating layer 9 applied to the bonded region improves the wettability of the unbonded region where no sintered silver is present. Due to this effect, the molten solder is guided to the gap between the semiconductor chip 1 and the electrode-attached ceramic substrate 3. The molten solder easily reaches the sintered silver layer 2 in the semiconductor chip and is solid-solved with the sintered silver near the interface of the sintered silver contained in the chip to form an alloy part 8 having the composition Sn / Ag. Is done. By the Au metallized layer 12 on the back surface of the semiconductor chip, the molten solder reaches the sintered silver layer 2 in the chip, and then reaches the Au metallized layer 12 on the back surface of the chip, soaking and spreading. Fill completely. The outer peripheral portion of the semiconductor chip is covered with a molten solder portion 10 that is not alloyed with silver.
このようにAuめっき層９は、半導体チップ１と電極付きセラミックス基板３との隙間を埋める効果が要求される。Auめっき層９を電極付きセラミックス基板３の全面に形成した場合、溶融はんだが導かれる方向が半導体チップ１の外側方向にも生じるため、隙間を埋めることが難しくなる。このことからAuめっき層９は部分めっきである必要がある。実施の形態３では、Auめっき層９のサイズをはんだ枠４と同サイズの7mm×7mmとした。Auめっき層９の厚みは、半導体チップ１を電極付きセラミックス基板３に接合する際の熱拡散の影響による濡れ性の低下を防止するため１μm以上は必要である。 Thus, the Au plating layer 9 is required to fill the gap between the semiconductor chip 1 and the electrode-attached ceramic substrate 3. When the Au plating layer 9 is formed on the entire surface of the ceramic substrate 3 with electrodes, the direction in which the molten solder is guided also occurs in the outer direction of the semiconductor chip 1, so that it becomes difficult to fill the gap. For this reason, the Au plating layer 9 needs to be partially plated. In the third embodiment, the size of the Au plating layer 9 is 7 mm × 7 mm which is the same size as the solder frame 4. The thickness of the Au plating layer 9 is required to be 1 μm or more in order to prevent a decrease in wettability due to the influence of thermal diffusion when the semiconductor chip 1 is bonded to the ceramic substrate 3 with electrodes.
実施の形態1、２では焼結銀層２が溶融はんだと合金化されつつも、断面構造的に半導
体チップ１の外側に存在する。一方、実施の形態３では焼結銀層２が完全に半導体チップ１の内側に収められているため、実施の形態1、２よりも、マイグレーションがより起こ
りにくい。また間隙がはんだで埋められているため、ヒートサイクル耐性を損なうことなく耐マイグレーション性の向上が見込める。
In the first and second embodiments, the sintered silver layer 2 exists outside the semiconductor chip 1 in a cross-sectional structure while being alloyed with the molten solder. On the other hand, since the sintered silver layer 2 is completely contained inside the semiconductor chip 1 in the third embodiment, migration is less likely to occur than in the first and second embodiments. In addition, since the gap is filled with solder, an improvement in migration resistance can be expected without impairing heat cycle resistance.
実施の形態４．
図８は本発明の実施の形態４に関わる半導体装置を得るための接合工程を示す模式図で
ある。実施の形態３と同様に半導体チップ１が接合された電極付きセラミックス基板３を鉛フリーのはんだペレット５を介在させてベース板６に載置する。はんだペレット５と同程度の融点を有する厚さ0.1mmtのはんだ枠４を半導体チップ１が内枠内に収まるようにマウントする。次に半導体チップ１と電極付きセラミックス基板３とベース板６の一体物を還元性雰囲気でリフロー処理する。実施の形態４によれば、実施の形態３と同様に、半導体装置の放熱性を維持したまま、耐マイグレーション性を向上させることができる。
Embodiment 4 FIG.
FIG. 8 is a schematic diagram showing a bonding process for obtaining a semiconductor device according to the fourth embodiment of the present invention. Similarly to the third embodiment, the electrode-attached ceramic substrate 3 to which the semiconductor chip 1 is bonded is placed on the base plate 6 with the lead-free solder pellets 5 interposed therebetween. A solder frame 4 having a melting point comparable to that of the solder pellet 5 and having a thickness of 0.1 mm is mounted so that the semiconductor chip 1 fits in the inner frame. Next, the integrated body of the semiconductor chip 1, the electrode-attached ceramic substrate 3 and the base plate 6 is subjected to a reflow process in a reducing atmosphere. According to the fourth embodiment, as in the third embodiment, the migration resistance can be improved while maintaining the heat dissipation of the semiconductor device.
半導体チップ１にＳｉＣを用いた場合、半導体装置１００、２００はその特徴を生かすべくＳｉの時と比較してより高温で動作させることになる。ＳｉＣデバイスを搭載する半導体装置においては、半導体装置としてより高い信頼性が求められるため、高信頼の半導体装置を実現するという本発明のメリットはより効果的なものとなる。 When SiC is used for the semiconductor chip 1, the semiconductor devices 100 and 200 are operated at a higher temperature than in the case of Si in order to take advantage of the characteristics. In a semiconductor device on which an SiC device is mounted, since higher reliability is required as a semiconductor device, the merit of the present invention for realizing a highly reliable semiconductor device becomes more effective.
なお、本発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。 It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.
１ 半導体チップ、２ 焼結銀層、３ 電極付きセラミックス基板、４ はんだ枠、５
はんだペレット、６ ベース板、７ ベース板接合部、８ 合金部、９ Auめっき層、１０ 溶融はんだ、１２ Auメタライズ層、２０ 焼結型銀ペースト、２１ 開口部、１００ 半導体装置、２００ 半導体装置
1 Semiconductor chip, 2 sintered silver layer, 3 ceramic substrate with electrodes, 4 solder frame, 5
Solder pellet, 6 base plate, 7 base plate joint, 8 alloy part, 9 Au plating layer, 10 molten solder, 12 Au metallized layer, 20 sintered silver paste, 21 opening, 100 semiconductor device, 200 semiconductor device
Claims (9)
両面に金属膜が形成されていて、一方の金属膜が前記ベース板にはんだ層を介在して接合されている絶縁基板と、
前記絶縁基板のもう一方の金属膜の上に形成された第１の金層と、
第２の金層が形成されていて、焼結銀層を介在して前記第１の金層に接合されている半導体チップと、
前記焼結銀層の周りに形成されていて、はんだと銀からなる合金部と、
前記合金部の周りに形成されていて、はんだの溶融物が固化してなる溶融はんだ部を備え、
前記焼結銀層の面積と前記合金部の面積と前記溶融はんだ部の面積の和は、前記絶縁基板の面積よりも小さいことを特徴とする半導体装置。 A metal base plate,
A metal film is formed on both surfaces, and one metal film is bonded to the base plate via a solder layer;
A first gold layer formed on the other metal film of the insulating substrate;
A semiconductor chip formed with a second gold layer and bonded to the first gold layer via a sintered silver layer;
Formed around the sintered silver layer, and an alloy portion made of solder and silver;
It is formed around the alloy part, and comprises a molten solder part formed by solidifying a solder melt,
The sum of the area of the sintered silver layer, the area of the alloy part, and the area of the molten solder part is smaller than the area of the insulating substrate.
前記第１工程で塗布された銀ペーストよりも面積が小さい半導体チップを用意し、前記半導体チップと前記絶縁基板を前記銀ペーストを介在させて張り合わせる第２工程と、
前記第２工程で張り合わされた絶縁基板と半導体チップを前記銀ペーストの焼結温度まで昇温し、前記絶縁基板と前記半導体チップとの接合体を得る第３工程と、
前記半導体チップよりも面積が大きくかつ前記銀ペーストよりも面積が小さい開口部が設けられているはんだ枠を前記第３工程で得られた接合体にかぶせる第４工程と、
前記第４工程ではんだ枠がかぶせられた接合体を金属製のベース板にはんだ層を介在させて載置し、前記接合体と前記ベース板との一体物を得る第５工程と、
前記第５工程で得られた接合体とベース板との一体物を加熱し、前記接合体と前記ベース板とを接合する第６工程とを備えていることを特徴とする半導体装置の製造方法。 A first step of applying a silver paste on one side of an insulating substrate having a metal film formed on both sides, leaving a margin around the periphery;
Preparing a semiconductor chip having a smaller area than the silver paste applied in the first step, and bonding the semiconductor chip and the insulating substrate with the silver paste interposed therebetween;
A third step of heating the insulating substrate and the semiconductor chip bonded together in the second step to a sintering temperature of the silver paste to obtain a bonded body of the insulating substrate and the semiconductor chip;
A fourth step of covering the joined body obtained in the third step with a solder frame having an opening larger in area than the semiconductor chip and smaller in area than the silver paste;
A fifth step of placing the joined body covered with the solder frame in the fourth step with a solder layer interposed on a metal base plate, and obtaining an integrated body of the joined body and the base plate;
A method for manufacturing a semiconductor device, comprising: a sixth step of heating an integrated body of the joined body and the base plate obtained in the fifth step and joining the joined body and the base plate. .
前記第１工程で塗布された銀ペーストよりも面積が小さい半導体チップを用意し、前記半導体チップと前記絶縁基板を前記銀ペーストを介在させて張り合わせる第２工程と、
前記第２工程で張り合わされた絶縁基板と半導体チップを前記銀ペーストの焼結温度まで昇温し、前記絶縁基板と前記半導体チップとの接合体を得る第３工程と、
はんだ層を介在させて前記第３工程で得られた接合体を金属製のベース板に載置し、前記接合体と前記ベース板との一体物を得る第４工程と、
前記半導体チップよりも面積が大きくかつ前記銀ペーストよりも面積が小さい開口部が設けられているはんだ枠を前記第４工程で得られる一体物にかぶせる第５工程と、
前記第５工程を経た接合体とベース板との一体物を加熱し、前記接合体と前記ベース板とを接合する第６工程とを備えていることを特徴とする半導体装置の製造方法。 A first step of applying a silver paste on one side of an insulating substrate having a metal film formed on both sides, leaving a margin around the periphery;
Preparing a semiconductor chip having a smaller area than the silver paste applied in the first step, and bonding the semiconductor chip and the insulating substrate with the silver paste interposed therebetween;
A third step of heating the insulating substrate and the semiconductor chip bonded together in the second step to a sintering temperature of the silver paste to obtain a bonded body of the insulating substrate and the semiconductor chip;
A fourth step of placing the joined body obtained in the third step with a solder layer interposed therebetween on a metal base plate to obtain an integrated body of the joined body and the base plate;
A fifth step of covering the integrated body obtained in the fourth step with a solder frame having an opening larger in area than the semiconductor chip and smaller in area than the silver paste;
A method of manufacturing a semiconductor device, comprising: a sixth step of heating an integrated body of the joined body and the base plate that has undergone the fifth step to join the joined body and the base plate.
前記第１工程で第１の金層が形成された絶縁基板と前記第１の金層よりも面積が小さく片面に第２の金層が形成されている半導体チップを、前記第１の金層と前記第２の金層を向き合わせて、かつ前記半導体チップよりも面積が小さい銀ペーストを介在させて、張り合わせる第２工程と、
前記第２工程で張り合わされた絶縁基板と半導体チップを前記銀ペーストの焼結温度まで昇温し、前記絶縁基板と前記半導体チップとの接合体を得る第３工程と、
前記半導体チップよりも面積が大きくかつ前記第１の金層よりも面積が小さい開口部が設けられているはんだ枠を前記第３工程で得られた接合体にかぶせる第４工程と、
前記第４工程ではんだ枠がかぶせられた接合体を金属製のベース板にはんだ層を介在させて載置し、前記接合体と前記ベース板との一体物を得る第５工程と、
前記第５工程で得られた接合体とベース板との一体物を加熱し、前記接合体と前記ベース板とを接合する第６工程とを備えていることを特徴とする半導体装置の製造方法。 A first step of forming a first gold layer on one side of an insulating substrate having a metal film formed on both sides, leaving a margin around it;
An insulating substrate on which the first gold layer is formed in the first step and a semiconductor chip having a smaller area than the first gold layer and a second gold layer formed on one side are formed on the first gold layer. And a second step of laminating the second gold layer facing each other and interposing a silver paste having a smaller area than the semiconductor chip,
A third step of heating the insulating substrate and the semiconductor chip bonded together in the second step to a sintering temperature of the silver paste to obtain a bonded body of the insulating substrate and the semiconductor chip;
A fourth step of covering the joined body obtained in the third step with a solder frame having an opening larger in area than the semiconductor chip and smaller in area than the first gold layer;
A fifth step of placing the joined body covered with the solder frame in the fourth step with a solder layer interposed on a metal base plate, and obtaining an integrated body of the joined body and the base plate;
A method for manufacturing a semiconductor device, comprising: a sixth step of heating an integrated body of the joined body and the base plate obtained in the fifth step and joining the joined body and the base plate. .
前記第１工程で第１の金層が形成された絶縁基板と前記第１の金層よりも面積が小さく片面に第２の金層が形成されている半導体チップを、前記第１の金層と前記第２の金層を向き合わせて、かつ前記半導体チップよりも面積が小さい銀ペーストを介在させて、張り合わせる第２工程と、
前記第２工程で張り合わされた絶縁基板と半導体チップを前記銀ペーストの焼結温度まで昇温し、前記絶縁基板と前記半導体チップとの接合体を得る第３工程と、
はんだ層を介在させて前記第３工程で得られた接合体を金属製のベース板に載置し、前記接合体と前記ベース板との一体物を得る第４工程と、
前記半導体チップよりも面積が大きくかつ前記第１の金層よりも面積が小さい開口部が設けられているはんだ枠を前記第４工程で得られる一体物の接合体にかぶせる第５工程と、前記第５工程を経た接合体とベース板との一体物を加熱し、前記接合体と前記ベース板とを接合する第６工程とを備えていることを特徴とする半導体装置の製造方法。 A first step of forming a first gold layer on one side of an insulating substrate having a metal film formed on both sides, leaving a margin around it;
An insulating substrate on which the first gold layer is formed in the first step and a semiconductor chip having a smaller area than the first gold layer and a second gold layer formed on one side are formed on the first gold layer. And a second step of laminating the second gold layer facing each other and interposing a silver paste having a smaller area than the semiconductor chip,
A third step of heating the insulating substrate and the semiconductor chip bonded together in the second step to a sintering temperature of the silver paste to obtain a bonded body of the insulating substrate and the semiconductor chip;
A fourth step of placing the joined body obtained in the third step with a solder layer interposed therebetween on a metal base plate to obtain an integrated body of the joined body and the base plate;
A fifth step in which a solder frame having an opening larger in area than the semiconductor chip and smaller in area than the first gold layer is placed on the unitary joint obtained in the fourth step; and A method of manufacturing a semiconductor device, comprising: a sixth step of heating an integrated body of the joined body and the base plate that has undergone the fifth step to join the joined body and the base plate.
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